stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.130383 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 130382890500 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 130382890500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 181123 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 190933 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 137045131 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 270196 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 951.39 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 172317810 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 181650743 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 247424 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 3866 # Number of read requests responded to by this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 1059280 # Total read bandwidth from this memory (bytes/s) 2511507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 838392 # Total read bandwidth from this memory (bytes/s) 2611507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1897672 # Total read bandwidth from this memory (bytes/s) 2711507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 1059280 # Instruction read bandwidth from this memory (bytes/s) 2811507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 1059280 # Instruction read bandwidth from this memory (bytes/s) 2911507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 1059280 # Total bandwidth to/from this memory (bytes/s) 3011507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 838392 # Total bandwidth to/from this memory (bytes/s) 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 1897672 # Total bandwidth to/from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.physmem.readReqs 3866 # Number of read requests accepted 3311507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3411507SCurtis.Dunham@arm.comsystem.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue 3511507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3611507SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM 3711507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3811507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3911507SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 247424 # Total read bytes from the system interface side 4011507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4111507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4211507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4311507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 305 # Per bank write bursts 4511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 217 # Per bank write bursts 4611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 135 # Per bank write bursts 4711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 313 # Per bank write bursts 4811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 306 # Per bank write bursts 4911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 305 # Per bank write bursts 5011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 273 # Per bank write bursts 5111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 222 # Per bank write bursts 5211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 248 # Per bank write bursts 5311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 218 # Per bank write bursts 5411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 295 # Per bank write bursts 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 200 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 183 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 218 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 224 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 204 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7711507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7811507SCurtis.Dunham@arm.comsystem.physmem.totGap 130382796000 # Total gap between requests 7911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 3866 # Read request sizes (log2) 8611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see 9411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see 9511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see 9611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 9711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 9811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 9911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 915 # Bytes accessed per row activation 19011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 268.939891 # Bytes accessed per row activation 19111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 176.781102 # Bytes accessed per row activation 19211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 276.529935 # Bytes accessed per row activation 19311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 273 29.84% 29.84% # Bytes accessed per row activation 19411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 347 37.92% 67.76% # Bytes accessed per row activation 19511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 83 9.07% 76.83% # Bytes accessed per row activation 19611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 59 6.45% 83.28% # Bytes accessed per row activation 19711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 35 3.83% 87.10% # Bytes accessed per row activation 19811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 24 2.62% 89.73% # Bytes accessed per row activation 19911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 16 1.75% 91.48% # Bytes accessed per row activation 20011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 20 2.19% 93.66% # Bytes accessed per row activation 20111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 58 6.34% 100.00% # Bytes accessed per row activation 20211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 915 # Bytes accessed per row activation 20311507SCurtis.Dunham@arm.comsystem.physmem.totQLat 27071500 # Total ticks spent queuing 20411507SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 99559000 # Total ticks spent from burst creation until serviced by the DRAM 20511507SCurtis.Dunham@arm.comsystem.physmem.totBusLat 19330000 # Total ticks spent in databus transfers 20611507SCurtis.Dunham@arm.comsystem.physmem.avgQLat 7002.46 # Average queueing delay per DRAM burst 20711507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20811507SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 25752.46 # Average memory access latency per DRAM burst 20911507SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s 21011507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21111507SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s 21211507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21311507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21411507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.01 # Data bus utilization in percentage 21511507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 21611507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 21811507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21911507SCurtis.Dunham@arm.comsystem.physmem.readRowHits 2948 # Number of row buffer hits during reads 22011507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22111507SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads 22211507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22311507SCurtis.Dunham@arm.comsystem.physmem.avgGap 33725503.36 # Average gap between requests 22411507SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined 22511507SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 3144960 # Energy for activate commands per rank (pJ) 22611507SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 1716000 # Energy for precharge commands per rank (pJ) 22711507SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) 22811507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22911507SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) 23011507SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 3562127505 # Energy for active background per rank (pJ) 23111507SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 75103936500 # Energy for precharge background per rank (pJ) 23211507SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 87202954965 # Total energy per rank (pJ) 23311507SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 668.831686 # Core power per rank (mW) 23411507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 124939990750 # Time in different power states 23511507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 4353700000 # Time in different power states 23611507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23711507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 1087339250 # Time in different power states 23811507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23911507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 3764880 # Energy for activate commands per rank (pJ) 24011507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 2054250 # Energy for precharge commands per rank (pJ) 24111507SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 13790400 # Energy for read commands per rank (pJ) 24211507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24311507SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 8515837200 # Energy for refresh commands per rank (pJ) 24411507SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 3544157970 # Energy for active background per rank (pJ) 24511507SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 75119701500 # Energy for precharge background per rank (pJ) 24611507SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 87199306200 # Total energy per rank (pJ) 24711507SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 668.803682 # Core power per rank (mW) 24811507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 124966482000 # Time in different power states 24911507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 4353700000 # Time in different power states 25011507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25111507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 1060850750 # Time in different power states 25211507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 49622074 # Number of BP lookups 25411507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 39447439 # Number of conditional branches predicted 25511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 5514206 # Number of conditional branches incorrect 25611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 24092073 # Number of BTB lookups 25711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 22843202 # Number of BTB hits 25811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 94.816258 # BTB Hit Percentage 26011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 1888965 # Number of times the RAS was used to get a target. 26111507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. 26211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 213748 # Number of indirect predictor lookups. 26311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 207973 # Number of indirect target hits. 26411507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 5775 # Number of indirect misses. 26511507SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. 26611507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 26811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 26911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 27011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 27111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 27211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 27311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 27711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 27811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 27911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 28011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 28111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 28711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 28811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 28911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 29311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 29611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 29711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 29911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 30411507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 30511507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 30611507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 30711507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 30811507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 30911507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 31011507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31111507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31211507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31311507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 31511507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 31611507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 31711507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 31811507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 31911507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 32011507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 32111507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 32211507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 32311507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 32411507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 32511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 32611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 32811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 32911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 33611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 33711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 33811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 33911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 34711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 34911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 35511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36211507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 36311507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 36411507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 36511507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 36611507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 36711507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 36811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 36911507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37011507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37111507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37211507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 37311507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 37411507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 37511507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 37611507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37711507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 37811507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 37911507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 38011507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 38111507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 38211507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 38311507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 400 # Number of system calls 38411507SCurtis.Dunham@arm.comsystem.cpu.numCycles 260765781 # number of cpu cycles simulated 38511507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 38611507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38711507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 172317810 # Number of instructions committed 38811507SCurtis.Dunham@arm.comsystem.cpu.committedOps 181650743 # Number of ops (including micro ops) committed 38911507SCurtis.Dunham@arm.comsystem.cpu.discardedOps 11583006 # Number of ops (including micro ops) which were discarded before commit 39011507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 39111507SCurtis.Dunham@arm.comsystem.cpu.cpi 1.513284 # CPI: cycles per instruction 39211507SCurtis.Dunham@arm.comsystem.cpu.ipc 0.660815 # IPC: instructions per cycle 39311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 39411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction 39511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction 39611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction 39711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction 39811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction 39911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction 40011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction 40111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction 40211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction 40311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction 40411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction 40511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction 40611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction 40711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction 40811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction 40911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction 41011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction 41111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction 41211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction 41311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction 41411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction 41511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction 41611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction 41711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction 41811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction 41911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction 42011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction 42111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction 42211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 42311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction 42411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemWrite 12644635 6.96% 100.00% # Class of committed instruction 42511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 42611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 42711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 181650743 # Class of committed instruction 42811507SCurtis.Dunham@arm.comsystem.cpu.tickCycles 254551967 # Number of cycles that the object actually ticked 42911507SCurtis.Dunham@arm.comsystem.cpu.idleCycles 6213814 # Total number of cycles that the object has spent stopped 43011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 42 # number of replacements 43111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 1378.689350 # Cycle average of tags in use 43211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 40754473 # Total number of references to valid blocks. 43311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. 43411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 22503.850359 # Average number of references to valid blocks. 43511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 43611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 1378.689350 # Average occupied blocks per requestor 43711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.336594 # Average percentage of cache occupancy 43811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.336594 # Average percentage of cache occupancy 43911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id 44011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 44111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 44211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id 44311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 44411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id 44511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id 44611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 81515639 # Number of tag accesses 44711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 81515639 # Number of data accesses 44811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 28346557 # number of ReadReq hits 44911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 28346557 # number of ReadReq hits 45011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits 45111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits 45211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits 45311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits 45411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 45511507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 45611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 45711507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 45811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 40709197 # number of demand (read+write) hits 45911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 40709197 # number of demand (read+write) hits 46011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 40709659 # number of overall hits 46111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 40709659 # number of overall hits 46211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses 46311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses 46411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses 46511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses 46611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 46711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 46811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses 46911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses 47011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses 47111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 2441 # number of overall misses 47211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 59629000 # number of ReadReq miss cycles 47311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 59629000 # number of ReadReq miss cycles 47411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 126003000 # number of WriteReq miss cycles 47511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 126003000 # number of WriteReq miss cycles 47611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 185632000 # number of demand (read+write) miss cycles 47711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 185632000 # number of demand (read+write) miss cycles 47811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 185632000 # number of overall miss cycles 47911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 185632000 # number of overall miss cycles 48011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 28347350 # number of ReadReq accesses(hits+misses) 48111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 28347350 # number of ReadReq accesses(hits+misses) 48211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 48311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 48411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) 48511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) 48611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 48711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 48811507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 48911507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 49011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 40711637 # number of demand (read+write) accesses 49111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 40711637 # number of demand (read+write) accesses 49211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 40712100 # number of overall (read+write) accesses 49311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 40712100 # number of overall (read+write) accesses 49411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses 49511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses 49611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses 49711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses 49811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses 49911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses 50011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses 50111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses 50211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses 50311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses 50411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243 # average ReadReq miss latency 50511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243 # average ReadReq miss latency 50611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734 # average WriteReq miss latency 50711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734 # average WriteReq miss latency 50811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525 # average overall miss latency 50911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 76078.688525 # average overall miss latency 51011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508 # average overall miss latency 51111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 76047.521508 # average overall miss latency 51211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 51311507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 51411507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 51511507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 51611507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 51711507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 51811507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 16 # number of writebacks 51911507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 16 # number of writebacks 52011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits 52111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits 52211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits 52311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits 52411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 630 # number of demand (read+write) MSHR hits 52511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 630 # number of demand (read+write) MSHR hits 52611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 630 # number of overall MSHR hits 52711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 630 # number of overall MSHR hits 52811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses 52911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses 53011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses 53111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses 53211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 53311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 53411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses 53511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses 53611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses 53711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses 53811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52555500 # number of ReadReq MSHR miss cycles 53911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 52555500 # number of ReadReq MSHR miss cycles 54011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85213000 # number of WriteReq MSHR miss cycles 54111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 85213000 # number of WriteReq MSHR miss cycles 54211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles 54311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles 54411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 137768500 # number of demand (read+write) MSHR miss cycles 54511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 137768500 # number of demand (read+write) MSHR miss cycles 54611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 137838500 # number of overall MSHR miss cycles 54711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 137838500 # number of overall MSHR miss cycles 54811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 54911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 55011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 55111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 55211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses 55311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses 55411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 55511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 55611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 55711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses 55811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519 # average ReadReq mshr miss latency 55911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519 # average ReadReq mshr miss latency 56011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683 # average WriteReq mshr miss latency 56111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683 # average WriteReq mshr miss latency 56211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency 56311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency 56411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370 # average overall mshr miss latency 56511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370 # average overall mshr miss latency 56611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676 # average overall mshr miss latency 56711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676 # average overall mshr miss latency 56811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 2881 # number of replacements 56911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 1423.942746 # Cycle average of tags in use 57011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 70779397 # Total number of references to valid blocks. 57111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 4677 # Sample count of references to valid blocks. 57211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 15133.503742 # Average number of references to valid blocks. 57311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 57411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1423.942746 # Average occupied blocks per requestor 57511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.695285 # Average percentage of cache occupancy 57611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.695285 # Average percentage of cache occupancy 57711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id 57811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 57911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id 58011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id 58111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id 58211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id 58311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id 58411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 141572827 # Number of tag accesses 58511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 141572827 # Number of data accesses 58611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 70779397 # number of ReadReq hits 58711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 70779397 # number of ReadReq hits 58811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 70779397 # number of demand (read+write) hits 58911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 70779397 # number of demand (read+write) hits 59011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 70779397 # number of overall hits 59111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 70779397 # number of overall hits 59211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses 59311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 4678 # number of ReadReq misses 59411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses 59511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 4678 # number of demand (read+write) misses 59611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 4678 # number of overall misses 59711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 4678 # number of overall misses 59811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 198432500 # number of ReadReq miss cycles 59911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 198432500 # number of ReadReq miss cycles 60011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 198432500 # number of demand (read+write) miss cycles 60111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 198432500 # number of demand (read+write) miss cycles 60211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 198432500 # number of overall miss cycles 60311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 198432500 # number of overall miss cycles 60411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 70784075 # number of ReadReq accesses(hits+misses) 60511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 70784075 # number of ReadReq accesses(hits+misses) 60611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 70784075 # number of demand (read+write) accesses 60711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 70784075 # number of demand (read+write) accesses 60811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 70784075 # number of overall (read+write) accesses 60911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 70784075 # number of overall (read+write) accesses 61011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 61111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 61211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 61311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 61411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 61511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses 61611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288 # average ReadReq miss latency 61711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288 # average ReadReq miss latency 61811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency 61911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 42418.234288 # average overall miss latency 62011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288 # average overall miss latency 62111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 42418.234288 # average overall miss latency 62211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 62311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 62411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 62511507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 62611507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 62711507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 62811507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 2881 # number of writebacks 62911507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 2881 # number of writebacks 63011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 4678 # number of ReadReq MSHR misses 63111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 4678 # number of ReadReq MSHR misses 63211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 4678 # number of demand (read+write) MSHR misses 63311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 4678 # number of demand (read+write) MSHR misses 63411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 4678 # number of overall MSHR misses 63511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 4678 # number of overall MSHR misses 63611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 193755500 # number of ReadReq MSHR miss cycles 63711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 193755500 # number of ReadReq MSHR miss cycles 63811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 193755500 # number of demand (read+write) MSHR miss cycles 63911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 193755500 # number of demand (read+write) MSHR miss cycles 64011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 193755500 # number of overall MSHR miss cycles 64111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 193755500 # number of overall MSHR miss cycles 64211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses 64311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses 64411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses 64511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses 64611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 64711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses 64811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055 # average ReadReq mshr miss latency 64911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055 # average ReadReq mshr miss latency 65011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 65111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency 65211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055 # average overall mshr miss latency 65311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055 # average overall mshr miss latency 65411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 65511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 1999.548128 # Cycle average of tags in use 65611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 5178 # Total number of references to valid blocks. 65711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 2783 # Sample count of references to valid blocks. 65811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 1.860582 # Average number of references to valid blocks. 65911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 66011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 3.029345 # Average occupied blocks per requestor 66111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 1506.706963 # Average occupied blocks per requestor 66211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 489.811820 # Average occupied blocks per requestor 66311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy 66411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.045981 # Average percentage of cache occupancy 66511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.014948 # Average percentage of cache occupancy 66611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.061021 # Average percentage of cache occupancy 66711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 2783 # Occupied blocks per task id 66811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 66911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id 67011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 67111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id 67211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 2003 # Occupied blocks per task id 67311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.084930 # Percentage of cache occupancy per task id 67411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 76554 # Number of tag accesses 67511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 76554 # Number of data accesses 67611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 67711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits 67811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 2559 # number of WritebackClean hits 67911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 2559 # number of WritebackClean hits 68011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 68111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 68211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2517 # number of ReadCleanReq hits 68311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 2517 # number of ReadCleanReq hits 68411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 81 # number of ReadSharedReq hits 68511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 81 # number of ReadSharedReq hits 68611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 2517 # number of demand (read+write) hits 68711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 89 # number of demand (read+write) hits 68811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 2606 # number of demand (read+write) hits 68911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 2517 # number of overall hits 69011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 89 # number of overall hits 69111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 2606 # number of overall hits 69211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses 69311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses 69411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2161 # number of ReadCleanReq misses 69511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 2161 # number of ReadCleanReq misses 69611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 631 # number of ReadSharedReq misses 69711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 631 # number of ReadSharedReq misses 69811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2161 # number of demand (read+write) misses 69911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses 70011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 3883 # number of demand (read+write) misses 70111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2161 # number of overall misses 70211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses 70311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 3883 # number of overall misses 70411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83479000 # number of ReadExReq miss cycles 70511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 83479000 # number of ReadExReq miss cycles 70611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 159937500 # number of ReadCleanReq miss cycles 70711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 159937500 # number of ReadCleanReq miss cycles 70811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50622000 # number of ReadSharedReq miss cycles 70911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 50622000 # number of ReadSharedReq miss cycles 71011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 159937500 # number of demand (read+write) miss cycles 71111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 134101000 # number of demand (read+write) miss cycles 71211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 294038500 # number of demand (read+write) miss cycles 71311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 159937500 # number of overall miss cycles 71411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 134101000 # number of overall miss cycles 71511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 294038500 # number of overall miss cycles 71611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) 71711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) 71811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 2559 # number of WritebackClean accesses(hits+misses) 71911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 2559 # number of WritebackClean accesses(hits+misses) 72011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) 72111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) 72211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4678 # number of ReadCleanReq accesses(hits+misses) 72311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 4678 # number of ReadCleanReq accesses(hits+misses) 72411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) 72511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) 72611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 4678 # number of demand (read+write) accesses 72711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses 72811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 6489 # number of demand (read+write) accesses 72911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 4678 # number of overall (read+write) accesses 73011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses 73111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 6489 # number of overall (read+write) accesses 73211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses 73311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses 73411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.461950 # miss rate for ReadCleanReq accesses 73511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.461950 # miss rate for ReadCleanReq accesses 73611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886236 # miss rate for ReadSharedReq accesses 73711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886236 # miss rate for ReadSharedReq accesses 73811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.461950 # miss rate for demand accesses 73911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.950856 # miss rate for demand accesses 74011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.598397 # miss rate for demand accesses 74111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.461950 # miss rate for overall accesses 74211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.950856 # miss rate for overall accesses 74311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.598397 # miss rate for overall accesses 74411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330 # average ReadExReq miss latency 74511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330 # average ReadExReq miss latency 74611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595 # average ReadCleanReq miss latency 74711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595 # average ReadCleanReq miss latency 74811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620 # average ReadSharedReq miss latency 74911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620 # average ReadSharedReq miss latency 75011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency 75111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency 75211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 75724.568633 # average overall miss latency 75311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595 # average overall miss latency 75411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180 # average overall miss latency 75511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 75724.568633 # average overall miss latency 75611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 75711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 75811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 75911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 76011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 76111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 76211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 76311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 76411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 76511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 76611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 76711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 76811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 76911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 77011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits 77111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 77211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses 77311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses 77411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2159 # number of ReadCleanReq MSHR misses 77511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 2159 # number of ReadCleanReq MSHR misses 77611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses 77711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses 77811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2159 # number of demand (read+write) MSHR misses 77911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses 78011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 3867 # number of demand (read+write) MSHR misses 78111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2159 # number of overall MSHR misses 78211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses 78311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 3867 # number of overall MSHR misses 78411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 72569000 # number of ReadExReq MSHR miss cycles 78511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 72569000 # number of ReadExReq MSHR miss cycles 78611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 138134000 # number of ReadCleanReq MSHR miss cycles 78711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 138134000 # number of ReadCleanReq MSHR miss cycles 78811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 43490000 # number of ReadSharedReq MSHR miss cycles 78911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 43490000 # number of ReadSharedReq MSHR miss cycles 79011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138134000 # number of demand (read+write) MSHR miss cycles 79111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 116059000 # number of demand (read+write) MSHR miss cycles 79211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 254193000 # number of demand (read+write) MSHR miss cycles 79311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138134000 # number of overall MSHR miss cycles 79411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 116059000 # number of overall MSHR miss cycles 79511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 254193000 # number of overall MSHR miss cycles 79611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses 79711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses 79811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for ReadCleanReq accesses 79911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461522 # mshr miss rate for ReadCleanReq accesses 80011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses 80111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses 80211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for demand accesses 80311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses 80411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.595932 # mshr miss rate for demand accesses 80511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461522 # mshr miss rate for overall accesses 80611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses 80711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.595932 # mshr miss rate for overall accesses 80811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330 # average ReadExReq mshr miss latency 80911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330 # average ReadExReq mshr miss latency 81011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549 # average ReadCleanReq mshr miss latency 81111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549 # average ReadCleanReq mshr miss latency 81211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663 # average ReadSharedReq mshr miss latency 81311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663 # average ReadSharedReq mshr miss latency 81411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency 81511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency 81611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency 81711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549 # average overall mshr miss latency 81811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192 # average overall mshr miss latency 81911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250 # average overall mshr miss latency 82011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 9412 # Total number of requests made to the snoop filter. 82111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 3057 # Number of requests hitting in the snoop filter with a single holder of the requested data. 82211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 82311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 82411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 82511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 82611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 5389 # Transaction distribution 82711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution 82811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 2881 # Transaction distribution 82911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution 83011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution 83111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution 83211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 4678 # Transaction distribution 83311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution 83411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12236 # Packet count per connected master and slave (bytes) 83511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) 83611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 15900 # Packet count per connected master and slave (bytes) 83711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483712 # Cumulative packet size per connected master and slave (bytes) 83811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) 83911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 600640 # Cumulative packet size per connected master and slave (bytes) 84011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 84111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 6489 # Request fanout histogram 84211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.071197 # Request fanout histogram 84311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.257174 # Request fanout histogram 84411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 84511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 6027 92.88% 92.88% # Request fanout histogram 84611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 462 7.12% 100.00% # Request fanout histogram 84711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 84811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 84911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 85011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 85111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 6489 # Request fanout histogram 85211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 7603000 # Layer occupancy (ticks) 85311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 85411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 7016498 # Layer occupancy (ticks) 85511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 85611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2723486 # Layer occupancy (ticks) 85711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 85811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 2775 # Transaction distribution 85911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 1091 # Transaction distribution 86011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 1091 # Transaction distribution 86111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 2775 # Transaction distribution 86211507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) 86311507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) 86411507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) 86511507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes) 86611507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 86711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 3866 # Request fanout histogram 86811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 86911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 87011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 87111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram 87211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 87311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 87411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 87511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 87611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 3866 # Request fanout histogram 87711507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 4516500 # Layer occupancy (ticks) 87811507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 87911507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 20548250 # Layer occupancy (ticks) 88011507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 88111507SCurtis.Dunham@arm.com 88211507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 883