111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 0.132570 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 132570000500 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 373440 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 393666 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 287300012 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 274936 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 461.43 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 172317810 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 181650743 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory 1911570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 247552 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 138240 # Number of instructions bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 138240 # Number of instructions bytes read from this memory 2211570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 3868 # Number of read requests responded to by this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s) 2611860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s) 2711860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s) 2811860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s) 2911860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s) 3011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s) 3111860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s) 3211860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s) 3311570SCurtis.Dunham@arm.comsystem.physmem.readReqs 3868 # Number of read requests accepted 3411507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511570SCurtis.Dunham@arm.comsystem.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue 3611507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711570SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 247552 # Total number of bytes read from DRAM 3811507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3911507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011570SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 247552 # Total read bytes from the system interface side 4111507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4211507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 305 # Per bank write bursts 4611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 217 # Per bank write bursts 4711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 135 # Per bank write bursts 4811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 313 # Per bank write bursts 4911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 306 # Per bank write bursts 5011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 305 # Per bank write bursts 5111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 273 # Per bank write bursts 5211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 222 # Per bank write bursts 5311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 248 # Per bank write bursts 5411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 218 # Per bank write bursts 5511570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 296 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 200 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 183 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 218 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 224 # Per bank write bursts 6011570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 205 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7811507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911860Sandreas.hansson@arm.comsystem.physmem.totGap 132569899500 # Total gap between requests 8011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611570SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 3868 # Read request sizes (log2) 8711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see 9511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see 9611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see 9711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 9811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 9911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation 19111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation 19211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation 19311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation 19411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation 19511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation 19611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation 19711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation 19811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation 19911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation 20011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation 20111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation 20211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation 20311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation 20411860Sandreas.hansson@arm.comsystem.physmem.totQLat 82551750 # Total ticks spent queuing 20511860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM 20611570SCurtis.Dunham@arm.comsystem.physmem.totBusLat 19340000 # Total ticks spent in databus transfers 20711860Sandreas.hansson@arm.comsystem.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst 20811507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst 21011570SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s 21111507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211570SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s 21311507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21411507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.01 # Data bus utilization in percentage 21611507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 21711507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 21911507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011680SCurtis.Dunham@arm.comsystem.physmem.readRowHits 2935 # Number of row buffer hits during reads 22111507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211680SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads 22311507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411860Sandreas.hansson@arm.comsystem.physmem.avgGap 34273500.39 # Average gap between requests 22511680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined 22611860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ) 22711860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ) 22811680SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ) 22911507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ) 23111860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ) 23211860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ) 23311860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ) 23411860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ) 23511860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ) 23611860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ) 23711860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 244.026270 # Core power per rank (mW) 23811860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank 23911860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states 24011860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 66782000 # Time in different power states 24111860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states 24211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states 24311860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states 24411860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states 24511860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ) 24611860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ) 24711680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ) 24811507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24911860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ) 25011860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ) 25111860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ) 25211860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ) 25311860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ) 25411860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ) 25511860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ) 25611860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 243.774090 # Core power per rank (mW) 25711860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank 25811860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states 25911860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 60730000 # Time in different power states 26011860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states 26111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states 26211860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states 26311860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states 26411860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 26511860Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 49693872 # Number of BP lookups 26611860Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted 26711860Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect 26811860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups 26911860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 22923274 # Number of BTB hits 27011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 27111860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage 27211860Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target. 27311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. 27411860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups. 27511860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 208025 # Number of indirect target hits. 27611860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 5884 # Number of indirect misses. 27711860Sandreas.hansson@arm.comsystem.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches. 27811507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27911860Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 28011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 28111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 28211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 28311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 28411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 28511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 28611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 28711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 28811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 28911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 29011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 29111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 29211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 29311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 29411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 29511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 29611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 29711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 29811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 29911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 30011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 30111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 30211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 30311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 30411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 30511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 30611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 30711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 30811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 30911860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 31011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 31111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 31211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 31511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 31611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 31711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 31811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 31911507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 32011507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 32111507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 32211507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 32311507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 32411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 32511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 32911507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 33011507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 33111507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 33211507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 33411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 33511507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 33611507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 33711507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 33811507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 33911860Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 34011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 34711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 34811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 34911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 35011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 35111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 35211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 35311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 35411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 35511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 35911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 36011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 36111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 36211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 36411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 36511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 36611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 36711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 36811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 36911860Sandreas.hansson@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 37011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 37111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 37711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 37911507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 38011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 38111507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 38211507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 38311507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 38411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 38511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 38711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 38911507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 39011507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 39111507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 39211507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 39411507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 39511507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 39611507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 39711507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 39811507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 39911955Sgabeblack@google.comsystem.cpu.workload.numSyscalls 400 # Number of system calls 40011860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states 40111860Sandreas.hansson@arm.comsystem.cpu.numCycles 265140001 # number of cpu cycles simulated 40211507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40311507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 40411507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 172317810 # Number of instructions committed 40511507SCurtis.Dunham@arm.comsystem.cpu.committedOps 181650743 # Number of ops (including micro ops) committed 40611860Sandreas.hansson@arm.comsystem.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit 40711507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 40811860Sandreas.hansson@arm.comsystem.cpu.cpi 1.538669 # CPI: cycles per instruction 40911860Sandreas.hansson@arm.comsystem.cpu.ipc 0.649913 # IPC: instructions per cycle 41011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 41111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction 41211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction 41311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction 41411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction 41511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction 41611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction 41711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction 41811687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction 41911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction 42011687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction 42111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction 42211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction 42311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction 42411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction 42511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction 42611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction 42711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction 42811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction 42911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction 43011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction 43111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction 43211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction 43511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction 43611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction 43711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction 43811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction 43911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction 44011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction 44211687Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction 44311687Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemWrite 12498389 6.88% 99.62% # Class of committed instruction 44411687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction 44511687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 181650743 # Class of committed instruction 44911860Sandreas.hansson@arm.comsystem.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked 45011860Sandreas.hansson@arm.comsystem.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped 45111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 45211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 42 # number of replacements 45311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use 45411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks. 45511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. 45611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks. 45711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 45811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor 45911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy 46011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.336570 # Average percentage of cache occupancy 46111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id 46211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 46311680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id 46411680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 46511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id 46611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id 46711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id 46811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses 46911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses 47011860Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 47111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits 47211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits 47311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits 47411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits 47511860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits 47611860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits 47711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 47811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits 47911507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits 48011507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits 48111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits 48211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits 48311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits 48411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 40709647 # number of overall hits 48511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses 48611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses 48711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses 48811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses 48911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 49011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 49111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses 49211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses 49311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses 49411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 2405 # number of overall misses 49511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles 49611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles 49711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles 49811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles 49911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles 50011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles 50111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles 50211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles 50311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses) 50411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses) 50511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) 50611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) 50711860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses) 50811860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses) 50911507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) 51011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) 51111507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) 51211507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) 51311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 40711588 # number of demand (read+write) accesses 51411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses 51511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 40712052 # number of overall (read+write) accesses 51611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses 51711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses 51811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses 51911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses 52011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses 52111860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002155 # miss rate for SoftPFReq accesses 52211860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses 52311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses 52411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses 52511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses 52611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses 52711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 85334.886818 # average ReadReq miss latency 52811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency 52911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88465.517241 # average WriteReq miss latency 53011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 88465.517241 # average WriteReq miss latency 53111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 87487.520799 # average overall miss latency 53211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency 53311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 87451.143451 # average overall miss latency 53411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 87451.143451 # average overall miss latency 53511507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 53611507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 53711507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 53811507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 53911507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 54011507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 54111507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 16 # number of writebacks 54211507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 16 # number of writebacks 54311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits 54411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits 54511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 554 # number of WriteReq MSHR hits 54611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 554 # number of WriteReq MSHR hits 54711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 594 # number of demand (read+write) MSHR hits 54811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits 54911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 594 # number of overall MSHR hits 55011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits 55111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses 55211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses 55311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses 55411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses 55511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 55611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 55711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses 55811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses 55911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses 56011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses 56111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 60392000 # number of ReadReq MSHR miss cycles 56211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 60392000 # number of ReadReq MSHR miss cycles 56311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 99618500 # number of WriteReq MSHR miss cycles 56411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 99618500 # number of WriteReq MSHR miss cycles 56511680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 77000 # number of SoftPFReq MSHR miss cycles 56611680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 77000 # number of SoftPFReq MSHR miss cycles 56711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 160010500 # number of demand (read+write) MSHR miss cycles 56811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 160010500 # number of demand (read+write) MSHR miss cycles 56911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 160087500 # number of overall MSHR miss cycles 57011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 160087500 # number of overall MSHR miss cycles 57111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses 57211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses 57311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses 57411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses 57511860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002155 # mshr miss rate for SoftPFReq accesses 57611860Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002155 # mshr miss rate for SoftPFReq accesses 57711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses 57811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses 57911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses 58011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses 58111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84939.521800 # average ReadReq mshr miss latency 58211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency 58311860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 90644.676979 # average WriteReq mshr miss latency 58411860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90644.676979 # average WriteReq mshr miss latency 58511680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 77000 # average SoftPFReq mshr miss latency 58611680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency 58711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency 58811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency 58911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency 59011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency 59111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 59211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 2861 # number of replacements 59311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 1424.892665 # Cycle average of tags in use 59411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 70991309 # Total number of references to valid blocks. 59511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 4660 # Sample count of references to valid blocks. 59611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 15234.186481 # Average number of references to valid blocks. 59711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 59811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1424.892665 # Average occupied blocks per requestor 59911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.695748 # Average percentage of cache occupancy 60011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.695748 # Average percentage of cache occupancy 60111570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id 60211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 60311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id 60411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id 60511680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id 60611570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id 60711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id 60811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 141996600 # Number of tag accesses 60911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 141996600 # Number of data accesses 61011860Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 61111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 70991309 # number of ReadReq hits 61211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 70991309 # number of ReadReq hits 61311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 70991309 # number of demand (read+write) hits 61411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 70991309 # number of demand (read+write) hits 61511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 70991309 # number of overall hits 61611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 70991309 # number of overall hits 61711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 4661 # number of ReadReq misses 61811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 4661 # number of ReadReq misses 61911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 4661 # number of demand (read+write) misses 62011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 4661 # number of demand (read+write) misses 62111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 4661 # number of overall misses 62211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 4661 # number of overall misses 62311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 236001500 # number of ReadReq miss cycles 62411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 236001500 # number of ReadReq miss cycles 62511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 236001500 # number of demand (read+write) miss cycles 62611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 236001500 # number of demand (read+write) miss cycles 62711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 236001500 # number of overall miss cycles 62811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 236001500 # number of overall miss cycles 62911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 70995970 # number of ReadReq accesses(hits+misses) 63011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 70995970 # number of ReadReq accesses(hits+misses) 63111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 70995970 # number of demand (read+write) accesses 63211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 70995970 # number of demand (read+write) accesses 63311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 70995970 # number of overall (read+write) accesses 63411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 70995970 # number of overall (read+write) accesses 63511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses 63611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses 63711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses 63811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses 63911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses 64011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses 64111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50633.233212 # average ReadReq miss latency 64211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 50633.233212 # average ReadReq miss latency 64311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency 64411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 50633.233212 # average overall miss latency 64511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency 64611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 50633.233212 # average overall miss latency 64711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 64811507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 64911507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 65011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 65111507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 65211507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 65311860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 2861 # number of writebacks 65411860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 2861 # number of writebacks 65511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses 65611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 4661 # number of ReadReq MSHR misses 65711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses 65811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 4661 # number of demand (read+write) MSHR misses 65911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses 66011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 4661 # number of overall MSHR misses 66111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231341500 # number of ReadReq MSHR miss cycles 66211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 231341500 # number of ReadReq MSHR miss cycles 66311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 231341500 # number of demand (read+write) MSHR miss cycles 66411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 231341500 # number of demand (read+write) MSHR miss cycles 66511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 231341500 # number of overall MSHR miss cycles 66611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 231341500 # number of overall MSHR miss cycles 66711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses 66811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses 66911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses 67011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses 67111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses 67211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses 67311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49633.447758 # average ReadReq mshr miss latency 67411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49633.447758 # average ReadReq mshr miss latency 67511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency 67611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency 67711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency 67811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency 67911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 68011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 68111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 2835.344855 # Cycle average of tags in use 68211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 5154 # Total number of references to valid blocks. 68311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. 68411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 1.332472 # Average number of references to valid blocks. 68511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 68611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.641960 # Average occupied blocks per requestor 68711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 1327.702895 # Average occupied blocks per requestor 68811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy 68911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.040518 # Average percentage of cache occupancy 69011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.086528 # Average percentage of cache occupancy 69111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id 69211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 69311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 69411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id 69511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id 69611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id 69711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id 69811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 76180 # Number of tag accesses 69911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 76180 # Number of data accesses 70011860Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 70111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 70211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits 70311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 2531 # number of WritebackClean hits 70411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 2531 # number of WritebackClean hits 70511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 70611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 70711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2499 # number of ReadCleanReq hits 70811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 2499 # number of ReadCleanReq hits 70911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits 71011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits 71111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 2499 # number of demand (read+write) hits 71211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits 71311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2587 # number of demand (read+write) hits 71411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 2499 # number of overall hits 71511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits 71611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2587 # number of overall hits 71711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses 71811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses 71911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2162 # number of ReadCleanReq misses 72011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 2162 # number of ReadCleanReq misses 72111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses 72211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses 72311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2162 # number of demand (read+write) misses 72411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1723 # number of demand (read+write) misses 72511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses 72611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses 72711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses 72811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 3885 # number of overall misses 72911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97884500 # number of ReadExReq miss cycles 73011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 97884500 # number of ReadExReq miss cycles 73111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 197728500 # number of ReadCleanReq miss cycles 73211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 197728500 # number of ReadCleanReq miss cycles 73311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 58476500 # number of ReadSharedReq miss cycles 73411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 58476500 # number of ReadSharedReq miss cycles 73511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 197728500 # number of demand (read+write) miss cycles 73611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 156361000 # number of demand (read+write) miss cycles 73711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 354089500 # number of demand (read+write) miss cycles 73811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 197728500 # number of overall miss cycles 73911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 156361000 # number of overall miss cycles 74011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 354089500 # number of overall miss cycles 74111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) 74211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) 74311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 2531 # number of WritebackClean accesses(hits+misses) 74411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 2531 # number of WritebackClean accesses(hits+misses) 74511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) 74611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) 74711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4661 # number of ReadCleanReq accesses(hits+misses) 74811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 4661 # number of ReadCleanReq accesses(hits+misses) 74911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) 75011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) 75111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 4661 # number of demand (read+write) accesses 75211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses 75311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 6472 # number of demand (read+write) accesses 75411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 4661 # number of overall (read+write) accesses 75511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses 75611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 6472 # number of overall (read+write) accesses 75711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses 75811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses 75911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463849 # miss rate for ReadCleanReq accesses 76011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463849 # miss rate for ReadCleanReq accesses 76111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses 76211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses 76311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.463849 # miss rate for demand accesses 76411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses 76511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses 76611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses 76711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses 76811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses 76911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency 77011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency 77111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency 77211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency 77311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency 77411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency 77511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency 77611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency 77711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency 77811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency 77911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency 78011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency 78111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 78211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 78411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 78511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 78611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 78711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 78811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 78911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 15 # number of ReadSharedReq MSHR hits 79011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits 79111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 79211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits 79311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits 79411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 79511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits 79611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits 79711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses 79811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses 79911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2161 # number of ReadCleanReq MSHR misses 80011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 2161 # number of ReadCleanReq MSHR misses 80111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses 80211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses 80311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2161 # number of demand (read+write) MSHR misses 80411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses 80511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 3869 # number of demand (read+write) MSHR misses 80611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses 80711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses 80811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses 80911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86974500 # number of ReadExReq MSHR miss cycles 81011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86974500 # number of ReadExReq MSHR miss cycles 81111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176055000 # number of ReadCleanReq MSHR miss cycles 81211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176055000 # number of ReadCleanReq MSHR miss cycles 81311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 50639500 # number of ReadSharedReq MSHR miss cycles 81411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 50639500 # number of ReadSharedReq MSHR miss cycles 81511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176055000 # number of demand (read+write) MSHR miss cycles 81611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137614000 # number of demand (read+write) MSHR miss cycles 81711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 313669000 # number of demand (read+write) MSHR miss cycles 81811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176055000 # number of overall MSHR miss cycles 81911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137614000 # number of overall MSHR miss cycles 82011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 313669000 # number of overall MSHR miss cycles 82111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses 82211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses 82311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses 82411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses 82511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses 82611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses 82711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses 82811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses 82911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses 83011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses 83111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses 83211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses 83311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency 83411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency 83511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency 83611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency 83711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency 83811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency 83911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency 84011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency 84111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency 84211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency 84311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency 84411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency 84511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter. 84611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data. 84711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 84811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 84911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 85011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 85111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 85211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution 85311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution 85411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution 85511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution 85611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution 85711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution 85811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution 85911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution 86011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes) 86111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) 86211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes) 86311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes) 86411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) 86511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes) 86611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 86711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 86811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram 86911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram 87011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram 87111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 87211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram 87311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram 87411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 87511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 87611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 87711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 87811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram 87911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks) 88011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 88111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks) 88211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 88311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) 88411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 88511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter. 88611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 88711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 88811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 88911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 89011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 89111860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states 89211570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 2777 # Transaction distribution 89311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 1091 # Transaction distribution 89411507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 1091 # Transaction distribution 89511570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 2777 # Transaction distribution 89611570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7736 # Packet count per connected master and slave (bytes) 89711570SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 7736 # Packet count per connected master and slave (bytes) 89811570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247552 # Cumulative packet size per connected master and slave (bytes) 89911570SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 247552 # Cumulative packet size per connected master and slave (bytes) 90011507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 90111570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 90211570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 3868 # Request fanout histogram 90311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 90411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 90511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 90611570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 3868 100.00% 100.00% # Request fanout histogram 90711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 90811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 90911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 91011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 91111570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 3868 # Request fanout histogram 91211860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks) 91311507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 91411860Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks) 91511507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 91611507SCurtis.Dunham@arm.com 91711507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 918