simout revision 10260
110260SAndrew.Bardsley@arm.comRedirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simout 210260SAndrew.Bardsley@arm.comRedirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simerr 310260SAndrew.Bardsley@arm.comgem5 Simulator System. http://gem5.org 410260SAndrew.Bardsley@arm.comgem5 is copyrighted software; use the --copyright option for details. 510260SAndrew.Bardsley@arm.com 610260SAndrew.Bardsley@arm.comgem5 compiled May 7 2014 10:57:46 710260SAndrew.Bardsley@arm.comgem5 started May 7 2014 13:16:45 810260SAndrew.Bardsley@arm.comgem5 executing on cz3211bhr8 910260SAndrew.Bardsley@arm.comcommand line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing 1010260SAndrew.Bardsley@arm.comCouldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav 1110260SAndrew.Bardsley@arm.comCouldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2 1210260SAndrew.Bardsley@arm.comGlobal frequency set at 1000000000000 ticks per second 1310260SAndrew.Bardsley@arm.com 0: system.cpu.isa: ISA system set to: 0 0x1c024750 1410260SAndrew.Bardsley@arm.cominfo: Entering event queue @ 0. Starting simulation... 1510260SAndrew.Bardsley@arm.com 1610260SAndrew.Bardsley@arm.comTimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 1710260SAndrew.Bardsley@arm.comStandard Cell Placement and Global Routing Program 1810260SAndrew.Bardsley@arm.comAuthors: Carl Sechen, Bill Swartz 1910260SAndrew.Bardsley@arm.com Yale University 2010260SAndrew.Bardsley@arm.cominfo: Increasing stack size by one page. 2110260SAndrew.Bardsley@arm.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2210260SAndrew.Bardsley@arm.com 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2310260SAndrew.Bardsley@arm.com 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 2410260SAndrew.Bardsley@arm.com 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2510260SAndrew.Bardsley@arm.com 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 2610260SAndrew.Bardsley@arm.com 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 2710260SAndrew.Bardsley@arm.com 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 2810260SAndrew.Bardsley@arm.com106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 2910260SAndrew.Bardsley@arm.com122 123 124 Exiting @ tick 133578736500 because target called exit() 30