config.ini revision 10315
110260SAndrew.Bardsley@arm.com[root]
210260SAndrew.Bardsley@arm.comtype=Root
310260SAndrew.Bardsley@arm.comchildren=system
410260SAndrew.Bardsley@arm.comeventq_index=0
510260SAndrew.Bardsley@arm.comfull_system=false
610260SAndrew.Bardsley@arm.comsim_quantum=0
710260SAndrew.Bardsley@arm.comtime_sync_enable=false
810260SAndrew.Bardsley@arm.comtime_sync_period=100000000000
910260SAndrew.Bardsley@arm.comtime_sync_spin_threshold=100000000
1010260SAndrew.Bardsley@arm.com
1110260SAndrew.Bardsley@arm.com[system]
1210260SAndrew.Bardsley@arm.comtype=System
1310315Snilay@cs.wisc.educhildren=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
1410260SAndrew.Bardsley@arm.comboot_osflags=a
1510260SAndrew.Bardsley@arm.comcache_line_size=64
1610260SAndrew.Bardsley@arm.comclk_domain=system.clk_domain
1710260SAndrew.Bardsley@arm.comeventq_index=0
1810260SAndrew.Bardsley@arm.cominit_param=0
1910260SAndrew.Bardsley@arm.comkernel=
2010315Snilay@cs.wisc.edukernel_addr_check=true
2110260SAndrew.Bardsley@arm.comload_addr_mask=1099511627775
2210260SAndrew.Bardsley@arm.comload_offset=0
2310260SAndrew.Bardsley@arm.commem_mode=timing
2410260SAndrew.Bardsley@arm.commem_ranges=
2510260SAndrew.Bardsley@arm.commemories=system.physmem
2610260SAndrew.Bardsley@arm.comnum_work_ids=16
2710260SAndrew.Bardsley@arm.comreadfile=
2810260SAndrew.Bardsley@arm.comsymbolfile=
2910260SAndrew.Bardsley@arm.comwork_begin_ckpt_count=0
3010260SAndrew.Bardsley@arm.comwork_begin_cpu_id_exit=-1
3110260SAndrew.Bardsley@arm.comwork_begin_exit_count=0
3210260SAndrew.Bardsley@arm.comwork_cpus_ckpt_count=0
3310260SAndrew.Bardsley@arm.comwork_end_ckpt_count=0
3410260SAndrew.Bardsley@arm.comwork_end_exit_count=0
3510260SAndrew.Bardsley@arm.comwork_item_id=-1
3610260SAndrew.Bardsley@arm.comsystem_port=system.membus.slave[0]
3710260SAndrew.Bardsley@arm.com
3810260SAndrew.Bardsley@arm.com[system.clk_domain]
3910260SAndrew.Bardsley@arm.comtype=SrcClockDomain
4010260SAndrew.Bardsley@arm.comclock=1000
4110315Snilay@cs.wisc.edudomain_id=-1
4210260SAndrew.Bardsley@arm.comeventq_index=0
4310315Snilay@cs.wisc.eduinit_perf_level=0
4410260SAndrew.Bardsley@arm.comvoltage_domain=system.voltage_domain
4510260SAndrew.Bardsley@arm.com
4610260SAndrew.Bardsley@arm.com[system.cpu]
4710260SAndrew.Bardsley@arm.comtype=MinorCPU
4810260SAndrew.Bardsley@arm.comchildren=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
4910260SAndrew.Bardsley@arm.combranchPred=system.cpu.branchPred
5010260SAndrew.Bardsley@arm.comchecker=Null
5110260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
5210260SAndrew.Bardsley@arm.comcpu_id=0
5310260SAndrew.Bardsley@arm.comdecodeCycleInput=true
5410260SAndrew.Bardsley@arm.comdecodeInputBufferSize=3
5510260SAndrew.Bardsley@arm.comdecodeInputWidth=2
5610260SAndrew.Bardsley@arm.comdecodeToExecuteForwardDelay=1
5710260SAndrew.Bardsley@arm.comdo_checkpoint_insts=true
5810260SAndrew.Bardsley@arm.comdo_quiesce=true
5910260SAndrew.Bardsley@arm.comdo_statistics_insts=true
6010260SAndrew.Bardsley@arm.comdstage2_mmu=system.cpu.dstage2_mmu
6110260SAndrew.Bardsley@arm.comdtb=system.cpu.dtb
6210260SAndrew.Bardsley@arm.comenableIdling=true
6310260SAndrew.Bardsley@arm.comeventq_index=0
6410260SAndrew.Bardsley@arm.comexecuteAllowEarlyMemoryIssue=true
6510260SAndrew.Bardsley@arm.comexecuteBranchDelay=1
6610260SAndrew.Bardsley@arm.comexecuteCommitLimit=2
6710260SAndrew.Bardsley@arm.comexecuteCycleInput=true
6810260SAndrew.Bardsley@arm.comexecuteFuncUnits=system.cpu.executeFuncUnits
6910260SAndrew.Bardsley@arm.comexecuteInputBufferSize=7
7010260SAndrew.Bardsley@arm.comexecuteInputWidth=2
7110260SAndrew.Bardsley@arm.comexecuteIssueLimit=2
7210260SAndrew.Bardsley@arm.comexecuteLSQMaxStoreBufferStoresPerCycle=2
7310260SAndrew.Bardsley@arm.comexecuteLSQRequestsQueueSize=1
7410260SAndrew.Bardsley@arm.comexecuteLSQStoreBufferSize=5
7510260SAndrew.Bardsley@arm.comexecuteLSQTransfersQueueSize=2
7610260SAndrew.Bardsley@arm.comexecuteMaxAccessesInMemory=2
7710260SAndrew.Bardsley@arm.comexecuteMemoryCommitLimit=1
7810260SAndrew.Bardsley@arm.comexecuteMemoryIssueLimit=1
7910260SAndrew.Bardsley@arm.comexecuteMemoryWidth=0
8010260SAndrew.Bardsley@arm.comexecuteSetTraceTimeOnCommit=true
8110260SAndrew.Bardsley@arm.comexecuteSetTraceTimeOnIssue=false
8210260SAndrew.Bardsley@arm.comfetch1FetchLimit=1
8310260SAndrew.Bardsley@arm.comfetch1LineSnapWidth=0
8410260SAndrew.Bardsley@arm.comfetch1LineWidth=0
8510260SAndrew.Bardsley@arm.comfetch1ToFetch2BackwardDelay=1
8610260SAndrew.Bardsley@arm.comfetch1ToFetch2ForwardDelay=1
8710260SAndrew.Bardsley@arm.comfetch2CycleInput=true
8810260SAndrew.Bardsley@arm.comfetch2InputBufferSize=2
8910260SAndrew.Bardsley@arm.comfetch2ToDecodeForwardDelay=1
9010260SAndrew.Bardsley@arm.comfunction_trace=false
9110260SAndrew.Bardsley@arm.comfunction_trace_start=0
9210260SAndrew.Bardsley@arm.cominterrupts=system.cpu.interrupts
9310260SAndrew.Bardsley@arm.comisa=system.cpu.isa
9410260SAndrew.Bardsley@arm.comistage2_mmu=system.cpu.istage2_mmu
9510260SAndrew.Bardsley@arm.comitb=system.cpu.itb
9610260SAndrew.Bardsley@arm.commax_insts_all_threads=0
9710260SAndrew.Bardsley@arm.commax_insts_any_thread=0
9810260SAndrew.Bardsley@arm.commax_loads_all_threads=0
9910260SAndrew.Bardsley@arm.commax_loads_any_thread=0
10010260SAndrew.Bardsley@arm.comnumThreads=1
10110260SAndrew.Bardsley@arm.comprofile=0
10210260SAndrew.Bardsley@arm.comprogress_interval=0
10310260SAndrew.Bardsley@arm.comsimpoint_start_insts=
10410315Snilay@cs.wisc.edusocket_id=0
10510260SAndrew.Bardsley@arm.comswitched_out=false
10610260SAndrew.Bardsley@arm.comsystem=system
10710260SAndrew.Bardsley@arm.comtracer=system.cpu.tracer
10810260SAndrew.Bardsley@arm.comworkload=system.cpu.workload
10910260SAndrew.Bardsley@arm.comdcache_port=system.cpu.dcache.cpu_side
11010260SAndrew.Bardsley@arm.comicache_port=system.cpu.icache.cpu_side
11110260SAndrew.Bardsley@arm.com
11210260SAndrew.Bardsley@arm.com[system.cpu.branchPred]
11310260SAndrew.Bardsley@arm.comtype=BranchPredictor
11410260SAndrew.Bardsley@arm.comBTBEntries=4096
11510260SAndrew.Bardsley@arm.comBTBTagSize=16
11610260SAndrew.Bardsley@arm.comRASSize=16
11710260SAndrew.Bardsley@arm.comchoiceCtrBits=2
11810260SAndrew.Bardsley@arm.comchoicePredictorSize=8192
11910260SAndrew.Bardsley@arm.comeventq_index=0
12010260SAndrew.Bardsley@arm.comglobalCtrBits=2
12110260SAndrew.Bardsley@arm.comglobalPredictorSize=8192
12210260SAndrew.Bardsley@arm.cominstShiftAmt=2
12310260SAndrew.Bardsley@arm.comlocalCtrBits=2
12410260SAndrew.Bardsley@arm.comlocalHistoryTableSize=2048
12510260SAndrew.Bardsley@arm.comlocalPredictorSize=2048
12610260SAndrew.Bardsley@arm.comnumThreads=1
12710260SAndrew.Bardsley@arm.compredType=tournament
12810260SAndrew.Bardsley@arm.com
12910260SAndrew.Bardsley@arm.com[system.cpu.dcache]
13010260SAndrew.Bardsley@arm.comtype=BaseCache
13110260SAndrew.Bardsley@arm.comchildren=tags
13210260SAndrew.Bardsley@arm.comaddr_ranges=0:18446744073709551615
13310260SAndrew.Bardsley@arm.comassoc=2
13410260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
13510260SAndrew.Bardsley@arm.comeventq_index=0
13610260SAndrew.Bardsley@arm.comforward_snoops=true
13710260SAndrew.Bardsley@arm.comhit_latency=2
13810260SAndrew.Bardsley@arm.comis_top_level=true
13910260SAndrew.Bardsley@arm.commax_miss_count=0
14010260SAndrew.Bardsley@arm.commshrs=4
14110260SAndrew.Bardsley@arm.comprefetch_on_access=false
14210260SAndrew.Bardsley@arm.comprefetcher=Null
14310260SAndrew.Bardsley@arm.comresponse_latency=2
14410260SAndrew.Bardsley@arm.comsequential_access=false
14510260SAndrew.Bardsley@arm.comsize=262144
14610260SAndrew.Bardsley@arm.comsystem=system
14710260SAndrew.Bardsley@arm.comtags=system.cpu.dcache.tags
14810260SAndrew.Bardsley@arm.comtgts_per_mshr=20
14910260SAndrew.Bardsley@arm.comtwo_queue=false
15010260SAndrew.Bardsley@arm.comwrite_buffers=8
15110260SAndrew.Bardsley@arm.comcpu_side=system.cpu.dcache_port
15210260SAndrew.Bardsley@arm.commem_side=system.cpu.toL2Bus.slave[1]
15310260SAndrew.Bardsley@arm.com
15410260SAndrew.Bardsley@arm.com[system.cpu.dcache.tags]
15510260SAndrew.Bardsley@arm.comtype=LRU
15610260SAndrew.Bardsley@arm.comassoc=2
15710260SAndrew.Bardsley@arm.comblock_size=64
15810260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
15910260SAndrew.Bardsley@arm.comeventq_index=0
16010260SAndrew.Bardsley@arm.comhit_latency=2
16110260SAndrew.Bardsley@arm.comsequential_access=false
16210260SAndrew.Bardsley@arm.comsize=262144
16310260SAndrew.Bardsley@arm.com
16410260SAndrew.Bardsley@arm.com[system.cpu.dstage2_mmu]
16510260SAndrew.Bardsley@arm.comtype=ArmStage2MMU
16610260SAndrew.Bardsley@arm.comchildren=stage2_tlb
16710260SAndrew.Bardsley@arm.comeventq_index=0
16810260SAndrew.Bardsley@arm.comstage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
16910260SAndrew.Bardsley@arm.comtlb=system.cpu.dtb
17010260SAndrew.Bardsley@arm.com
17110260SAndrew.Bardsley@arm.com[system.cpu.dstage2_mmu.stage2_tlb]
17210260SAndrew.Bardsley@arm.comtype=ArmTLB
17310260SAndrew.Bardsley@arm.comchildren=walker
17410260SAndrew.Bardsley@arm.comeventq_index=0
17510260SAndrew.Bardsley@arm.comis_stage2=true
17610260SAndrew.Bardsley@arm.comsize=32
17710260SAndrew.Bardsley@arm.comwalker=system.cpu.dstage2_mmu.stage2_tlb.walker
17810260SAndrew.Bardsley@arm.com
17910260SAndrew.Bardsley@arm.com[system.cpu.dstage2_mmu.stage2_tlb.walker]
18010260SAndrew.Bardsley@arm.comtype=ArmTableWalker
18110260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
18210260SAndrew.Bardsley@arm.comeventq_index=0
18310260SAndrew.Bardsley@arm.comis_stage2=true
18410260SAndrew.Bardsley@arm.comnum_squash_per_cycle=2
18510260SAndrew.Bardsley@arm.comsys=system
18610260SAndrew.Bardsley@arm.comport=system.cpu.toL2Bus.slave[5]
18710260SAndrew.Bardsley@arm.com
18810260SAndrew.Bardsley@arm.com[system.cpu.dtb]
18910260SAndrew.Bardsley@arm.comtype=ArmTLB
19010260SAndrew.Bardsley@arm.comchildren=walker
19110260SAndrew.Bardsley@arm.comeventq_index=0
19210260SAndrew.Bardsley@arm.comis_stage2=false
19310260SAndrew.Bardsley@arm.comsize=64
19410260SAndrew.Bardsley@arm.comwalker=system.cpu.dtb.walker
19510260SAndrew.Bardsley@arm.com
19610260SAndrew.Bardsley@arm.com[system.cpu.dtb.walker]
19710260SAndrew.Bardsley@arm.comtype=ArmTableWalker
19810260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
19910260SAndrew.Bardsley@arm.comeventq_index=0
20010260SAndrew.Bardsley@arm.comis_stage2=false
20110260SAndrew.Bardsley@arm.comnum_squash_per_cycle=2
20210260SAndrew.Bardsley@arm.comsys=system
20310260SAndrew.Bardsley@arm.comport=system.cpu.toL2Bus.slave[3]
20410260SAndrew.Bardsley@arm.com
20510260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits]
20610260SAndrew.Bardsley@arm.comtype=MinorFUPool
20710260SAndrew.Bardsley@arm.comchildren=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
20810260SAndrew.Bardsley@arm.comeventq_index=0
20910260SAndrew.Bardsley@arm.comfuncUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
21010260SAndrew.Bardsley@arm.com
21110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0]
21210260SAndrew.Bardsley@arm.comtype=MinorFU
21310260SAndrew.Bardsley@arm.comchildren=opClasses timings
21410315Snilay@cs.wisc.educantForwardFromFUIndices=
21510260SAndrew.Bardsley@arm.comeventq_index=0
21610260SAndrew.Bardsley@arm.comissueLat=1
21710260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses
21810260SAndrew.Bardsley@arm.comopLat=3
21910260SAndrew.Bardsley@arm.comtimings=system.cpu.executeFuncUnits.funcUnits0.timings
22010260SAndrew.Bardsley@arm.com
22110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0.opClasses]
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22410260SAndrew.Bardsley@arm.comeventq_index=0
22510260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
22610260SAndrew.Bardsley@arm.com
22710260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
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22910260SAndrew.Bardsley@arm.comeventq_index=0
23010260SAndrew.Bardsley@arm.comopClass=IntAlu
23110260SAndrew.Bardsley@arm.com
23210260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0.timings]
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24010260SAndrew.Bardsley@arm.commask=0
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24310260SAndrew.Bardsley@arm.comsrcRegsRelativeLats=2
24410260SAndrew.Bardsley@arm.comsuppress=false
24510260SAndrew.Bardsley@arm.com
24610260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
24710260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
24810260SAndrew.Bardsley@arm.comeventq_index=0
24910260SAndrew.Bardsley@arm.comopClasses=
25010260SAndrew.Bardsley@arm.com
25110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1]
25210260SAndrew.Bardsley@arm.comtype=MinorFU
25310260SAndrew.Bardsley@arm.comchildren=opClasses timings
25410315Snilay@cs.wisc.educantForwardFromFUIndices=
25510260SAndrew.Bardsley@arm.comeventq_index=0
25610260SAndrew.Bardsley@arm.comissueLat=1
25710260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
25810260SAndrew.Bardsley@arm.comopLat=3
25910260SAndrew.Bardsley@arm.comtimings=system.cpu.executeFuncUnits.funcUnits1.timings
26010260SAndrew.Bardsley@arm.com
26110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.opClasses]
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26510260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
26610260SAndrew.Bardsley@arm.com
26710260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
26810260SAndrew.Bardsley@arm.comtype=MinorOpClass
26910260SAndrew.Bardsley@arm.comeventq_index=0
27010260SAndrew.Bardsley@arm.comopClass=IntAlu
27110260SAndrew.Bardsley@arm.com
27210260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.timings]
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27410260SAndrew.Bardsley@arm.comchildren=opClasses
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27810260SAndrew.Bardsley@arm.comextraCommitLat=0
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28010260SAndrew.Bardsley@arm.commask=0
28110260SAndrew.Bardsley@arm.commatch=0
28210260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
28310260SAndrew.Bardsley@arm.comsrcRegsRelativeLats=2
28410260SAndrew.Bardsley@arm.comsuppress=false
28510260SAndrew.Bardsley@arm.com
28610260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
28710260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
28810260SAndrew.Bardsley@arm.comeventq_index=0
28910260SAndrew.Bardsley@arm.comopClasses=
29010260SAndrew.Bardsley@arm.com
29110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2]
29210260SAndrew.Bardsley@arm.comtype=MinorFU
29310260SAndrew.Bardsley@arm.comchildren=opClasses timings
29410315Snilay@cs.wisc.educantForwardFromFUIndices=
29510260SAndrew.Bardsley@arm.comeventq_index=0
29610260SAndrew.Bardsley@arm.comissueLat=1
29710260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
29810260SAndrew.Bardsley@arm.comopLat=3
29910260SAndrew.Bardsley@arm.comtimings=system.cpu.executeFuncUnits.funcUnits2.timings
30010260SAndrew.Bardsley@arm.com
30110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2.opClasses]
30210260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
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30510260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
30610260SAndrew.Bardsley@arm.com
30710260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
30810260SAndrew.Bardsley@arm.comtype=MinorOpClass
30910260SAndrew.Bardsley@arm.comeventq_index=0
31010260SAndrew.Bardsley@arm.comopClass=IntMult
31110260SAndrew.Bardsley@arm.com
31210260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2.timings]
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31910260SAndrew.Bardsley@arm.comextraCommitLatExpr=Null
32010260SAndrew.Bardsley@arm.commask=0
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32310260SAndrew.Bardsley@arm.comsrcRegsRelativeLats=0
32410260SAndrew.Bardsley@arm.comsuppress=false
32510260SAndrew.Bardsley@arm.com
32610260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
32710260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
32810260SAndrew.Bardsley@arm.comeventq_index=0
32910260SAndrew.Bardsley@arm.comopClasses=
33010260SAndrew.Bardsley@arm.com
33110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits3]
33210260SAndrew.Bardsley@arm.comtype=MinorFU
33310260SAndrew.Bardsley@arm.comchildren=opClasses
33410315Snilay@cs.wisc.educantForwardFromFUIndices=
33510260SAndrew.Bardsley@arm.comeventq_index=0
33610260SAndrew.Bardsley@arm.comissueLat=9
33710260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
33810260SAndrew.Bardsley@arm.comopLat=9
33910260SAndrew.Bardsley@arm.comtimings=
34010260SAndrew.Bardsley@arm.com
34110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits3.opClasses]
34210260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
34310260SAndrew.Bardsley@arm.comchildren=opClasses
34410260SAndrew.Bardsley@arm.comeventq_index=0
34510260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
34610260SAndrew.Bardsley@arm.com
34710260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
34810260SAndrew.Bardsley@arm.comtype=MinorOpClass
34910260SAndrew.Bardsley@arm.comeventq_index=0
35010260SAndrew.Bardsley@arm.comopClass=IntDiv
35110260SAndrew.Bardsley@arm.com
35210260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits4]
35310260SAndrew.Bardsley@arm.comtype=MinorFU
35410260SAndrew.Bardsley@arm.comchildren=opClasses timings
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68010260SAndrew.Bardsley@arm.com[system.cpu.itb]
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68210260SAndrew.Bardsley@arm.comchildren=walker
68310260SAndrew.Bardsley@arm.comeventq_index=0
68410260SAndrew.Bardsley@arm.comis_stage2=false
68510260SAndrew.Bardsley@arm.comsize=64
68610260SAndrew.Bardsley@arm.comwalker=system.cpu.itb.walker
68710260SAndrew.Bardsley@arm.com
68810260SAndrew.Bardsley@arm.com[system.cpu.itb.walker]
68910260SAndrew.Bardsley@arm.comtype=ArmTableWalker
69010260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
69110260SAndrew.Bardsley@arm.comeventq_index=0
69210260SAndrew.Bardsley@arm.comis_stage2=false
69310260SAndrew.Bardsley@arm.comnum_squash_per_cycle=2
69410260SAndrew.Bardsley@arm.comsys=system
69510260SAndrew.Bardsley@arm.comport=system.cpu.toL2Bus.slave[2]
69610260SAndrew.Bardsley@arm.com
69710260SAndrew.Bardsley@arm.com[system.cpu.l2cache]
69810260SAndrew.Bardsley@arm.comtype=BaseCache
69910260SAndrew.Bardsley@arm.comchildren=tags
70010260SAndrew.Bardsley@arm.comaddr_ranges=0:18446744073709551615
70110260SAndrew.Bardsley@arm.comassoc=8
70210260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
70310260SAndrew.Bardsley@arm.comeventq_index=0
70410260SAndrew.Bardsley@arm.comforward_snoops=true
70510260SAndrew.Bardsley@arm.comhit_latency=20
70610260SAndrew.Bardsley@arm.comis_top_level=false
70710260SAndrew.Bardsley@arm.commax_miss_count=0
70810260SAndrew.Bardsley@arm.commshrs=20
70910260SAndrew.Bardsley@arm.comprefetch_on_access=false
71010260SAndrew.Bardsley@arm.comprefetcher=Null
71110260SAndrew.Bardsley@arm.comresponse_latency=20
71210260SAndrew.Bardsley@arm.comsequential_access=false
71310260SAndrew.Bardsley@arm.comsize=2097152
71410260SAndrew.Bardsley@arm.comsystem=system
71510260SAndrew.Bardsley@arm.comtags=system.cpu.l2cache.tags
71610260SAndrew.Bardsley@arm.comtgts_per_mshr=12
71710260SAndrew.Bardsley@arm.comtwo_queue=false
71810260SAndrew.Bardsley@arm.comwrite_buffers=8
71910260SAndrew.Bardsley@arm.comcpu_side=system.cpu.toL2Bus.master[0]
72010260SAndrew.Bardsley@arm.commem_side=system.membus.slave[1]
72110260SAndrew.Bardsley@arm.com
72210260SAndrew.Bardsley@arm.com[system.cpu.l2cache.tags]
72310260SAndrew.Bardsley@arm.comtype=LRU
72410260SAndrew.Bardsley@arm.comassoc=8
72510260SAndrew.Bardsley@arm.comblock_size=64
72610260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
72710260SAndrew.Bardsley@arm.comeventq_index=0
72810260SAndrew.Bardsley@arm.comhit_latency=20
72910260SAndrew.Bardsley@arm.comsequential_access=false
73010260SAndrew.Bardsley@arm.comsize=2097152
73110260SAndrew.Bardsley@arm.com
73210260SAndrew.Bardsley@arm.com[system.cpu.toL2Bus]
73310260SAndrew.Bardsley@arm.comtype=CoherentBus
73410260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
73510260SAndrew.Bardsley@arm.comeventq_index=0
73610260SAndrew.Bardsley@arm.comheader_cycles=1
73710260SAndrew.Bardsley@arm.comsystem=system
73810260SAndrew.Bardsley@arm.comuse_default_range=false
73910260SAndrew.Bardsley@arm.comwidth=32
74010260SAndrew.Bardsley@arm.commaster=system.cpu.l2cache.cpu_side
74110260SAndrew.Bardsley@arm.comslave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
74210260SAndrew.Bardsley@arm.com
74310260SAndrew.Bardsley@arm.com[system.cpu.tracer]
74410260SAndrew.Bardsley@arm.comtype=ExeTracer
74510260SAndrew.Bardsley@arm.comeventq_index=0
74610260SAndrew.Bardsley@arm.com
74710260SAndrew.Bardsley@arm.com[system.cpu.workload]
74810260SAndrew.Bardsley@arm.comtype=LiveProcess
74910260SAndrew.Bardsley@arm.comcmd=twolf smred
75010260SAndrew.Bardsley@arm.comcwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
75110260SAndrew.Bardsley@arm.comegid=100
75210260SAndrew.Bardsley@arm.comenv=
75310260SAndrew.Bardsley@arm.comerrout=cerr
75410260SAndrew.Bardsley@arm.comeuid=100
75510260SAndrew.Bardsley@arm.comeventq_index=0
75610315Snilay@cs.wisc.eduexecutable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
75710260SAndrew.Bardsley@arm.comgid=100
75810260SAndrew.Bardsley@arm.cominput=cin
75910260SAndrew.Bardsley@arm.commax_stack_size=67108864
76010260SAndrew.Bardsley@arm.comoutput=cout
76110260SAndrew.Bardsley@arm.compid=100
76210260SAndrew.Bardsley@arm.comppid=99
76310260SAndrew.Bardsley@arm.comsimpoint=0
76410260SAndrew.Bardsley@arm.comsystem=system
76510260SAndrew.Bardsley@arm.comuid=100
76610260SAndrew.Bardsley@arm.com
76710260SAndrew.Bardsley@arm.com[system.cpu_clk_domain]
76810260SAndrew.Bardsley@arm.comtype=SrcClockDomain
76910260SAndrew.Bardsley@arm.comclock=500
77010315Snilay@cs.wisc.edudomain_id=-1
77110260SAndrew.Bardsley@arm.comeventq_index=0
77210315Snilay@cs.wisc.eduinit_perf_level=0
77310260SAndrew.Bardsley@arm.comvoltage_domain=system.voltage_domain
77410260SAndrew.Bardsley@arm.com
77510315Snilay@cs.wisc.edu[system.dvfs_handler]
77610315Snilay@cs.wisc.edutype=DVFSHandler
77710315Snilay@cs.wisc.edudomains=
77810315Snilay@cs.wisc.eduenable=false
77910315Snilay@cs.wisc.edueventq_index=0
78010315Snilay@cs.wisc.edusys_clk_domain=system.clk_domain
78110315Snilay@cs.wisc.edutransition_latency=100000000
78210315Snilay@cs.wisc.edu
78310260SAndrew.Bardsley@arm.com[system.membus]
78410260SAndrew.Bardsley@arm.comtype=CoherentBus
78510260SAndrew.Bardsley@arm.comclk_domain=system.clk_domain
78610260SAndrew.Bardsley@arm.comeventq_index=0
78710260SAndrew.Bardsley@arm.comheader_cycles=1
78810260SAndrew.Bardsley@arm.comsystem=system
78910260SAndrew.Bardsley@arm.comuse_default_range=false
79010260SAndrew.Bardsley@arm.comwidth=8
79110260SAndrew.Bardsley@arm.commaster=system.physmem.port
79210260SAndrew.Bardsley@arm.comslave=system.system_port system.cpu.l2cache.mem_side
79310260SAndrew.Bardsley@arm.com
79410260SAndrew.Bardsley@arm.com[system.physmem]
79510260SAndrew.Bardsley@arm.comtype=DRAMCtrl
79610260SAndrew.Bardsley@arm.comactivation_limit=4
79710260SAndrew.Bardsley@arm.comaddr_mapping=RoRaBaChCo
79810260SAndrew.Bardsley@arm.combanks_per_rank=8
79910260SAndrew.Bardsley@arm.comburst_length=8
80010260SAndrew.Bardsley@arm.comchannels=1
80110260SAndrew.Bardsley@arm.comclk_domain=system.clk_domain
80210260SAndrew.Bardsley@arm.comconf_table_reported=true
80310260SAndrew.Bardsley@arm.comdevice_bus_width=8
80410260SAndrew.Bardsley@arm.comdevice_rowbuffer_size=1024
80510260SAndrew.Bardsley@arm.comdevices_per_rank=8
80610260SAndrew.Bardsley@arm.comeventq_index=0
80710260SAndrew.Bardsley@arm.comin_addr_map=true
80810260SAndrew.Bardsley@arm.commax_accesses_per_row=16
80910260SAndrew.Bardsley@arm.commem_sched_policy=frfcfs
81010260SAndrew.Bardsley@arm.commin_writes_per_switch=16
81110260SAndrew.Bardsley@arm.comnull=false
81210260SAndrew.Bardsley@arm.compage_policy=open_adaptive
81310260SAndrew.Bardsley@arm.comrange=0:134217727
81410260SAndrew.Bardsley@arm.comranks_per_channel=2
81510260SAndrew.Bardsley@arm.comread_buffer_size=32
81610260SAndrew.Bardsley@arm.comstatic_backend_latency=10000
81710260SAndrew.Bardsley@arm.comstatic_frontend_latency=10000
81810260SAndrew.Bardsley@arm.comtBURST=5000
81910315Snilay@cs.wisc.edutCK=1250
82010260SAndrew.Bardsley@arm.comtCL=13750
82110260SAndrew.Bardsley@arm.comtRAS=35000
82210260SAndrew.Bardsley@arm.comtRCD=13750
82310260SAndrew.Bardsley@arm.comtREFI=7800000
82410315Snilay@cs.wisc.edutRFC=260000
82510260SAndrew.Bardsley@arm.comtRP=13750
82610315Snilay@cs.wisc.edutRRD=6000
82710315Snilay@cs.wisc.edutRTP=7500
82810315Snilay@cs.wisc.edutRTW=2500
82910315Snilay@cs.wisc.edutWR=15000
83010260SAndrew.Bardsley@arm.comtWTR=7500
83110315Snilay@cs.wisc.edutXAW=30000
83210260SAndrew.Bardsley@arm.comwrite_buffer_size=64
83310260SAndrew.Bardsley@arm.comwrite_high_thresh_perc=85
83410260SAndrew.Bardsley@arm.comwrite_low_thresh_perc=50
83510260SAndrew.Bardsley@arm.comport=system.membus.master[0]
83610260SAndrew.Bardsley@arm.com
83710260SAndrew.Bardsley@arm.com[system.voltage_domain]
83810260SAndrew.Bardsley@arm.comtype=VoltageDomain
83910260SAndrew.Bardsley@arm.comeventq_index=0
84010260SAndrew.Bardsley@arm.comvoltage=1.000000
84110260SAndrew.Bardsley@arm.com
842