config.ini revision 10260
110260SAndrew.Bardsley@arm.com[root]
210260SAndrew.Bardsley@arm.comtype=Root
310260SAndrew.Bardsley@arm.comchildren=system
410260SAndrew.Bardsley@arm.comeventq_index=0
510260SAndrew.Bardsley@arm.comfull_system=false
610260SAndrew.Bardsley@arm.comsim_quantum=0
710260SAndrew.Bardsley@arm.comtime_sync_enable=false
810260SAndrew.Bardsley@arm.comtime_sync_period=100000000000
910260SAndrew.Bardsley@arm.comtime_sync_spin_threshold=100000000
1010260SAndrew.Bardsley@arm.com
1110260SAndrew.Bardsley@arm.com[system]
1210260SAndrew.Bardsley@arm.comtype=System
1310260SAndrew.Bardsley@arm.comchildren=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
1410260SAndrew.Bardsley@arm.comboot_osflags=a
1510260SAndrew.Bardsley@arm.comcache_line_size=64
1610260SAndrew.Bardsley@arm.comclk_domain=system.clk_domain
1710260SAndrew.Bardsley@arm.comeventq_index=0
1810260SAndrew.Bardsley@arm.cominit_param=0
1910260SAndrew.Bardsley@arm.comkernel=
2010260SAndrew.Bardsley@arm.comload_addr_mask=1099511627775
2110260SAndrew.Bardsley@arm.comload_offset=0
2210260SAndrew.Bardsley@arm.commem_mode=timing
2310260SAndrew.Bardsley@arm.commem_ranges=
2410260SAndrew.Bardsley@arm.commemories=system.physmem
2510260SAndrew.Bardsley@arm.comnum_work_ids=16
2610260SAndrew.Bardsley@arm.comreadfile=
2710260SAndrew.Bardsley@arm.comsymbolfile=
2810260SAndrew.Bardsley@arm.comwork_begin_ckpt_count=0
2910260SAndrew.Bardsley@arm.comwork_begin_cpu_id_exit=-1
3010260SAndrew.Bardsley@arm.comwork_begin_exit_count=0
3110260SAndrew.Bardsley@arm.comwork_cpus_ckpt_count=0
3210260SAndrew.Bardsley@arm.comwork_end_ckpt_count=0
3310260SAndrew.Bardsley@arm.comwork_end_exit_count=0
3410260SAndrew.Bardsley@arm.comwork_item_id=-1
3510260SAndrew.Bardsley@arm.comsystem_port=system.membus.slave[0]
3610260SAndrew.Bardsley@arm.com
3710260SAndrew.Bardsley@arm.com[system.clk_domain]
3810260SAndrew.Bardsley@arm.comtype=SrcClockDomain
3910260SAndrew.Bardsley@arm.comclock=1000
4010260SAndrew.Bardsley@arm.comeventq_index=0
4110260SAndrew.Bardsley@arm.comvoltage_domain=system.voltage_domain
4210260SAndrew.Bardsley@arm.com
4310260SAndrew.Bardsley@arm.com[system.cpu]
4410260SAndrew.Bardsley@arm.comtype=MinorCPU
4510260SAndrew.Bardsley@arm.comchildren=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
4610260SAndrew.Bardsley@arm.combranchPred=system.cpu.branchPred
4710260SAndrew.Bardsley@arm.comchecker=Null
4810260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
4910260SAndrew.Bardsley@arm.comcpu_id=0
5010260SAndrew.Bardsley@arm.comdecodeCycleInput=true
5110260SAndrew.Bardsley@arm.comdecodeInputBufferSize=3
5210260SAndrew.Bardsley@arm.comdecodeInputWidth=2
5310260SAndrew.Bardsley@arm.comdecodeToExecuteForwardDelay=1
5410260SAndrew.Bardsley@arm.comdo_checkpoint_insts=true
5510260SAndrew.Bardsley@arm.comdo_quiesce=true
5610260SAndrew.Bardsley@arm.comdo_statistics_insts=true
5710260SAndrew.Bardsley@arm.comdstage2_mmu=system.cpu.dstage2_mmu
5810260SAndrew.Bardsley@arm.comdtb=system.cpu.dtb
5910260SAndrew.Bardsley@arm.comenableIdling=true
6010260SAndrew.Bardsley@arm.comeventq_index=0
6110260SAndrew.Bardsley@arm.comexecuteAllowEarlyMemoryIssue=true
6210260SAndrew.Bardsley@arm.comexecuteBranchDelay=1
6310260SAndrew.Bardsley@arm.comexecuteCommitLimit=2
6410260SAndrew.Bardsley@arm.comexecuteCycleInput=true
6510260SAndrew.Bardsley@arm.comexecuteFuncUnits=system.cpu.executeFuncUnits
6610260SAndrew.Bardsley@arm.comexecuteInputBufferSize=7
6710260SAndrew.Bardsley@arm.comexecuteInputWidth=2
6810260SAndrew.Bardsley@arm.comexecuteIssueLimit=2
6910260SAndrew.Bardsley@arm.comexecuteLSQMaxStoreBufferStoresPerCycle=2
7010260SAndrew.Bardsley@arm.comexecuteLSQRequestsQueueSize=1
7110260SAndrew.Bardsley@arm.comexecuteLSQStoreBufferSize=5
7210260SAndrew.Bardsley@arm.comexecuteLSQTransfersQueueSize=2
7310260SAndrew.Bardsley@arm.comexecuteMaxAccessesInMemory=2
7410260SAndrew.Bardsley@arm.comexecuteMemoryCommitLimit=1
7510260SAndrew.Bardsley@arm.comexecuteMemoryIssueLimit=1
7610260SAndrew.Bardsley@arm.comexecuteMemoryWidth=0
7710260SAndrew.Bardsley@arm.comexecuteSetTraceTimeOnCommit=true
7810260SAndrew.Bardsley@arm.comexecuteSetTraceTimeOnIssue=false
7910260SAndrew.Bardsley@arm.comfetch1FetchLimit=1
8010260SAndrew.Bardsley@arm.comfetch1LineSnapWidth=0
8110260SAndrew.Bardsley@arm.comfetch1LineWidth=0
8210260SAndrew.Bardsley@arm.comfetch1ToFetch2BackwardDelay=1
8310260SAndrew.Bardsley@arm.comfetch1ToFetch2ForwardDelay=1
8410260SAndrew.Bardsley@arm.comfetch2CycleInput=true
8510260SAndrew.Bardsley@arm.comfetch2InputBufferSize=2
8610260SAndrew.Bardsley@arm.comfetch2ToDecodeForwardDelay=1
8710260SAndrew.Bardsley@arm.comfunction_trace=false
8810260SAndrew.Bardsley@arm.comfunction_trace_start=0
8910260SAndrew.Bardsley@arm.cominterrupts=system.cpu.interrupts
9010260SAndrew.Bardsley@arm.comisa=system.cpu.isa
9110260SAndrew.Bardsley@arm.comistage2_mmu=system.cpu.istage2_mmu
9210260SAndrew.Bardsley@arm.comitb=system.cpu.itb
9310260SAndrew.Bardsley@arm.commax_insts_all_threads=0
9410260SAndrew.Bardsley@arm.commax_insts_any_thread=0
9510260SAndrew.Bardsley@arm.commax_loads_all_threads=0
9610260SAndrew.Bardsley@arm.commax_loads_any_thread=0
9710260SAndrew.Bardsley@arm.comnumThreads=1
9810260SAndrew.Bardsley@arm.comprofile=0
9910260SAndrew.Bardsley@arm.comprogress_interval=0
10010260SAndrew.Bardsley@arm.comsimpoint_start_insts=
10110260SAndrew.Bardsley@arm.comswitched_out=false
10210260SAndrew.Bardsley@arm.comsystem=system
10310260SAndrew.Bardsley@arm.comtracer=system.cpu.tracer
10410260SAndrew.Bardsley@arm.comworkload=system.cpu.workload
10510260SAndrew.Bardsley@arm.comdcache_port=system.cpu.dcache.cpu_side
10610260SAndrew.Bardsley@arm.comicache_port=system.cpu.icache.cpu_side
10710260SAndrew.Bardsley@arm.com
10810260SAndrew.Bardsley@arm.com[system.cpu.branchPred]
10910260SAndrew.Bardsley@arm.comtype=BranchPredictor
11010260SAndrew.Bardsley@arm.comBTBEntries=4096
11110260SAndrew.Bardsley@arm.comBTBTagSize=16
11210260SAndrew.Bardsley@arm.comRASSize=16
11310260SAndrew.Bardsley@arm.comchoiceCtrBits=2
11410260SAndrew.Bardsley@arm.comchoicePredictorSize=8192
11510260SAndrew.Bardsley@arm.comeventq_index=0
11610260SAndrew.Bardsley@arm.comglobalCtrBits=2
11710260SAndrew.Bardsley@arm.comglobalPredictorSize=8192
11810260SAndrew.Bardsley@arm.cominstShiftAmt=2
11910260SAndrew.Bardsley@arm.comlocalCtrBits=2
12010260SAndrew.Bardsley@arm.comlocalHistoryTableSize=2048
12110260SAndrew.Bardsley@arm.comlocalPredictorSize=2048
12210260SAndrew.Bardsley@arm.comnumThreads=1
12310260SAndrew.Bardsley@arm.compredType=tournament
12410260SAndrew.Bardsley@arm.com
12510260SAndrew.Bardsley@arm.com[system.cpu.dcache]
12610260SAndrew.Bardsley@arm.comtype=BaseCache
12710260SAndrew.Bardsley@arm.comchildren=tags
12810260SAndrew.Bardsley@arm.comaddr_ranges=0:18446744073709551615
12910260SAndrew.Bardsley@arm.comassoc=2
13010260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
13110260SAndrew.Bardsley@arm.comeventq_index=0
13210260SAndrew.Bardsley@arm.comforward_snoops=true
13310260SAndrew.Bardsley@arm.comhit_latency=2
13410260SAndrew.Bardsley@arm.comis_top_level=true
13510260SAndrew.Bardsley@arm.commax_miss_count=0
13610260SAndrew.Bardsley@arm.commshrs=4
13710260SAndrew.Bardsley@arm.comprefetch_on_access=false
13810260SAndrew.Bardsley@arm.comprefetcher=Null
13910260SAndrew.Bardsley@arm.comresponse_latency=2
14010260SAndrew.Bardsley@arm.comsequential_access=false
14110260SAndrew.Bardsley@arm.comsize=262144
14210260SAndrew.Bardsley@arm.comsystem=system
14310260SAndrew.Bardsley@arm.comtags=system.cpu.dcache.tags
14410260SAndrew.Bardsley@arm.comtgts_per_mshr=20
14510260SAndrew.Bardsley@arm.comtwo_queue=false
14610260SAndrew.Bardsley@arm.comwrite_buffers=8
14710260SAndrew.Bardsley@arm.comcpu_side=system.cpu.dcache_port
14810260SAndrew.Bardsley@arm.commem_side=system.cpu.toL2Bus.slave[1]
14910260SAndrew.Bardsley@arm.com
15010260SAndrew.Bardsley@arm.com[system.cpu.dcache.tags]
15110260SAndrew.Bardsley@arm.comtype=LRU
15210260SAndrew.Bardsley@arm.comassoc=2
15310260SAndrew.Bardsley@arm.comblock_size=64
15410260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
15510260SAndrew.Bardsley@arm.comeventq_index=0
15610260SAndrew.Bardsley@arm.comhit_latency=2
15710260SAndrew.Bardsley@arm.comsequential_access=false
15810260SAndrew.Bardsley@arm.comsize=262144
15910260SAndrew.Bardsley@arm.com
16010260SAndrew.Bardsley@arm.com[system.cpu.dstage2_mmu]
16110260SAndrew.Bardsley@arm.comtype=ArmStage2MMU
16210260SAndrew.Bardsley@arm.comchildren=stage2_tlb
16310260SAndrew.Bardsley@arm.comeventq_index=0
16410260SAndrew.Bardsley@arm.comstage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
16510260SAndrew.Bardsley@arm.comtlb=system.cpu.dtb
16610260SAndrew.Bardsley@arm.com
16710260SAndrew.Bardsley@arm.com[system.cpu.dstage2_mmu.stage2_tlb]
16810260SAndrew.Bardsley@arm.comtype=ArmTLB
16910260SAndrew.Bardsley@arm.comchildren=walker
17010260SAndrew.Bardsley@arm.comeventq_index=0
17110260SAndrew.Bardsley@arm.comis_stage2=true
17210260SAndrew.Bardsley@arm.comsize=32
17310260SAndrew.Bardsley@arm.comwalker=system.cpu.dstage2_mmu.stage2_tlb.walker
17410260SAndrew.Bardsley@arm.com
17510260SAndrew.Bardsley@arm.com[system.cpu.dstage2_mmu.stage2_tlb.walker]
17610260SAndrew.Bardsley@arm.comtype=ArmTableWalker
17710260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
17810260SAndrew.Bardsley@arm.comeventq_index=0
17910260SAndrew.Bardsley@arm.comis_stage2=true
18010260SAndrew.Bardsley@arm.comnum_squash_per_cycle=2
18110260SAndrew.Bardsley@arm.comsys=system
18210260SAndrew.Bardsley@arm.comport=system.cpu.toL2Bus.slave[5]
18310260SAndrew.Bardsley@arm.com
18410260SAndrew.Bardsley@arm.com[system.cpu.dtb]
18510260SAndrew.Bardsley@arm.comtype=ArmTLB
18610260SAndrew.Bardsley@arm.comchildren=walker
18710260SAndrew.Bardsley@arm.comeventq_index=0
18810260SAndrew.Bardsley@arm.comis_stage2=false
18910260SAndrew.Bardsley@arm.comsize=64
19010260SAndrew.Bardsley@arm.comwalker=system.cpu.dtb.walker
19110260SAndrew.Bardsley@arm.com
19210260SAndrew.Bardsley@arm.com[system.cpu.dtb.walker]
19310260SAndrew.Bardsley@arm.comtype=ArmTableWalker
19410260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
19510260SAndrew.Bardsley@arm.comeventq_index=0
19610260SAndrew.Bardsley@arm.comis_stage2=false
19710260SAndrew.Bardsley@arm.comnum_squash_per_cycle=2
19810260SAndrew.Bardsley@arm.comsys=system
19910260SAndrew.Bardsley@arm.comport=system.cpu.toL2Bus.slave[3]
20010260SAndrew.Bardsley@arm.com
20110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits]
20210260SAndrew.Bardsley@arm.comtype=MinorFUPool
20310260SAndrew.Bardsley@arm.comchildren=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6
20410260SAndrew.Bardsley@arm.comeventq_index=0
20510260SAndrew.Bardsley@arm.comfuncUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6
20610260SAndrew.Bardsley@arm.com
20710260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0]
20810260SAndrew.Bardsley@arm.comtype=MinorFU
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21010260SAndrew.Bardsley@arm.comeventq_index=0
21110260SAndrew.Bardsley@arm.comissueLat=1
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21310260SAndrew.Bardsley@arm.comopLat=3
21410260SAndrew.Bardsley@arm.comtimings=system.cpu.executeFuncUnits.funcUnits0.timings
21510260SAndrew.Bardsley@arm.com
21610260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0.opClasses]
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22010260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses
22110260SAndrew.Bardsley@arm.com
22210260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses]
22310260SAndrew.Bardsley@arm.comtype=MinorOpClass
22410260SAndrew.Bardsley@arm.comeventq_index=0
22510260SAndrew.Bardsley@arm.comopClass=IntAlu
22610260SAndrew.Bardsley@arm.com
22710260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0.timings]
22810260SAndrew.Bardsley@arm.comtype=MinorFUTiming
22910260SAndrew.Bardsley@arm.comchildren=opClasses
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23110260SAndrew.Bardsley@arm.comeventq_index=0
23210260SAndrew.Bardsley@arm.comextraAssumedLat=0
23310260SAndrew.Bardsley@arm.comextraCommitLat=0
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23510260SAndrew.Bardsley@arm.commask=0
23610260SAndrew.Bardsley@arm.commatch=0
23710260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses
23810260SAndrew.Bardsley@arm.comsrcRegsRelativeLats=2
23910260SAndrew.Bardsley@arm.comsuppress=false
24010260SAndrew.Bardsley@arm.com
24110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses]
24210260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
24310260SAndrew.Bardsley@arm.comeventq_index=0
24410260SAndrew.Bardsley@arm.comopClasses=
24510260SAndrew.Bardsley@arm.com
24610260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1]
24710260SAndrew.Bardsley@arm.comtype=MinorFU
24810260SAndrew.Bardsley@arm.comchildren=opClasses timings
24910260SAndrew.Bardsley@arm.comeventq_index=0
25010260SAndrew.Bardsley@arm.comissueLat=1
25110260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses
25210260SAndrew.Bardsley@arm.comopLat=3
25310260SAndrew.Bardsley@arm.comtimings=system.cpu.executeFuncUnits.funcUnits1.timings
25410260SAndrew.Bardsley@arm.com
25510260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.opClasses]
25610260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
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25810260SAndrew.Bardsley@arm.comeventq_index=0
25910260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses
26010260SAndrew.Bardsley@arm.com
26110260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses]
26210260SAndrew.Bardsley@arm.comtype=MinorOpClass
26310260SAndrew.Bardsley@arm.comeventq_index=0
26410260SAndrew.Bardsley@arm.comopClass=IntAlu
26510260SAndrew.Bardsley@arm.com
26610260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.timings]
26710260SAndrew.Bardsley@arm.comtype=MinorFUTiming
26810260SAndrew.Bardsley@arm.comchildren=opClasses
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27010260SAndrew.Bardsley@arm.comeventq_index=0
27110260SAndrew.Bardsley@arm.comextraAssumedLat=0
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27410260SAndrew.Bardsley@arm.commask=0
27510260SAndrew.Bardsley@arm.commatch=0
27610260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses
27710260SAndrew.Bardsley@arm.comsrcRegsRelativeLats=2
27810260SAndrew.Bardsley@arm.comsuppress=false
27910260SAndrew.Bardsley@arm.com
28010260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses]
28110260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
28210260SAndrew.Bardsley@arm.comeventq_index=0
28310260SAndrew.Bardsley@arm.comopClasses=
28410260SAndrew.Bardsley@arm.com
28510260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2]
28610260SAndrew.Bardsley@arm.comtype=MinorFU
28710260SAndrew.Bardsley@arm.comchildren=opClasses timings
28810260SAndrew.Bardsley@arm.comeventq_index=0
28910260SAndrew.Bardsley@arm.comissueLat=1
29010260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses
29110260SAndrew.Bardsley@arm.comopLat=3
29210260SAndrew.Bardsley@arm.comtimings=system.cpu.executeFuncUnits.funcUnits2.timings
29310260SAndrew.Bardsley@arm.com
29410260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2.opClasses]
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29710260SAndrew.Bardsley@arm.comeventq_index=0
29810260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses
29910260SAndrew.Bardsley@arm.com
30010260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses]
30110260SAndrew.Bardsley@arm.comtype=MinorOpClass
30210260SAndrew.Bardsley@arm.comeventq_index=0
30310260SAndrew.Bardsley@arm.comopClass=IntMult
30410260SAndrew.Bardsley@arm.com
30510260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2.timings]
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31310260SAndrew.Bardsley@arm.commask=0
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31610260SAndrew.Bardsley@arm.comsrcRegsRelativeLats=0
31710260SAndrew.Bardsley@arm.comsuppress=false
31810260SAndrew.Bardsley@arm.com
31910260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses]
32010260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
32110260SAndrew.Bardsley@arm.comeventq_index=0
32210260SAndrew.Bardsley@arm.comopClasses=
32310260SAndrew.Bardsley@arm.com
32410260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits3]
32510260SAndrew.Bardsley@arm.comtype=MinorFU
32610260SAndrew.Bardsley@arm.comchildren=opClasses
32710260SAndrew.Bardsley@arm.comeventq_index=0
32810260SAndrew.Bardsley@arm.comissueLat=9
32910260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses
33010260SAndrew.Bardsley@arm.comopLat=9
33110260SAndrew.Bardsley@arm.comtimings=
33210260SAndrew.Bardsley@arm.com
33310260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits3.opClasses]
33410260SAndrew.Bardsley@arm.comtype=MinorOpClassSet
33510260SAndrew.Bardsley@arm.comchildren=opClasses
33610260SAndrew.Bardsley@arm.comeventq_index=0
33710260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses
33810260SAndrew.Bardsley@arm.com
33910260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses]
34010260SAndrew.Bardsley@arm.comtype=MinorOpClass
34110260SAndrew.Bardsley@arm.comeventq_index=0
34210260SAndrew.Bardsley@arm.comopClass=IntDiv
34310260SAndrew.Bardsley@arm.com
34410260SAndrew.Bardsley@arm.com[system.cpu.executeFuncUnits.funcUnits4]
34510260SAndrew.Bardsley@arm.comtype=MinorFU
34610260SAndrew.Bardsley@arm.comchildren=opClasses timings
34710260SAndrew.Bardsley@arm.comeventq_index=0
34810260SAndrew.Bardsley@arm.comissueLat=1
34910260SAndrew.Bardsley@arm.comopClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses
35010260SAndrew.Bardsley@arm.comopLat=6
35110260SAndrew.Bardsley@arm.comtimings=system.cpu.executeFuncUnits.funcUnits4.timings
35210260SAndrew.Bardsley@arm.com
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68110260SAndrew.Bardsley@arm.comis_stage2=false
68210260SAndrew.Bardsley@arm.comnum_squash_per_cycle=2
68310260SAndrew.Bardsley@arm.comsys=system
68410260SAndrew.Bardsley@arm.comport=system.cpu.toL2Bus.slave[2]
68510260SAndrew.Bardsley@arm.com
68610260SAndrew.Bardsley@arm.com[system.cpu.l2cache]
68710260SAndrew.Bardsley@arm.comtype=BaseCache
68810260SAndrew.Bardsley@arm.comchildren=tags
68910260SAndrew.Bardsley@arm.comaddr_ranges=0:18446744073709551615
69010260SAndrew.Bardsley@arm.comassoc=8
69110260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
69210260SAndrew.Bardsley@arm.comeventq_index=0
69310260SAndrew.Bardsley@arm.comforward_snoops=true
69410260SAndrew.Bardsley@arm.comhit_latency=20
69510260SAndrew.Bardsley@arm.comis_top_level=false
69610260SAndrew.Bardsley@arm.commax_miss_count=0
69710260SAndrew.Bardsley@arm.commshrs=20
69810260SAndrew.Bardsley@arm.comprefetch_on_access=false
69910260SAndrew.Bardsley@arm.comprefetcher=Null
70010260SAndrew.Bardsley@arm.comresponse_latency=20
70110260SAndrew.Bardsley@arm.comsequential_access=false
70210260SAndrew.Bardsley@arm.comsize=2097152
70310260SAndrew.Bardsley@arm.comsystem=system
70410260SAndrew.Bardsley@arm.comtags=system.cpu.l2cache.tags
70510260SAndrew.Bardsley@arm.comtgts_per_mshr=12
70610260SAndrew.Bardsley@arm.comtwo_queue=false
70710260SAndrew.Bardsley@arm.comwrite_buffers=8
70810260SAndrew.Bardsley@arm.comcpu_side=system.cpu.toL2Bus.master[0]
70910260SAndrew.Bardsley@arm.commem_side=system.membus.slave[1]
71010260SAndrew.Bardsley@arm.com
71110260SAndrew.Bardsley@arm.com[system.cpu.l2cache.tags]
71210260SAndrew.Bardsley@arm.comtype=LRU
71310260SAndrew.Bardsley@arm.comassoc=8
71410260SAndrew.Bardsley@arm.comblock_size=64
71510260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
71610260SAndrew.Bardsley@arm.comeventq_index=0
71710260SAndrew.Bardsley@arm.comhit_latency=20
71810260SAndrew.Bardsley@arm.comsequential_access=false
71910260SAndrew.Bardsley@arm.comsize=2097152
72010260SAndrew.Bardsley@arm.com
72110260SAndrew.Bardsley@arm.com[system.cpu.toL2Bus]
72210260SAndrew.Bardsley@arm.comtype=CoherentBus
72310260SAndrew.Bardsley@arm.comclk_domain=system.cpu_clk_domain
72410260SAndrew.Bardsley@arm.comeventq_index=0
72510260SAndrew.Bardsley@arm.comheader_cycles=1
72610260SAndrew.Bardsley@arm.comsystem=system
72710260SAndrew.Bardsley@arm.comuse_default_range=false
72810260SAndrew.Bardsley@arm.comwidth=32
72910260SAndrew.Bardsley@arm.commaster=system.cpu.l2cache.cpu_side
73010260SAndrew.Bardsley@arm.comslave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
73110260SAndrew.Bardsley@arm.com
73210260SAndrew.Bardsley@arm.com[system.cpu.tracer]
73310260SAndrew.Bardsley@arm.comtype=ExeTracer
73410260SAndrew.Bardsley@arm.comeventq_index=0
73510260SAndrew.Bardsley@arm.com
73610260SAndrew.Bardsley@arm.com[system.cpu.workload]
73710260SAndrew.Bardsley@arm.comtype=LiveProcess
73810260SAndrew.Bardsley@arm.comcmd=twolf smred
73910260SAndrew.Bardsley@arm.comcwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
74010260SAndrew.Bardsley@arm.comegid=100
74110260SAndrew.Bardsley@arm.comenv=
74210260SAndrew.Bardsley@arm.comerrout=cerr
74310260SAndrew.Bardsley@arm.comeuid=100
74410260SAndrew.Bardsley@arm.comeventq_index=0
74510260SAndrew.Bardsley@arm.comexecutable=/arm/projectscratch/pd/sysrandd/dist/cpu2000/binaries/arm/linux/twolf
74610260SAndrew.Bardsley@arm.comgid=100
74710260SAndrew.Bardsley@arm.cominput=cin
74810260SAndrew.Bardsley@arm.commax_stack_size=67108864
74910260SAndrew.Bardsley@arm.comoutput=cout
75010260SAndrew.Bardsley@arm.compid=100
75110260SAndrew.Bardsley@arm.comppid=99
75210260SAndrew.Bardsley@arm.comsimpoint=0
75310260SAndrew.Bardsley@arm.comsystem=system
75410260SAndrew.Bardsley@arm.comuid=100
75510260SAndrew.Bardsley@arm.com
75610260SAndrew.Bardsley@arm.com[system.cpu_clk_domain]
75710260SAndrew.Bardsley@arm.comtype=SrcClockDomain
75810260SAndrew.Bardsley@arm.comclock=500
75910260SAndrew.Bardsley@arm.comeventq_index=0
76010260SAndrew.Bardsley@arm.comvoltage_domain=system.voltage_domain
76110260SAndrew.Bardsley@arm.com
76210260SAndrew.Bardsley@arm.com[system.membus]
76310260SAndrew.Bardsley@arm.comtype=CoherentBus
76410260SAndrew.Bardsley@arm.comclk_domain=system.clk_domain
76510260SAndrew.Bardsley@arm.comeventq_index=0
76610260SAndrew.Bardsley@arm.comheader_cycles=1
76710260SAndrew.Bardsley@arm.comsystem=system
76810260SAndrew.Bardsley@arm.comuse_default_range=false
76910260SAndrew.Bardsley@arm.comwidth=8
77010260SAndrew.Bardsley@arm.commaster=system.physmem.port
77110260SAndrew.Bardsley@arm.comslave=system.system_port system.cpu.l2cache.mem_side
77210260SAndrew.Bardsley@arm.com
77310260SAndrew.Bardsley@arm.com[system.physmem]
77410260SAndrew.Bardsley@arm.comtype=DRAMCtrl
77510260SAndrew.Bardsley@arm.comactivation_limit=4
77610260SAndrew.Bardsley@arm.comaddr_mapping=RoRaBaChCo
77710260SAndrew.Bardsley@arm.combanks_per_rank=8
77810260SAndrew.Bardsley@arm.comburst_length=8
77910260SAndrew.Bardsley@arm.comchannels=1
78010260SAndrew.Bardsley@arm.comclk_domain=system.clk_domain
78110260SAndrew.Bardsley@arm.comconf_table_reported=true
78210260SAndrew.Bardsley@arm.comdevice_bus_width=8
78310260SAndrew.Bardsley@arm.comdevice_rowbuffer_size=1024
78410260SAndrew.Bardsley@arm.comdevices_per_rank=8
78510260SAndrew.Bardsley@arm.comeventq_index=0
78610260SAndrew.Bardsley@arm.comin_addr_map=true
78710260SAndrew.Bardsley@arm.commax_accesses_per_row=16
78810260SAndrew.Bardsley@arm.commem_sched_policy=frfcfs
78910260SAndrew.Bardsley@arm.commin_writes_per_switch=16
79010260SAndrew.Bardsley@arm.comnull=false
79110260SAndrew.Bardsley@arm.compage_policy=open_adaptive
79210260SAndrew.Bardsley@arm.comrange=0:134217727
79310260SAndrew.Bardsley@arm.comranks_per_channel=2
79410260SAndrew.Bardsley@arm.comread_buffer_size=32
79510260SAndrew.Bardsley@arm.comstatic_backend_latency=10000
79610260SAndrew.Bardsley@arm.comstatic_frontend_latency=10000
79710260SAndrew.Bardsley@arm.comtBURST=5000
79810260SAndrew.Bardsley@arm.comtCL=13750
79910260SAndrew.Bardsley@arm.comtRAS=35000
80010260SAndrew.Bardsley@arm.comtRCD=13750
80110260SAndrew.Bardsley@arm.comtREFI=7800000
80210260SAndrew.Bardsley@arm.comtRFC=300000
80310260SAndrew.Bardsley@arm.comtRP=13750
80410260SAndrew.Bardsley@arm.comtRRD=6250
80510260SAndrew.Bardsley@arm.comtWTR=7500
80610260SAndrew.Bardsley@arm.comtXAW=40000
80710260SAndrew.Bardsley@arm.comwrite_buffer_size=64
80810260SAndrew.Bardsley@arm.comwrite_high_thresh_perc=85
80910260SAndrew.Bardsley@arm.comwrite_low_thresh_perc=50
81010260SAndrew.Bardsley@arm.comport=system.membus.master[0]
81110260SAndrew.Bardsley@arm.com
81210260SAndrew.Bardsley@arm.com[system.voltage_domain]
81310260SAndrew.Bardsley@arm.comtype=VoltageDomain
81410260SAndrew.Bardsley@arm.comeventq_index=0
81510260SAndrew.Bardsley@arm.comvoltage=1.000000
81610260SAndrew.Bardsley@arm.com
817