stats.txt revision 10220:9eab5efc02e8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.882581 # Number of seconds simulated 4sim_ticks 5882580526000 # Number of ticks simulated 5final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 693030 # Simulator instruction rate (inst/s) 8host_op_rate 1079804 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1355284560 # Simulator tick rate (ticks/s) 10host_mem_usage 288492 # Number of bytes of host memory used 11host_seconds 4340.48 # Real time elapsed on the host 12sim_insts 3008081022 # Number of instructions simulated 13sim_ops 4686862596 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory 18system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65178944 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65178944 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1958234 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1958909 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1018421 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11079992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) 39system.membus.throughput 32392097 # Throughput (bytes/s) 40system.membus.trans_dist::ReadReq 1177614 # Transaction distribution 41system.membus.trans_dist::ReadResp 1177614 # Transaction distribution 42system.membus.trans_dist::Writeback 1018421 # Transaction distribution 43system.membus.trans_dist::ReadExReq 781295 # Transaction distribution 44system.membus.trans_dist::ReadExResp 781295 # Transaction distribution 45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) 47system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) 48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) 49system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) 50system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) 51system.membus.data_through_bus 190549120 # Total data (bytes) 52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 53system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks) 54system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 55system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) 56system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 57system.cpu_clk_domain.clock 500 # Clock period in ticks 58system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 59system.cpu.workload.num_syscalls 46 # Number of system calls 60system.cpu.numCycles 11765161052 # number of cpu cycles simulated 61system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 62system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 63system.cpu.committedInsts 3008081022 # Number of instructions committed 64system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed 65system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses 66system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 67system.cpu.num_func_calls 33534539 # number of times a function call or return occured 68system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls 69system.cpu.num_int_insts 4684368009 # number of integer instructions 70system.cpu.num_fp_insts 0 # number of float instructions 71system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read 72system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written 73system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 74system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 75system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read 76system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written 77system.cpu.num_mem_refs 1677713084 # number of memory refs 78system.cpu.num_load_insts 1239184746 # Number of load instructions 79system.cpu.num_store_insts 438528338 # Number of store instructions 80system.cpu.num_idle_cycles 0 # Number of idle cycles 81system.cpu.num_busy_cycles 11765161052 # Number of busy cycles 82system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 83system.cpu.idle_fraction 0 # Percentage of idle cycles 84system.cpu.Branches 248500691 # Number of branches fetched 85system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction 86system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction 87system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction 88system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction 89system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction 90system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction 91system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction 92system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction 93system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction 94system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction 95system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction 96system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction 97system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction 98system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction 99system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction 100system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction 101system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction 102system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction 103system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction 104system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction 105system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction 106system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction 107system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction 108system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction 109system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction 110system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction 111system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction 112system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction 113system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction 114system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction 115system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction 116system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction 117system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 118system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 119system.cpu.op_class::total 4686862596 # Class of executed instruction 120system.cpu.icache.tags.replacements 10 # number of replacements 121system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use 122system.cpu.icache.tags.total_refs 4013232208 # Total number of references to valid blocks. 123system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. 124system.cpu.icache.tags.avg_refs 5945529.197037 # Average number of references to valid blocks. 125system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 126system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor 127system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy 128system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy 129system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id 130system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 131system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id 132system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id 133system.cpu.icache.tags.tag_accesses 8026466441 # Number of tag accesses 134system.cpu.icache.tags.data_accesses 8026466441 # Number of data accesses 135system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits 136system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits 137system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits 138system.cpu.icache.demand_hits::total 4013232208 # number of demand (read+write) hits 139system.cpu.icache.overall_hits::cpu.inst 4013232208 # number of overall hits 140system.cpu.icache.overall_hits::total 4013232208 # number of overall hits 141system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 142system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses 143system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 144system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses 145system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses 146system.cpu.icache.overall_misses::total 675 # number of overall misses 147system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles 148system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles 149system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles 150system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles 151system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles 152system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles 153system.cpu.icache.ReadReq_accesses::cpu.inst 4013232883 # number of ReadReq accesses(hits+misses) 154system.cpu.icache.ReadReq_accesses::total 4013232883 # number of ReadReq accesses(hits+misses) 155system.cpu.icache.demand_accesses::cpu.inst 4013232883 # number of demand (read+write) accesses 156system.cpu.icache.demand_accesses::total 4013232883 # number of demand (read+write) accesses 157system.cpu.icache.overall_accesses::cpu.inst 4013232883 # number of overall (read+write) accesses 158system.cpu.icache.overall_accesses::total 4013232883 # number of overall (read+write) accesses 159system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 160system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 161system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 162system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 163system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 164system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 165system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency 166system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency 167system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency 168system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency 169system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency 170system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency 171system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 175system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 176system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 177system.cpu.icache.fast_writes 0 # number of fast writes performed 178system.cpu.icache.cache_copies 0 # number of cache copies performed 179system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 180system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses 181system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 182system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses 183system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 184system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses 185system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles 186system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles 187system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles 188system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles 189system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles 190system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles 191system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 192system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 193system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 194system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 195system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 196system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 197system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency 198system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency 199system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency 200system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency 201system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency 202system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency 203system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 204system.cpu.l2cache.tags.replacements 1926197 # number of replacements 205system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use 206system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. 207system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. 208system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. 209system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. 210system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor 211system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor 212system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor 213system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy 214system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy 215system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy 216system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy 217system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id 218system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 219system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id 220system.cpu.l2cache.tags.age_task_id_blocks_1024::2 996 # Occupied blocks per task id 221system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id 222system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27921 # Occupied blocks per task id 223system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id 224system.cpu.l2cache.tags.tag_accesses 106336271 # Number of tag accesses 225system.cpu.l2cache.tags.data_accesses 106336271 # Number of data accesses 226system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits 227system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits 228system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits 229system.cpu.l2cache.Writeback_hits::total 3697956 # number of Writeback hits 230system.cpu.l2cache.ReadExReq_hits::cpu.data 1108532 # number of ReadExReq hits 231system.cpu.l2cache.ReadExReq_hits::total 1108532 # number of ReadExReq hits 232system.cpu.l2cache.demand_hits::cpu.data 7154443 # number of demand (read+write) hits 233system.cpu.l2cache.demand_hits::total 7154443 # number of demand (read+write) hits 234system.cpu.l2cache.overall_hits::cpu.data 7154443 # number of overall hits 235system.cpu.l2cache.overall_hits::total 7154443 # number of overall hits 236system.cpu.l2cache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses 237system.cpu.l2cache.ReadReq_misses::cpu.data 1176939 # number of ReadReq misses 238system.cpu.l2cache.ReadReq_misses::total 1177614 # number of ReadReq misses 239system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses 240system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses 241system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses 242system.cpu.l2cache.demand_misses::cpu.data 1958234 # number of demand (read+write) misses 243system.cpu.l2cache.demand_misses::total 1958909 # number of demand (read+write) misses 244system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses 245system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses 246system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses 247system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles 248system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles 249system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles 250system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles 251system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles 252system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles 253system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles 254system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles 255system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles 256system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles 257system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles 258system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) 259system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) 260system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) 261system.cpu.l2cache.Writeback_accesses::writebacks 3697956 # number of Writeback accesses(hits+misses) 262system.cpu.l2cache.Writeback_accesses::total 3697956 # number of Writeback accesses(hits+misses) 263system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) 264system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) 265system.cpu.l2cache.demand_accesses::cpu.inst 675 # number of demand (read+write) accesses 266system.cpu.l2cache.demand_accesses::cpu.data 9112677 # number of demand (read+write) accesses 267system.cpu.l2cache.demand_accesses::total 9113352 # number of demand (read+write) accesses 268system.cpu.l2cache.overall_accesses::cpu.inst 675 # number of overall (read+write) accesses 269system.cpu.l2cache.overall_accesses::cpu.data 9112677 # number of overall (read+write) accesses 270system.cpu.l2cache.overall_accesses::total 9113352 # number of overall (read+write) accesses 271system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses 272system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162947 # miss rate for ReadReq accesses 273system.cpu.l2cache.ReadReq_miss_rate::total 0.163025 # miss rate for ReadReq accesses 274system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413421 # miss rate for ReadExReq accesses 275system.cpu.l2cache.ReadExReq_miss_rate::total 0.413421 # miss rate for ReadExReq accesses 276system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 277system.cpu.l2cache.demand_miss_rate::cpu.data 0.214891 # miss rate for demand accesses 278system.cpu.l2cache.demand_miss_rate::total 0.214949 # miss rate for demand accesses 279system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 280system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses 281system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses 282system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency 283system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency 284system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency 285system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency 286system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency 287system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency 288system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency 289system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency 290system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency 291system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency 292system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency 293system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 294system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 295system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 296system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 297system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 298system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 299system.cpu.l2cache.fast_writes 0 # number of fast writes performed 300system.cpu.l2cache.cache_copies 0 # number of cache copies performed 301system.cpu.l2cache.writebacks::writebacks 1018421 # number of writebacks 302system.cpu.l2cache.writebacks::total 1018421 # number of writebacks 303system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses 304system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1176939 # number of ReadReq MSHR misses 305system.cpu.l2cache.ReadReq_mshr_misses::total 1177614 # number of ReadReq MSHR misses 306system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses 307system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # number of ReadExReq MSHR misses 308system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses 309system.cpu.l2cache.demand_mshr_misses::cpu.data 1958234 # number of demand (read+write) MSHR misses 310system.cpu.l2cache.demand_mshr_misses::total 1958909 # number of demand (read+write) MSHR misses 311system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses 312system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses 313system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses 314system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles 315system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles 316system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles 317system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles 318system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles 319system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles 320system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles 321system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles 322system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles 323system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles 324system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles 325system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses 326system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses 327system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses 328system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413421 # mshr miss rate for ReadExReq accesses 329system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413421 # mshr miss rate for ReadExReq accesses 330system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 331system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for demand accesses 332system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 # mshr miss rate for demand accesses 333system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 334system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses 335system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses 336system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency 337system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency 338system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency 339system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency 340system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency 341system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency 342system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency 343system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency 344system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency 345system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency 346system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency 347system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 348system.cpu.dcache.tags.replacements 9108581 # number of replacements 349system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use 350system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. 351system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. 352system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. 353system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. 354system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor 355system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy 356system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy 357system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 358system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 359system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 363system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 364system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses 365system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses 366system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits 367system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits 368system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits 369system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits 370system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits 371system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits 372system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits 373system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits 374system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses 375system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses 376system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses 377system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses 378system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses 379system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses 380system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses 381system.cpu.dcache.overall_misses::total 9112677 # number of overall misses 382system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles 383system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles 384system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles 385system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles 386system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles 387system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles 388system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles 389system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles 390system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) 391system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) 393system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses 395system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses 396system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses 397system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses 398system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses 399system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses 400system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses 401system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses 402system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses 403system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses 404system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses 405system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses 406system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency 407system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency 408system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency 410system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency 411system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency 412system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 420system.cpu.dcache.fast_writes 0 # number of fast writes performed 421system.cpu.dcache.cache_copies 0 # number of cache copies performed 422system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks 423system.cpu.dcache.writebacks::total 3697956 # number of writebacks 424system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses 425system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses 426system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses 427system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses 428system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses 429system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses 430system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses 431system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses 432system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles 433system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles 434system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles 435system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles 436system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles 437system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles 438system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles 439system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles 440system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses 441system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses 442system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses 443system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses 444system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses 445system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses 446system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses 447system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses 448system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency 449system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency 450system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency 451system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency 452system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 453system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 454system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency 455system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency 456system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 457system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s) 458system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution 459system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution 460system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution 463system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1350 # Packet count per connected master and slave (bytes) 464system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21923310 # Packet count per connected master and slave (bytes) 465system.cpu.toL2Bus.pkt_count::total 21924660 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) 467system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819880512 # Cumulative packet size per connected master and slave (bytes) 468system.cpu.toL2Bus.tot_pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes) 469system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes) 470system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 471system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) 472system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 473system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) 474system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 475system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) 476system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 477 478---------- End Simulation Statistics ---------- 479