stats.txt revision 9729:e2fafd224f43
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.391205 # Number of seconds simulated 4sim_ticks 2391205115000 # Number of ticks simulated 5final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1401168 # Simulator instruction rate (inst/s) 8host_op_rate 1563717 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2177389973 # Simulator tick rate (ticks/s) 10host_mem_usage 243008 # Number of bytes of host memory used 11host_seconds 1098.20 # Real time elapsed on the host 12sim_insts 1538759601 # Number of instructions simulated 13sim_ops 1717270334 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory 16system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory 20system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) 37system.membus.throughput 79651138 # Throughput (bytes/s) 38system.membus.trans_dist::ReadReq 1177898 # Transaction distribution 39system.membus.trans_dist::ReadResp 1177898 # Transaction distribution 40system.membus.trans_dist::Writeback 1017198 # Transaction distribution 41system.membus.trans_dist::ReadExReq 780876 # Transaction distribution 42system.membus.trans_dist::ReadExResp 780876 # Transaction distribution 43system.membus.pkt_count_system.cpu.l2cache.mem_side 4934746 # Packet count per connected master and slave (bytes) 44system.membus.pkt_count 4934746 # Packet count per connected master and slave (bytes) 45system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190462208 # Cumulative packet size per connected master and slave (bytes) 46system.membus.tot_pkt_size 190462208 # Cumulative packet size per connected master and slave (bytes) 47system.membus.data_through_bus 190462208 # Total data (bytes) 48system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 49system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) 50system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 51system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) 52system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 53system.cpu.dtb.inst_hits 0 # ITB inst hits 54system.cpu.dtb.inst_misses 0 # ITB inst misses 55system.cpu.dtb.read_hits 0 # DTB read hits 56system.cpu.dtb.read_misses 0 # DTB read misses 57system.cpu.dtb.write_hits 0 # DTB write hits 58system.cpu.dtb.write_misses 0 # DTB write misses 59system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 60system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 61system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 62system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 63system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 64system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 65system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 66system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 67system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 68system.cpu.dtb.read_accesses 0 # DTB read accesses 69system.cpu.dtb.write_accesses 0 # DTB write accesses 70system.cpu.dtb.inst_accesses 0 # ITB inst accesses 71system.cpu.dtb.hits 0 # DTB hits 72system.cpu.dtb.misses 0 # DTB misses 73system.cpu.dtb.accesses 0 # DTB accesses 74system.cpu.itb.inst_hits 0 # ITB inst hits 75system.cpu.itb.inst_misses 0 # ITB inst misses 76system.cpu.itb.read_hits 0 # DTB read hits 77system.cpu.itb.read_misses 0 # DTB read misses 78system.cpu.itb.write_hits 0 # DTB write hits 79system.cpu.itb.write_misses 0 # DTB write misses 80system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 81system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 82system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 83system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 84system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 85system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 86system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 87system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.itb.read_accesses 0 # DTB read accesses 90system.cpu.itb.write_accesses 0 # DTB write accesses 91system.cpu.itb.inst_accesses 0 # ITB inst accesses 92system.cpu.itb.hits 0 # DTB hits 93system.cpu.itb.misses 0 # DTB misses 94system.cpu.itb.accesses 0 # DTB accesses 95system.cpu.workload.num_syscalls 46 # Number of system calls 96system.cpu.numCycles 4782410230 # number of cpu cycles simulated 97system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 98system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 99system.cpu.committedInsts 1538759601 # Number of instructions committed 100system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed 101system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses 102system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 103system.cpu.num_func_calls 27330256 # number of times a function call or return occured 104system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls 105system.cpu.num_int_insts 1536941842 # number of integer instructions 106system.cpu.num_fp_insts 36 # number of float instructions 107system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read 108system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written 109system.cpu.num_fp_register_reads 24 # number of times the floating registers were read 110system.cpu.num_fp_register_writes 16 # number of times the floating registers were written 111system.cpu.num_mem_refs 660773815 # number of memory refs 112system.cpu.num_load_insts 485926769 # Number of load instructions 113system.cpu.num_store_insts 174847046 # Number of store instructions 114system.cpu.num_idle_cycles 0 # Number of idle cycles 115system.cpu.num_busy_cycles 4782410230 # Number of busy cycles 116system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 117system.cpu.idle_fraction 0 # Percentage of idle cycles 118system.cpu.icache.replacements 7 # number of replacements 119system.cpu.icache.tagsinuse 514.976015 # Cycle average of tags in use 120system.cpu.icache.total_refs 1544564952 # Total number of references to valid blocks. 121system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. 122system.cpu.icache.avg_refs 2420948.200627 # Average number of references to valid blocks. 123system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 124system.cpu.icache.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor 125system.cpu.icache.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy 126system.cpu.icache.occ_percent::total 0.251453 # Average percentage of cache occupancy 127system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits 128system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits 129system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits 130system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits 131system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits 132system.cpu.icache.overall_hits::total 1544564952 # number of overall hits 133system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses 134system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses 135system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses 136system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses 137system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses 138system.cpu.icache.overall_misses::total 638 # number of overall misses 139system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles 140system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles 141system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles 142system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles 143system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles 144system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles 145system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) 146system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) 147system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses 148system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses 149system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses 150system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses 151system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 152system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 153system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 154system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 155system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 156system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 157system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency 158system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency 159system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency 160system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency 161system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency 162system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency 163system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 164system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 165system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 166system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 167system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 168system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 169system.cpu.icache.fast_writes 0 # number of fast writes performed 170system.cpu.icache.cache_copies 0 # number of cache copies performed 171system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 172system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 173system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 174system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 175system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 176system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses 177system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles 178system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles 179system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles 180system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles 181system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles 182system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles 183system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 184system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 185system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 186system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 187system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 188system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 189system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency 190system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency 191system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency 192system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency 193system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency 194system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency 195system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 196system.cpu.l2cache.replacements 1926075 # number of replacements 197system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use 198system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks. 199system.cpu.l2cache.sampled_refs 1955843 # Sample count of references to valid blocks. 200system.cpu.l2cache.avg_refs 4.585016 # Average number of references to valid blocks. 201system.cpu.l2cache.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. 202system.cpu.l2cache.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor 203system.cpu.l2cache.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor 204system.cpu.l2cache.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor 205system.cpu.l2cache.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy 206system.cpu.l2cache.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy 207system.cpu.l2cache.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy 208system.cpu.l2cache.occ_percent::total 0.945651 # Average percentage of cache occupancy 209system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits 210system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits 211system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits 212system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits 213system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits 214system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits 215system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits 216system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 217system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits 218system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits 219system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 220system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits 221system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits 222system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses 223system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses 224system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses 225system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses 226system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses 227system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses 228system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses 229system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses 230system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses 231system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses 232system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses 233system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles 234system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles 235system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles 236system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles 237system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles 238system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles 239system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles 240system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles 241system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles 242system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles 243system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles 244system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) 245system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) 246system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) 247system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses) 248system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses) 249system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) 250system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) 251system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses 252system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses 253system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses 254system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses 255system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses 256system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses 257system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses 258system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses 259system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses 260system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses 261system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses 262system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses 263system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses 264system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses 265system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses 266system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses 267system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses 268system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency 269system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency 270system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency 271system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency 272system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency 273system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency 274system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency 275system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency 276system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency 277system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency 278system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency 279system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 280system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 281system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 282system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 283system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 284system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 285system.cpu.l2cache.fast_writes 0 # number of fast writes performed 286system.cpu.l2cache.cache_copies 0 # number of cache copies performed 287system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks 288system.cpu.l2cache.writebacks::total 1017198 # number of writebacks 289system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses 290system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses 291system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses 292system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses 293system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses 294system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses 295system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses 296system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses 297system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses 298system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses 299system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses 300system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles 301system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles 302system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles 303system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles 304system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles 305system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles 306system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles 307system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles 308system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles 309system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles 310system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles 311system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses 312system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses 313system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses 314system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses 315system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses 316system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses 317system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses 318system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses 319system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses 320system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses 321system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses 322system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency 323system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency 324system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency 325system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency 326system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency 327system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency 328system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency 329system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency 330system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency 331system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency 332system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency 333system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 334system.cpu.dcache.replacements 9111140 # number of replacements 335system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use 336system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks. 337system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. 338system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. 339system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. 340system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor 341system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy 342system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy 343system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits 344system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits 345system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits 346system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits 347system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 348system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 349system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 350system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 351system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits 352system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits 353system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits 354system.cpu.dcache.overall_hits::total 645854937 # number of overall hits 355system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses 356system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses 357system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses 358system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses 359system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses 360system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses 361system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses 362system.cpu.dcache.overall_misses::total 9115236 # number of overall misses 363system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles 364system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles 365system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles 366system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles 367system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles 368system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles 369system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles 370system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles 371system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) 372system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) 373system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 374system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 375system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 376system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 377system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 378system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 379system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses 380system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses 381system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses 382system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses 383system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses 384system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses 385system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses 386system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses 387system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses 388system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses 389system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses 390system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses 391system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency 392system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency 393system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency 394system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency 395system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency 396system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency 397system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency 398system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency 399system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 400system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 401system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 402system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 403system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 404system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 405system.cpu.dcache.fast_writes 0 # number of fast writes performed 406system.cpu.dcache.cache_copies 0 # number of cache copies performed 407system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks 408system.cpu.dcache.writebacks::total 3697418 # number of writebacks 409system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses 410system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses 411system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 412system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses 413system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses 414system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses 415system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses 416system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses 417system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles 418system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles 419system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles 420system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles 421system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles 422system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles 423system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles 424system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles 425system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses 426system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses 427system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses 428system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses 429system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses 430system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses 431system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses 432system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses 433system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency 434system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency 435system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency 436system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency 437system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency 438system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency 439system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency 440system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency 441system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s) 443system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution 447system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution 448system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1276 # Packet count per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21927890 # Packet count per connected master and slave (bytes) 450system.cpu.toL2Bus.pkt_count 21929166 # Packet count per connected master and slave (bytes) 451system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40832 # Cumulative packet size per connected master and slave (bytes) 452system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 820009856 # Cumulative packet size per connected master and slave (bytes) 453system.cpu.toL2Bus.tot_pkt_size 820050688 # Cumulative packet size per connected master and slave (bytes) 454system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) 455system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 456system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) 457system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 458system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) 459system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 460system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) 461system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 462 463---------- End Simulation Statistics ---------- 464