stats.txt revision 9055:38f1926fb599
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.431420 # Number of seconds simulated 4sim_ticks 2431419954000 # Number of ticks simulated 5final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1031283 # Simulator instruction rate (inst/s) 8host_op_rate 1150922 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1629547552 # Simulator tick rate (ticks/s) 10host_mem_usage 230584 # Number of bytes of host memory used 11host_seconds 1492.08 # Real time elapsed on the host 12sim_insts 1538759609 # Number of instructions simulated 13sim_ops 1717270343 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 172726592 # Number of bytes read from this memory 16system.physmem.bytes_read::total 172766016 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 75006720 # Number of bytes written to this memory 20system.physmem.bytes_written::total 75006720 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2698853 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2699469 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1171980 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1171980 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 16214 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 71039391 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 71055605 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 16214 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 16214 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 30848937 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 30848937 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 30848937 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 16214 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 71039391 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 101904542 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 46system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 48system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 49system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 50system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 51system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52system.cpu.dtb.read_accesses 0 # DTB read accesses 53system.cpu.dtb.write_accesses 0 # DTB write accesses 54system.cpu.dtb.inst_accesses 0 # ITB inst accesses 55system.cpu.dtb.hits 0 # DTB hits 56system.cpu.dtb.misses 0 # DTB misses 57system.cpu.dtb.accesses 0 # DTB accesses 58system.cpu.itb.inst_hits 0 # ITB inst hits 59system.cpu.itb.inst_misses 0 # ITB inst misses 60system.cpu.itb.read_hits 0 # DTB read hits 61system.cpu.itb.read_misses 0 # DTB read misses 62system.cpu.itb.write_hits 0 # DTB write hits 63system.cpu.itb.write_misses 0 # DTB write misses 64system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 65system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 66system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 67system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 69system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 70system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 71system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 46 # Number of system calls 80system.cpu.numCycles 4862839908 # number of cpu cycles simulated 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 83system.cpu.committedInsts 1538759609 # Number of instructions committed 84system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed 85system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses 86system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 87system.cpu.num_func_calls 27330134 # number of times a function call or return occured 88system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls 89system.cpu.num_int_insts 1536941850 # number of integer instructions 90system.cpu.num_fp_insts 36 # number of float instructions 91system.cpu.num_int_register_reads 9304894713 # number of times the integer registers were read 92system.cpu.num_int_register_writes 1675132418 # number of times the integer registers were written 93system.cpu.num_fp_register_reads 24 # number of times the floating registers were read 94system.cpu.num_fp_register_writes 16 # number of times the floating registers were written 95system.cpu.num_mem_refs 660773816 # number of memory refs 96system.cpu.num_load_insts 485926770 # Number of load instructions 97system.cpu.num_store_insts 174847046 # Number of store instructions 98system.cpu.num_idle_cycles 0 # Number of idle cycles 99system.cpu.num_busy_cycles 4862839908 # Number of busy cycles 100system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 101system.cpu.idle_fraction 0 # Percentage of idle cycles 102system.cpu.icache.replacements 7 # number of replacements 103system.cpu.icache.tagsinuse 514.872896 # Cycle average of tags in use 104system.cpu.icache.total_refs 1544564961 # Total number of references to valid blocks. 105system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks. 106system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks. 107system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 108system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor 109system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy 110system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy 111system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits 112system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits 113system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits 114system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits 115system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits 116system.cpu.icache.overall_hits::total 1544564961 # number of overall hits 117system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses 118system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses 119system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses 120system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses 121system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses 122system.cpu.icache.overall_misses::total 638 # number of overall misses 123system.cpu.icache.ReadReq_miss_latency::cpu.inst 34804000 # number of ReadReq miss cycles 124system.cpu.icache.ReadReq_miss_latency::total 34804000 # number of ReadReq miss cycles 125system.cpu.icache.demand_miss_latency::cpu.inst 34804000 # number of demand (read+write) miss cycles 126system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles 127system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles 128system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles 129system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses) 130system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses) 131system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses 132system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses 133system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses 134system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses 135system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 136system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 137system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 138system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 139system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 140system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 141system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency 142system.cpu.icache.ReadReq_avg_miss_latency::total 54551.724138 # average ReadReq miss latency 143system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency 144system.cpu.icache.demand_avg_miss_latency::total 54551.724138 # average overall miss latency 145system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency 146system.cpu.icache.overall_avg_miss_latency::total 54551.724138 # average overall miss latency 147system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 148system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 149system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 150system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 151system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 152system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 153system.cpu.icache.fast_writes 0 # number of fast writes performed 154system.cpu.icache.cache_copies 0 # number of cache copies performed 155system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 156system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 157system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 158system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 159system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 160system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses 161system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32890000 # number of ReadReq MSHR miss cycles 162system.cpu.icache.ReadReq_mshr_miss_latency::total 32890000 # number of ReadReq MSHR miss cycles 163system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32890000 # number of demand (read+write) MSHR miss cycles 164system.cpu.icache.demand_mshr_miss_latency::total 32890000 # number of demand (read+write) MSHR miss cycles 165system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles 166system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles 167system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 168system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 169system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 170system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 171system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 172system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 173system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency 174system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51551.724138 # average ReadReq mshr miss latency 175system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency 176system.cpu.icache.demand_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency 177system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency 178system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138 # average overall mshr miss latency 179system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 180system.cpu.dcache.replacements 9111140 # number of replacements 181system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use 182system.cpu.dcache.total_refs 645855060 # Total number of references to valid blocks. 183system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks. 184system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks. 185system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit. 186system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor 187system.cpu.dcache.occ_percent::cpu.data 0.997002 # Average percentage of cache occupancy 188system.cpu.dcache.occ_percent::total 0.997002 # Average percentage of cache occupancy 189system.cpu.dcache.ReadReq_hits::cpu.data 475158040 # number of ReadReq hits 190system.cpu.dcache.ReadReq_hits::total 475158040 # number of ReadReq hits 191system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits 192system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits 193system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 194system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 195system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 196system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 197system.cpu.dcache.demand_hits::cpu.data 645854938 # number of demand (read+write) hits 198system.cpu.dcache.demand_hits::total 645854938 # number of demand (read+write) hits 199system.cpu.dcache.overall_hits::cpu.data 645854938 # number of overall hits 200system.cpu.dcache.overall_hits::total 645854938 # number of overall hits 201system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses 202system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses 203system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses 204system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses 205system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses 206system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses 207system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses 208system.cpu.dcache.overall_misses::total 9115236 # number of overall misses 209system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000 # number of ReadReq miss cycles 210system.cpu.dcache.ReadReq_miss_latency::total 177140908000 # number of ReadReq miss cycles 211system.cpu.dcache.WriteReq_miss_latency::cpu.data 63824222000 # number of WriteReq miss cycles 212system.cpu.dcache.WriteReq_miss_latency::total 63824222000 # number of WriteReq miss cycles 213system.cpu.dcache.demand_miss_latency::cpu.data 240965130000 # number of demand (read+write) miss cycles 214system.cpu.dcache.demand_miss_latency::total 240965130000 # number of demand (read+write) miss cycles 215system.cpu.dcache.overall_miss_latency::cpu.data 240965130000 # number of overall miss cycles 216system.cpu.dcache.overall_miss_latency::total 240965130000 # number of overall miss cycles 217system.cpu.dcache.ReadReq_accesses::cpu.data 482384127 # number of ReadReq accesses(hits+misses) 218system.cpu.dcache.ReadReq_accesses::total 482384127 # number of ReadReq accesses(hits+misses) 219system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 220system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 221system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 222system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 223system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 224system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 225system.cpu.dcache.demand_accesses::cpu.data 654970174 # number of demand (read+write) accesses 226system.cpu.dcache.demand_accesses::total 654970174 # number of demand (read+write) accesses 227system.cpu.dcache.overall_accesses::cpu.data 654970174 # number of overall (read+write) accesses 228system.cpu.dcache.overall_accesses::total 654970174 # number of overall (read+write) accesses 229system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses 230system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses 231system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses 232system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses 233system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses 234system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses 235system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses 236system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses 237system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594 # average ReadReq miss latency 238system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594 # average ReadReq miss latency 239system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656 # average WriteReq miss latency 240system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656 # average WriteReq miss latency 241system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency 242system.cpu.dcache.demand_avg_miss_latency::total 26435.424162 # average overall miss latency 243system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162 # average overall miss latency 244system.cpu.dcache.overall_avg_miss_latency::total 26435.424162 # average overall miss latency 245system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 246system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 248system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 249system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 250system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 251system.cpu.dcache.fast_writes 0 # number of fast writes performed 252system.cpu.dcache.cache_copies 0 # number of cache copies performed 253system.cpu.dcache.writebacks::writebacks 3061985 # number of writebacks 254system.cpu.dcache.writebacks::total 3061985 # number of writebacks 255system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses 256system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses 257system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 258system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses 259system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses 260system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses 261system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses 262system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses 263system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155462647000 # number of ReadReq MSHR miss cycles 264system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000 # number of ReadReq MSHR miss cycles 265system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58156775000 # number of WriteReq MSHR miss cycles 266system.cpu.dcache.WriteReq_mshr_miss_latency::total 58156775000 # number of WriteReq MSHR miss cycles 267system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213619422000 # number of demand (read+write) MSHR miss cycles 268system.cpu.dcache.demand_mshr_miss_latency::total 213619422000 # number of demand (read+write) MSHR miss cycles 269system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000 # number of overall MSHR miss cycles 270system.cpu.dcache.overall_mshr_miss_latency::total 213619422000 # number of overall MSHR miss cycles 271system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses 272system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses 273system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses 274system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses 275system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses 276system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses 277system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses 278system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses 279system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594 # average ReadReq mshr miss latency 280system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21514.084594 # average ReadReq mshr miss latency 281system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656 # average WriteReq mshr miss latency 282system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30784.641656 # average WriteReq mshr miss latency 283system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency 284system.cpu.dcache.demand_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency 285system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162 # average overall mshr miss latency 286system.cpu.dcache.overall_avg_mshr_miss_latency::total 23435.424162 # average overall mshr miss latency 287system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 288system.cpu.l2cache.replacements 2687066 # number of replacements 289system.cpu.l2cache.tagsinuse 26134.517233 # Cycle average of tags in use 290system.cpu.l2cache.total_refs 7569171 # Total number of references to valid blocks. 291system.cpu.l2cache.sampled_refs 2714383 # Sample count of references to valid blocks. 292system.cpu.l2cache.avg_refs 2.788542 # Average number of references to valid blocks. 293system.cpu.l2cache.warmup_cycle 538044123000 # Cycle when the warmup percentage was hit. 294system.cpu.l2cache.occ_blocks::writebacks 11106.896016 # Average occupied blocks per requestor 295system.cpu.l2cache.occ_blocks::cpu.inst 11.181020 # Average occupied blocks per requestor 296system.cpu.l2cache.occ_blocks::cpu.data 15016.440197 # Average occupied blocks per requestor 297system.cpu.l2cache.occ_percent::writebacks 0.338956 # Average percentage of cache occupancy 298system.cpu.l2cache.occ_percent::cpu.inst 0.000341 # Average percentage of cache occupancy 299system.cpu.l2cache.occ_percent::cpu.data 0.458265 # Average percentage of cache occupancy 300system.cpu.l2cache.occ_percent::total 0.797562 # Average percentage of cache occupancy 301system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits 302system.cpu.l2cache.ReadReq_hits::cpu.data 5417142 # number of ReadReq hits 303system.cpu.l2cache.ReadReq_hits::total 5417164 # number of ReadReq hits 304system.cpu.l2cache.Writeback_hits::writebacks 3061985 # number of Writeback hits 305system.cpu.l2cache.Writeback_hits::total 3061985 # number of Writeback hits 306system.cpu.l2cache.ReadExReq_hits::cpu.data 999241 # number of ReadExReq hits 307system.cpu.l2cache.ReadExReq_hits::total 999241 # number of ReadExReq hits 308system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 309system.cpu.l2cache.demand_hits::cpu.data 6416383 # number of demand (read+write) hits 310system.cpu.l2cache.demand_hits::total 6416405 # number of demand (read+write) hits 311system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 312system.cpu.l2cache.overall_hits::cpu.data 6416383 # number of overall hits 313system.cpu.l2cache.overall_hits::total 6416405 # number of overall hits 314system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses 315system.cpu.l2cache.ReadReq_misses::cpu.data 1808945 # number of ReadReq misses 316system.cpu.l2cache.ReadReq_misses::total 1809561 # number of ReadReq misses 317system.cpu.l2cache.ReadExReq_misses::cpu.data 889908 # number of ReadExReq misses 318system.cpu.l2cache.ReadExReq_misses::total 889908 # number of ReadExReq misses 319system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses 320system.cpu.l2cache.demand_misses::cpu.data 2698853 # number of demand (read+write) misses 321system.cpu.l2cache.demand_misses::total 2699469 # number of demand (read+write) misses 322system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses 323system.cpu.l2cache.overall_misses::cpu.data 2698853 # number of overall misses 324system.cpu.l2cache.overall_misses::total 2699469 # number of overall misses 325system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles 326system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94065140000 # number of ReadReq miss cycles 327system.cpu.l2cache.ReadReq_miss_latency::total 94097172000 # number of ReadReq miss cycles 328system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46275216000 # number of ReadExReq miss cycles 329system.cpu.l2cache.ReadExReq_miss_latency::total 46275216000 # number of ReadExReq miss cycles 330system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles 331system.cpu.l2cache.demand_miss_latency::cpu.data 140340356000 # number of demand (read+write) miss cycles 332system.cpu.l2cache.demand_miss_latency::total 140372388000 # number of demand (read+write) miss cycles 333system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles 334system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000 # number of overall miss cycles 335system.cpu.l2cache.overall_miss_latency::total 140372388000 # number of overall miss cycles 336system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) 337system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) 338system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) 339system.cpu.l2cache.Writeback_accesses::writebacks 3061985 # number of Writeback accesses(hits+misses) 340system.cpu.l2cache.Writeback_accesses::total 3061985 # number of Writeback accesses(hits+misses) 341system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) 342system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) 343system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses 344system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses 345system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses 346system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses 347system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses 348system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses 349system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses 350system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250335 # miss rate for ReadReq accesses 351system.cpu.l2cache.ReadReq_miss_rate::total 0.250398 # miss rate for ReadReq accesses 352system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471063 # miss rate for ReadExReq accesses 353system.cpu.l2cache.ReadExReq_miss_rate::total 0.471063 # miss rate for ReadExReq accesses 354system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses 355system.cpu.l2cache.demand_miss_rate::cpu.data 0.296082 # miss rate for demand accesses 356system.cpu.l2cache.demand_miss_rate::total 0.296128 # miss rate for demand accesses 357system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses 358system.cpu.l2cache.overall_miss_rate::cpu.data 0.296082 # miss rate for overall accesses 359system.cpu.l2cache.overall_miss_rate::total 0.296128 # miss rate for overall accesses 360system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 361system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 362system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 363system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 364system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 365system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 366system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 367system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 368system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 369system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 370system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 371system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 375system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 376system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 377system.cpu.l2cache.fast_writes 0 # number of fast writes performed 378system.cpu.l2cache.cache_copies 0 # number of cache copies performed 379system.cpu.l2cache.writebacks::writebacks 1171980 # number of writebacks 380system.cpu.l2cache.writebacks::total 1171980 # number of writebacks 381system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses 382system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1808945 # number of ReadReq MSHR misses 383system.cpu.l2cache.ReadReq_mshr_misses::total 1809561 # number of ReadReq MSHR misses 384system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889908 # number of ReadExReq MSHR misses 385system.cpu.l2cache.ReadExReq_mshr_misses::total 889908 # number of ReadExReq MSHR misses 386system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses 387system.cpu.l2cache.demand_mshr_misses::cpu.data 2698853 # number of demand (read+write) MSHR misses 388system.cpu.l2cache.demand_mshr_misses::total 2699469 # number of demand (read+write) MSHR misses 389system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses 390system.cpu.l2cache.overall_mshr_misses::cpu.data 2698853 # number of overall MSHR misses 391system.cpu.l2cache.overall_mshr_misses::total 2699469 # number of overall MSHR misses 392system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles 393system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72357800000 # number of ReadReq MSHR miss cycles 394system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72382440000 # number of ReadReq MSHR miss cycles 395system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35596320000 # number of ReadExReq MSHR miss cycles 396system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35596320000 # number of ReadExReq MSHR miss cycles 397system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles 398system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000 # number of demand (read+write) MSHR miss cycles 399system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000 # number of demand (read+write) MSHR miss cycles 400system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles 401system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 # number of overall MSHR miss cycles 402system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles 403system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses 404system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses 405system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.250398 # mshr miss rate for ReadReq accesses 406system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses 407system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471063 # mshr miss rate for ReadExReq accesses 408system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses 409system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses 410system.cpu.l2cache.demand_mshr_miss_rate::total 0.296128 # mshr miss rate for demand accesses 411system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses 412system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses 413system.cpu.l2cache.overall_mshr_miss_rate::total 0.296128 # mshr miss rate for overall accesses 414system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 415system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 416system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 417system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 418system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 419system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 420system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 421system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 422system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 423system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 424system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 425system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 426 427---------- End Simulation Statistics ---------- 428