stats.txt revision 10628:c9b7e0c69f88
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.363671 # Number of seconds simulated 4sim_ticks 2363670998000 # Number of ticks simulated 5final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1113267 # Simulator instruction rate (inst/s) 8host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1710076181 # Simulator tick rate (ticks/s) 10host_mem_usage 309628 # Number of bytes of host memory used 11host_seconds 1382.20 # Real time elapsed on the host 12sim_insts 1538759601 # Number of instructions simulated 13sim_ops 1658228914 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory 18system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.inst_hits 0 # ITB inst hits 136system.cpu.itb.inst_misses 0 # ITB inst misses 137system.cpu.itb.read_hits 0 # DTB read hits 138system.cpu.itb.read_misses 0 # DTB read misses 139system.cpu.itb.write_hits 0 # DTB write hits 140system.cpu.itb.write_misses 0 # DTB write misses 141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 146system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 147system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 148system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 46 # Number of system calls 157system.cpu.numCycles 4727341996 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 1538759601 # Number of instructions committed 161system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 164system.cpu.num_func_calls 27330256 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls 166system.cpu.num_int_insts 1477900422 # number of integer instructions 167system.cpu.num_fp_insts 36 # number of float instructions 168system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read 169system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 24 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 16 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written 174system.cpu.num_mem_refs 633153380 # number of memory refs 175system.cpu.num_load_insts 458306334 # Number of load instructions 176system.cpu.num_store_insts 174847046 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 178system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 213462426 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction 184system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction 192system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction 193system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction 194system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction 195system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction 196system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction 197system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction 198system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction 199system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction 200system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction 201system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction 202system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction 203system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction 204system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction 205system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction 206system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction 207system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction 208system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction 212system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction 213system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 1664032480 # Class of executed instruction 217system.cpu.dcache.tags.replacements 9111140 # number of replacements 218system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use 219system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. 220system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. 221system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. 222system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. 223system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor 224system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy 225system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 227system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses 235system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits 236system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits 237system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits 238system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits 239system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 240system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 241system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 242system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 243system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits 244system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits 245system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits 246system.cpu.dcache.overall_hits::total 618379947 # number of overall hits 247system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses 248system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses 249system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses 250system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses 251system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 252system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 253system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses 254system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses 255system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses 256system.cpu.dcache.overall_misses::total 9115236 # number of overall misses 257system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles 258system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles 259system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles 260system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles 261system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles 262system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles 263system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles 264system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles 265system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) 266system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) 267system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 268system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 269system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) 270system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) 271system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 272system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 273system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 274system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 275system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses 276system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses 277system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses 278system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses 279system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses 280system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses 281system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses 282system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses 283system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 284system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 285system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses 286system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses 287system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses 288system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses 289system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency 290system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency 291system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency 292system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency 293system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency 294system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency 295system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency 296system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 303system.cpu.dcache.fast_writes 0 # number of fast writes performed 304system.cpu.dcache.cache_copies 0 # number of cache copies performed 305system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks 306system.cpu.dcache.writebacks::total 3697418 # number of writebacks 307system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses 308system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses 309system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 310system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses 311system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 312system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 313system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses 314system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses 315system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses 316system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses 317system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles 318system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles 319system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles 320system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles 321system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles 322system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles 323system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles 324system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles 325system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles 326system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles 327system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses 328system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses 329system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses 330system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses 331system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses 332system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses 333system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses 334system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses 335system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses 336system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses 337system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency 338system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency 339system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency 340system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency 341system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency 342system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency 343system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency 344system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency 345system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency 346system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency 347system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 348system.cpu.icache.tags.replacements 7 # number of replacements 349system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use 350system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. 351system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. 352system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. 353system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor 355system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy 356system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy 357system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id 361system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id 362system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses 363system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses 364system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits 365system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits 366system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits 367system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits 368system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits 369system.cpu.icache.overall_hits::total 1544564952 # number of overall hits 370system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses 371system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses 372system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses 373system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses 374system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses 375system.cpu.icache.overall_misses::total 638 # number of overall misses 376system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles 377system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles 378system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles 379system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles 380system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles 381system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles 382system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) 383system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) 384system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses 385system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses 386system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses 387system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses 388system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 389system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 390system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 391system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 392system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 393system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 394system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency 395system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency 396system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency 397system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency 398system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency 399system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency 400system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 401system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 402system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 403system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 404system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 405system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 406system.cpu.icache.fast_writes 0 # number of fast writes performed 407system.cpu.icache.cache_copies 0 # number of cache copies performed 408system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 409system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 410system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 411system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 412system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 413system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses 414system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles 419system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles 420system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 421system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 422system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 423system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 424system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 425system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency 427system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency 429system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency 431system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency 432system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 433system.cpu.l2cache.tags.replacements 1926075 # number of replacements 434system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use 435system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. 436system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. 437system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. 438system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit. 439system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor 440system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor 441system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor 442system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy 443system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy 444system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy 445system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy 446system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id 447system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 448system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 449system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id 450system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id 452system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id 453system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses 454system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses 455system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits 456system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits 457system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits 458system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits 459system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits 460system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits 461system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits 462system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 463system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits 464system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits 465system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 466system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits 467system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits 468system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses 469system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses 470system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses 471system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses 472system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses 473system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses 474system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses 475system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses 476system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses 477system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses 478system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses 479system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles 480system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles 481system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles 482system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles 483system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles 484system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles 485system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles 486system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles 487system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles 488system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles 489system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles 490system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) 491system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) 492system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) 493system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses) 494system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses) 495system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) 496system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) 497system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses 498system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses 499system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses 500system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses 501system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses 502system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses 503system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses 504system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses 505system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses 506system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses 507system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses 508system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses 509system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses 510system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses 511system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses 512system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses 513system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses 514system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency 515system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency 516system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency 517system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency 518system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency 519system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency 520system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency 521system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency 522system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency 523system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency 524system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency 525system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 526system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 527system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 528system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 529system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 530system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 531system.cpu.l2cache.fast_writes 0 # number of fast writes performed 532system.cpu.l2cache.cache_copies 0 # number of cache copies performed 533system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks 534system.cpu.l2cache.writebacks::total 1017198 # number of writebacks 535system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses 536system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses 537system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses 538system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses 539system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses 540system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses 541system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses 542system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses 543system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses 544system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses 545system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses 546system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles 547system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles 548system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles 549system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles 550system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles 551system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles 552system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles 553system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles 554system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles 555system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles 556system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles 557system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses 558system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses 559system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses 560system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses 561system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses 562system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses 563system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses 564system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses 565system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses 566system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses 567system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses 568system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency 569system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency 570system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency 571system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency 572system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency 573system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency 574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency 575system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency 576system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency 577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency 578system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency 579system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 580system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution 581system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 582system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution 583system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution 584system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution 585system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) 586system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) 587system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes) 588system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) 589system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) 590system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) 591system.cpu.toL2Bus.snoops 0 # Total snoops (count) 592system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram 593system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 594system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 595system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 596system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 599system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 600system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram 602system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram 607system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) 608system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 609system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) 610system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 611system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) 612system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 613system.membus.trans_dist::ReadReq 1177898 # Transaction distribution 614system.membus.trans_dist::ReadResp 1177898 # Transaction distribution 615system.membus.trans_dist::Writeback 1017198 # Transaction distribution 616system.membus.trans_dist::ReadExReq 780876 # Transaction distribution 617system.membus.trans_dist::ReadExResp 780876 # Transaction distribution 618system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) 619system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) 620system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) 621system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) 622system.membus.snoops 0 # Total snoops (count) 623system.membus.snoop_fanout::samples 2975972 # Request fanout histogram 624system.membus.snoop_fanout::mean 0 # Request fanout histogram 625system.membus.snoop_fanout::stdev 0 # Request fanout histogram 626system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 627system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram 628system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 629system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 630system.membus.snoop_fanout::min_value 0 # Request fanout histogram 631system.membus.snoop_fanout::max_value 0 # Request fanout histogram 632system.membus.snoop_fanout::total 2975972 # Request fanout histogram 633system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) 634system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 635system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) 636system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 637 638---------- End Simulation Statistics ---------- 639