stats.txt revision 9924:31ef410b6843
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.541686 # Number of seconds simulated 4sim_ticks 541686426500 # Number of ticks simulated 5final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 133850 # Simulator instruction rate (inst/s) 8host_op_rate 149320 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46941984 # Simulator tick rate (ticks/s) 10host_mem_usage 248124 # Number of bytes of host memory used 11host_seconds 11539.49 # Real time elapsed on the host 12sim_insts 1544563023 # Number of instructions simulated 13sim_ops 1723073835 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 143725568 # Number of bytes read from this memory 16system.physmem.bytes_read::total 143773696 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 70430528 # Number of bytes written to this memory 20system.physmem.bytes_written::total 70430528 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2245712 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2246464 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1100477 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1100477 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 88848 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 265329831 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 265418679 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 88848 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 88848 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 130020847 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 130020847 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 130020847 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 88848 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 265329831 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 395439526 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 2246464 # Total number of read requests accepted by DRAM controller 38system.physmem.writeReqs 1100477 # Total number of write requests accepted by DRAM controller 39system.physmem.readBursts 2246464 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 40system.physmem.writeBursts 1100477 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 41system.physmem.bytesRead 143773696 # Total number of bytes read from memory 42system.physmem.bytesWritten 70430528 # Total number of bytes written to memory 43system.physmem.bytesConsumedRd 143773696 # bytesRead derated as per pkt->getSize() 44system.physmem.bytesConsumedWr 70430528 # bytesWritten derated as per pkt->getSize() 45system.physmem.servicedByWrQ 599 # Number of DRAM read bursts serviced by write Q 46system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 47system.physmem.perBankRdReqs::0 139699 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::1 136238 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::2 133756 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::3 136368 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::4 134718 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::5 135333 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::6 136160 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::7 136095 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::8 143598 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::9 146293 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::10 144461 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::11 146176 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::12 145883 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::13 146345 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::14 142220 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::15 142522 # Track reads on a per bank basis 63system.physmem.perBankWrReqs::0 69143 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::1 67428 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::2 65656 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::3 66333 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::4 66095 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::5 66425 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::6 67930 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::7 68755 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::8 70311 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::9 70943 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::10 70521 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::11 70921 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::12 70374 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::13 70896 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::14 69672 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::15 69074 # Track writes on a per bank basis 79system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 80system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry 81system.physmem.totGap 541686363500 # Total gap between requests 82system.physmem.readPktSize::0 0 # Categorize read packet sizes 83system.physmem.readPktSize::1 0 # Categorize read packet sizes 84system.physmem.readPktSize::2 0 # Categorize read packet sizes 85system.physmem.readPktSize::3 0 # Categorize read packet sizes 86system.physmem.readPktSize::4 0 # Categorize read packet sizes 87system.physmem.readPktSize::5 0 # Categorize read packet sizes 88system.physmem.readPktSize::6 2246464 # Categorize read packet sizes 89system.physmem.writePktSize::0 0 # Categorize write packet sizes 90system.physmem.writePktSize::1 0 # Categorize write packet sizes 91system.physmem.writePktSize::2 0 # Categorize write packet sizes 92system.physmem.writePktSize::3 0 # Categorize write packet sizes 93system.physmem.writePktSize::4 0 # Categorize write packet sizes 94system.physmem.writePktSize::5 0 # Categorize write packet sizes 95system.physmem.writePktSize::6 1100477 # Categorize write packet sizes 96system.physmem.rdQLenPdf::0 1615292 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 444627 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 139018 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 46909 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 128system.physmem.wrQLenPdf::0 45574 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::1 47478 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::2 47792 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::3 47823 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::5 47833 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::6 47833 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::7 47834 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 47834 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 47846 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 47846 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 47846 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 47846 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 2273 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 55 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 13 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see 160system.physmem.bytesPerActivate::samples 1997603 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::mean 107.193624 # Bytes accessed per row activation 162system.physmem.bytesPerActivate::gmean 79.812437 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::stdev 283.653287 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::64-65 1593724 79.78% 79.78% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::128-129 230021 11.51% 91.30% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::192-193 68328 3.42% 94.72% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::256-257 32466 1.63% 96.34% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::320-321 17759 0.89% 97.23% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::384-385 11013 0.55% 97.78% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::448-449 7534 0.38% 98.16% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::512-513 7551 0.38% 98.54% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::576-577 3933 0.20% 98.73% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::640-641 3162 0.16% 98.89% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::704-705 2715 0.14% 99.03% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::768-769 2783 0.14% 99.17% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::832-833 1408 0.07% 99.24% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::896-897 1190 0.06% 99.30% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::960-961 1060 0.05% 99.35% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1024-1025 829 0.04% 99.39% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1088-1089 802 0.04% 99.43% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1152-1153 757 0.04% 99.47% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1216-1217 590 0.03% 99.50% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1280-1281 531 0.03% 99.53% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1344-1345 601 0.03% 99.56% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1408-1409 798 0.04% 99.60% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1472-1473 3587 0.18% 99.78% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1536-1537 465 0.02% 99.80% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1600-1601 167 0.01% 99.81% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1664-1665 158 0.01% 99.82% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1728-1729 136 0.01% 99.82% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1792-1793 120 0.01% 99.83% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1856-1857 86 0.00% 99.83% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1920-1921 82 0.00% 99.84% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1984-1985 107 0.01% 99.84% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2048-2049 81 0.00% 99.85% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2112-2113 77 0.00% 99.85% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2176-2177 52 0.00% 99.85% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2240-2241 39 0.00% 99.86% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.86% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2368-2369 40 0.00% 99.86% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2432-2433 36 0.00% 99.86% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2496-2497 29 0.00% 99.86% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2560-2561 41 0.00% 99.86% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2624-2625 32 0.00% 99.87% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.87% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2752-2753 31 0.00% 99.87% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2816-2817 29 0.00% 99.87% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2880-2881 27 0.00% 99.87% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2944-2945 27 0.00% 99.87% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::3008-3009 30 0.00% 99.88% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::3072-3073 18 0.00% 99.88% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.88% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3264-3265 20 0.00% 99.88% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3328-3329 20 0.00% 99.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3392-3393 12 0.00% 99.88% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3456-3457 18 0.00% 99.88% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3520-3521 11 0.00% 99.88% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3584-3585 17 0.00% 99.88% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3648-3649 17 0.00% 99.88% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3712-3713 21 0.00% 99.89% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3776-3777 17 0.00% 99.89% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3840-3841 17 0.00% 99.89% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.89% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4032-4033 31 0.00% 99.89% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4096-4097 28 0.00% 99.89% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4160-4161 33 0.00% 99.89% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4224-4225 13 0.00% 99.89% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.89% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4352-4353 14 0.00% 99.90% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4416-4417 10 0.00% 99.90% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4480-4481 16 0.00% 99.90% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.90% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.90% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.90% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.90% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.90% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4864-4865 5 0.00% 99.90% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4928-4929 9 0.00% 99.90% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.90% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5120-5121 15 0.00% 99.90% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.90% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.90% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.90% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.90% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5440-5441 10 0.00% 99.90% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5504-5505 12 0.00% 99.91% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.91% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.91% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.91% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.91% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5888-5889 4 0.00% 99.91% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.91% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::6016-6017 7 0.00% 99.91% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::6080-6081 17 0.00% 99.91% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::6144-6145 9 0.00% 99.91% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.91% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6464-6465 4 0.00% 99.91% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6528-6529 11 0.00% 99.91% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.91% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6656-6657 10 0.00% 99.91% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.91% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6784-6785 9 0.00% 99.91% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.91% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6912-6913 9 0.00% 99.91% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6976-6977 5 0.00% 99.91% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::7040-7041 8 0.00% 99.91% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::7104-7105 15 0.00% 99.91% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.91% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7232-7233 14 0.00% 99.92% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.92% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.92% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7488-7489 7 0.00% 99.92% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7552-7553 7 0.00% 99.92% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7616-7617 5 0.00% 99.92% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7680-7681 122 0.01% 99.92% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7744-7745 15 0.00% 99.92% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7808-7809 8 0.00% 99.92% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7872-7873 6 0.00% 99.93% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.93% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8064-8065 8 0.00% 99.93% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8128-8129 20 0.00% 99.93% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8192-8193 1459 0.07% 100.00% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::total 1997603 # Bytes accessed per row activation 293system.physmem.totQLat 50283923250 # Total cycles spent in queuing delays 294system.physmem.totMemAccLat 124431529500 # Sum of mem lat for all requests 295system.physmem.totBusLat 11229325000 # Total cycles spent in databus access 296system.physmem.totBankLat 62918281250 # Total cycles spent in bank access 297system.physmem.avgQLat 22389.56 # Average queueing delay per request 298system.physmem.avgBankLat 28015.17 # Average bank access latency per request 299system.physmem.avgBusLat 5000.00 # Average bus latency per request 300system.physmem.avgMemAccLat 55404.72 # Average memory access latency 301system.physmem.avgRdBW 265.42 # Average achieved read bandwidth in MB/s 302system.physmem.avgWrBW 130.02 # Average achieved write bandwidth in MB/s 303system.physmem.avgConsumedRdBW 265.42 # Average consumed read bandwidth in MB/s 304system.physmem.avgConsumedWrBW 130.02 # Average consumed write bandwidth in MB/s 305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 306system.physmem.busUtil 3.09 # Data bus utilization in percentage 307system.physmem.avgRdQLen 0.23 # Average read queue length over time 308system.physmem.avgWrQLen 10.65 # Average write queue length over time 309system.physmem.readRowHits 1005654 # Number of row buffer hits during reads 310system.physmem.writeRowHits 343066 # Number of row buffer hits during writes 311system.physmem.readRowHitRate 44.78 # Row buffer hit rate for reads 312system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes 313system.physmem.avgGap 161845.21 # Average gap between requests 314system.membus.throughput 395439408 # Throughput (bytes/s) 315system.membus.trans_dist::ReadReq 1420071 # Transaction distribution 316system.membus.trans_dist::ReadResp 1420070 # Transaction distribution 317system.membus.trans_dist::Writeback 1100477 # Transaction distribution 318system.membus.trans_dist::ReadExReq 826393 # Transaction distribution 319system.membus.trans_dist::ReadExResp 826393 # Transaction distribution 320system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593404 # Packet count per connected master and slave (bytes) 321system.membus.pkt_count::total 5593404 # Packet count per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214204160 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size::total 214204160 # Cumulative packet size per connected master and slave (bytes) 324system.membus.data_through_bus 214204160 # Total data (bytes) 325system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 326system.membus.reqLayer0.occupancy 12928469250 # Layer occupancy (ticks) 327system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 328system.membus.respLayer1.occupancy 21152142500 # Layer occupancy (ticks) 329system.membus.respLayer1.utilization 3.9 # Layer utilization (%) 330system.cpu.branchPred.lookups 304298989 # Number of BP lookups 331system.cpu.branchPred.condPredicted 250519406 # Number of conditional branches predicted 332system.cpu.branchPred.condIncorrect 15198708 # Number of conditional branches incorrect 333system.cpu.branchPred.BTBLookups 177303182 # Number of BTB lookups 334system.cpu.branchPred.BTBHits 162516904 # Number of BTB hits 335system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 336system.cpu.branchPred.BTBHitPct 91.660455 # BTB Hit Percentage 337system.cpu.branchPred.usedRAS 17540360 # Number of times the RAS was used to get a target. 338system.cpu.branchPred.RASInCorrect 213 # Number of incorrect RAS predictions. 339system.cpu.dtb.inst_hits 0 # ITB inst hits 340system.cpu.dtb.inst_misses 0 # ITB inst misses 341system.cpu.dtb.read_hits 0 # DTB read hits 342system.cpu.dtb.read_misses 0 # DTB read misses 343system.cpu.dtb.write_hits 0 # DTB write hits 344system.cpu.dtb.write_misses 0 # DTB write misses 345system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 346system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 347system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 348system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 349system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 350system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 351system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 352system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 353system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 354system.cpu.dtb.read_accesses 0 # DTB read accesses 355system.cpu.dtb.write_accesses 0 # DTB write accesses 356system.cpu.dtb.inst_accesses 0 # ITB inst accesses 357system.cpu.dtb.hits 0 # DTB hits 358system.cpu.dtb.misses 0 # DTB misses 359system.cpu.dtb.accesses 0 # DTB accesses 360system.cpu.itb.inst_hits 0 # ITB inst hits 361system.cpu.itb.inst_misses 0 # ITB inst misses 362system.cpu.itb.read_hits 0 # DTB read hits 363system.cpu.itb.read_misses 0 # DTB read misses 364system.cpu.itb.write_hits 0 # DTB write hits 365system.cpu.itb.write_misses 0 # DTB write misses 366system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 367system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 368system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 369system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 370system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 371system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 372system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 373system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.itb.read_accesses 0 # DTB read accesses 376system.cpu.itb.write_accesses 0 # DTB write accesses 377system.cpu.itb.inst_accesses 0 # ITB inst accesses 378system.cpu.itb.hits 0 # DTB hits 379system.cpu.itb.misses 0 # DTB misses 380system.cpu.itb.accesses 0 # DTB accesses 381system.cpu.workload.num_syscalls 46 # Number of system calls 382system.cpu.numCycles 1083372854 # number of cpu cycles simulated 383system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 384system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 385system.cpu.fetch.icacheStallCycles 300343787 # Number of cycles fetch is stalled on an Icache miss 386system.cpu.fetch.Insts 2195221955 # Number of instructions fetch has processed 387system.cpu.fetch.Branches 304298989 # Number of branches that fetch encountered 388system.cpu.fetch.predictedBranches 180057264 # Number of branches that fetch has predicted taken 389system.cpu.fetch.Cycles 436998042 # Number of cycles fetch has run and was not squashing or blocked 390system.cpu.fetch.SquashCycles 88977352 # Number of cycles fetch has spent squashing 391system.cpu.fetch.BlockedCycles 165479201 # Number of cycles fetch has spent blocked 392system.cpu.fetch.PendingTrapStallCycles 101 # Number of stall cycles due to pending traps 393system.cpu.fetch.CacheLines 290623561 # Number of cache lines fetched 394system.cpu.fetch.IcacheSquashes 6109702 # Number of outstanding Icache misses that were squashed 395system.cpu.fetch.rateDist::samples 973376815 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::mean 2.494162 # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::stdev 3.204787 # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::0 536378856 55.10% 55.10% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::1 25841118 2.65% 57.76% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::2 39079231 4.01% 61.77% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::3 48353852 4.97% 66.74% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::4 43959831 4.52% 71.26% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::5 46474608 4.77% 76.03% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::6 38397974 3.94% 79.98% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::7 19032697 1.96% 81.93% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::8 175858648 18.07% 100.00% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::total 973376815 # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.branchRate 0.280881 # Number of branch fetches per cycle 413system.cpu.fetch.rate 2.026285 # Number of inst fetches per cycle 414system.cpu.decode.IdleCycles 332723748 # Number of cycles decode is idle 415system.cpu.decode.BlockedCycles 143314435 # Number of cycles decode is blocked 416system.cpu.decode.RunCycles 406466996 # Number of cycles decode is running 417system.cpu.decode.UnblockCycles 20316722 # Number of cycles decode is unblocking 418system.cpu.decode.SquashCycles 70554914 # Number of cycles decode is squashing 419system.cpu.decode.BranchResolved 46046806 # Number of times decode resolved a branch 420system.cpu.decode.BranchMispred 803 # Number of times decode detected a branch misprediction 421system.cpu.decode.DecodedInsts 2374638821 # Number of instructions handled by decode 422system.cpu.decode.SquashedInsts 2490 # Number of squashed instructions handled by decode 423system.cpu.rename.SquashCycles 70554914 # Number of cycles rename is squashing 424system.cpu.rename.IdleCycles 356505375 # Number of cycles rename is idle 425system.cpu.rename.BlockCycles 71902909 # Number of cycles rename is blocking 426system.cpu.rename.serializeStallCycles 22171 # count of cycles rename stalled for serializing inst 427system.cpu.rename.RunCycles 401350772 # Number of cycles rename is running 428system.cpu.rename.UnblockCycles 73040674 # Number of cycles rename is unblocking 429system.cpu.rename.RenamedInsts 2310606044 # Number of instructions processed by rename 430system.cpu.rename.ROBFullEvents 153145 # Number of times rename has blocked due to ROB full 431system.cpu.rename.IQFullEvents 5003938 # Number of times rename has blocked due to IQ full 432system.cpu.rename.LSQFullEvents 60088597 # Number of times rename has blocked due to LSQ full 433system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers 434system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed 435system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made 436system.cpu.rename.int_rename_lookups 9782199775 # Number of integer rename lookups 437system.cpu.rename.fp_rename_lookups 333 # Number of floating rename lookups 438system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed 439system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing 440system.cpu.rename.serializingInsts 862 # count of serializing insts renamed 441system.cpu.rename.tempSerializingInsts 859 # count of temporary serializing insts renamed 442system.cpu.rename.skidInsts 161072397 # count of insts added to the skid buffer 443system.cpu.memDep0.insertedLoads 625574992 # Number of loads inserted to the mem dependence unit. 444system.cpu.memDep0.insertedStores 221105439 # Number of stores inserted to the mem dependence unit. 445system.cpu.memDep0.conflictingLoads 85703818 # Number of conflicting loads. 446system.cpu.memDep0.conflictingStores 70396970 # Number of conflicting stores. 447system.cpu.iq.iqInstsAdded 2205173654 # Number of instructions added to the IQ (excludes non-spec) 448system.cpu.iq.iqNonSpecInstsAdded 876 # Number of non-speculative instructions added to the IQ 449system.cpu.iq.iqInstsIssued 2020003765 # Number of instructions issued 450system.cpu.iq.iqSquashedInstsIssued 4023223 # Number of squashed instructions issued 451system.cpu.iq.iqSquashedInstsExamined 477517821 # Number of squashed instructions iterated over during squash; mainly for profiling 452system.cpu.iq.iqSquashedOperandsExamined 1138229874 # Number of squashed operands that are examined and possibly removed from graph 453system.cpu.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed 454system.cpu.iq.issued_per_cycle::samples 973376815 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::mean 2.075254 # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::stdev 1.906645 # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::0 290079957 29.80% 29.80% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::1 153607537 15.78% 45.58% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::2 161004232 16.54% 62.12% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::3 120476061 12.38% 74.50% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::4 123716545 12.71% 87.21% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::5 73794754 7.58% 94.79% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::6 38284776 3.93% 98.72% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::7 9892649 1.02% 99.74% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::8 2520304 0.26% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::total 973376815 # Number of insts issued each cycle 471system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntAlu 894925 3.74% 3.74% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntMult 5467 0.02% 3.76% # attempts to use FU when none available 474system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available 480system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemRead 18249723 76.22% 79.99% # attempts to use FU when none available 502system.cpu.iq.fu_full::MemWrite 4791929 20.01% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 505system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 506system.cpu.iq.FU_type_0::IntAlu 1237561423 61.27% 61.27% # Type of FU issued 507system.cpu.iq.FU_type_0::IntMult 924895 0.05% 61.31% # Type of FU issued 508system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.31% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.31% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.31% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.31% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.31% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.31% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.31% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.31% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.31% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.31% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.31% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.31% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.31% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.31% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.31% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 61.31% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.31% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued 535system.cpu.iq.FU_type_0::MemRead 588422338 29.13% 90.44% # Type of FU issued 536system.cpu.iq.FU_type_0::MemWrite 193095054 9.56% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 538system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 539system.cpu.iq.FU_type_0::total 2020003765 # Type of FU issued 540system.cpu.iq.rate 1.864551 # Inst issue rate 541system.cpu.iq.fu_busy_cnt 23942044 # FU busy when requested 542system.cpu.iq.fu_busy_rate 0.011852 # FU busy rate (busy events/executed inst) 543system.cpu.iq.int_inst_queue_reads 5041349349 # Number of integer instruction queue reads 544system.cpu.iq.int_inst_queue_writes 2682881596 # Number of integer instruction queue writes 545system.cpu.iq.int_inst_queue_wakeup_accesses 1957831333 # Number of integer instruction queue wakeup accesses 546system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads 547system.cpu.iq.fp_inst_queue_writes 528 # Number of floating instruction queue writes 548system.cpu.iq.fp_inst_queue_wakeup_accesses 100 # Number of floating instruction queue wakeup accesses 549system.cpu.iq.int_alu_accesses 2043945677 # Number of integer alu accesses 550system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses 551system.cpu.iew.lsq.thread0.forwLoads 64652125 # Number of loads that had data forwarded from stores 552system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 553system.cpu.iew.lsq.thread0.squashedLoads 139648223 # Number of loads squashed 554system.cpu.iew.lsq.thread0.ignoredResponses 271348 # Number of memory responses ignored because the instruction is squashed 555system.cpu.iew.lsq.thread0.memOrderViolation 192348 # Number of memory ordering violations 556system.cpu.iew.lsq.thread0.squashedStores 46258394 # Number of stores squashed 557system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 558system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 559system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled 560system.cpu.iew.lsq.thread0.cacheBlocked 5367173 # Number of times an access to memory failed due to the cache being blocked 561system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 562system.cpu.iew.iewSquashCycles 70554914 # Number of cycles IEW is squashing 563system.cpu.iew.iewBlockCycles 34630118 # Number of cycles IEW is blocking 564system.cpu.iew.iewUnblockCycles 1599053 # Number of cycles IEW is unblocking 565system.cpu.iew.iewDispatchedInsts 2205174629 # Number of instructions dispatched to IQ 566system.cpu.iew.iewDispSquashedInsts 7647376 # Number of squashed instructions skipped by dispatch 567system.cpu.iew.iewDispLoadInsts 625574992 # Number of dispatched load instructions 568system.cpu.iew.iewDispStoreInsts 221105439 # Number of dispatched store instructions 569system.cpu.iew.iewDispNonSpecInsts 814 # Number of dispatched non-speculative instructions 570system.cpu.iew.iewIQFullEvents 476287 # Number of times the IQ has become full, causing a stall 571system.cpu.iew.iewLSQFullEvents 97145 # Number of times the LSQ has become full, causing a stall 572system.cpu.iew.memOrderViolationEvents 192348 # Number of memory order violations 573system.cpu.iew.predictedTakenIncorrect 8141918 # Number of branches that were predicted taken incorrectly 574system.cpu.iew.predictedNotTakenIncorrect 9600574 # Number of branches that were predicted not taken incorrectly 575system.cpu.iew.branchMispredicts 17742492 # Number of branch mispredicts detected at execute 576system.cpu.iew.iewExecutedInsts 1989129664 # Number of executed instructions 577system.cpu.iew.iewExecLoadInsts 574576777 # Number of load instructions executed 578system.cpu.iew.iewExecSquashedInsts 30874101 # Number of squashed instructions skipped in execute 579system.cpu.iew.exec_swp 0 # number of swp insts executed 580system.cpu.iew.exec_nop 99 # number of nop insts executed 581system.cpu.iew.exec_refs 764789002 # number of memory reference insts executed 582system.cpu.iew.exec_branches 238317780 # Number of branches executed 583system.cpu.iew.exec_stores 190212225 # Number of stores executed 584system.cpu.iew.exec_rate 1.836053 # Inst execution rate 585system.cpu.iew.wb_sent 1966244201 # cumulative count of insts sent to commit 586system.cpu.iew.wb_count 1957831433 # cumulative count of insts written-back 587system.cpu.iew.wb_producers 1295814578 # num instructions producing a value 588system.cpu.iew.wb_consumers 2059506895 # num instructions consuming a value 589system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 590system.cpu.iew.wb_rate 1.807163 # insts written-back per cycle 591system.cpu.iew.wb_fanout 0.629187 # average fanout of values written-back 592system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 593system.cpu.commit.commitSquashedInsts 482200307 # The number of squashed insts skipped by commit 594system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 595system.cpu.commit.branchMispredicts 15197938 # The number of times a branch was mispredicted 596system.cpu.commit.committed_per_cycle::samples 902821901 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::mean 1.908542 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::stdev 2.715709 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::0 414368116 45.90% 45.90% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::1 193212165 21.40% 67.30% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::2 72772864 8.06% 75.36% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::3 35254508 3.90% 79.26% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::4 18855841 2.09% 81.35% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::5 30818249 3.41% 84.77% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::6 19938130 2.21% 86.97% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::7 11407177 1.26% 88.24% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::8 106194851 11.76% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::total 902821901 # Number of insts commited each cycle 613system.cpu.commit.committedInsts 1544563041 # Number of instructions committed 614system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed 615system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 616system.cpu.commit.refs 660773814 # Number of memory references committed 617system.cpu.commit.loads 485926769 # Number of loads committed 618system.cpu.commit.membars 62 # Number of memory barriers committed 619system.cpu.commit.branches 213462426 # Number of branches committed 620system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 621system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. 622system.cpu.commit.function_calls 13665177 # Number of function calls committed. 623system.cpu.commit.bw_lim_events 106194851 # number cycles where commit BW limit reached 624system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 625system.cpu.rob.rob_reads 3001900611 # The number of ROB reads 626system.cpu.rob.rob_writes 4481254115 # The number of ROB writes 627system.cpu.timesIdled 1150610 # Number of times that the entire CPU went into an idle state and unscheduled itself 628system.cpu.idleCycles 109996039 # Total number of cycles that the CPU has spent unscheduled due to idling 629system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 630system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated 631system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated 632system.cpu.cpi 0.701411 # CPI: Cycles Per Instruction 633system.cpu.cpi_total 0.701411 # CPI: Total CPI of All Threads 634system.cpu.ipc 1.425698 # IPC: Instructions Per Cycle 635system.cpu.ipc_total 1.425698 # IPC: Total IPC of All Threads 636system.cpu.int_regfile_reads 9960721721 # number of integer regfile reads 637system.cpu.int_regfile_writes 1937694107 # number of integer regfile writes 638system.cpu.fp_regfile_reads 91 # number of floating regfile reads 639system.cpu.fp_regfile_writes 89 # number of floating regfile writes 640system.cpu.misc_regfile_reads 737621013 # number of misc regfile reads 641system.cpu.misc_regfile_writes 124 # number of misc regfile writes 642system.cpu.toL2Bus.throughput 1581534685 # Throughput (bytes/s) 643system.cpu.toL2Bus.trans_dist::ReadReq 7709688 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::ReadResp 7709687 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::Writeback 3782769 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExReq 1893417 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadExResp 1893417 # Transaction distribution 648system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1564 # Packet count per connected master and slave (bytes) 649system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22987414 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.pkt_count::total 22988978 # Packet count per connected master and slave (bytes) 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50048 # Cumulative packet size per connected master and slave (bytes) 652system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856645824 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.tot_pkt_size::total 856695872 # Cumulative packet size per connected master and slave (bytes) 654system.cpu.toL2Bus.data_through_bus 856695872 # Total data (bytes) 655system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 656system.cpu.toL2Bus.reqLayer0.occupancy 10475876330 # Layer occupancy (ticks) 657system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) 658system.cpu.toL2Bus.respLayer0.occupancy 1321749 # Layer occupancy (ticks) 659system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 660system.cpu.toL2Bus.respLayer1.occupancy 14846430743 # Layer occupancy (ticks) 661system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) 662system.cpu.icache.tags.replacements 22 # number of replacements 663system.cpu.icache.tags.tagsinuse 629.635316 # Cycle average of tags in use 664system.cpu.icache.tags.total_refs 290622345 # Total number of references to valid blocks. 665system.cpu.icache.tags.sampled_refs 782 # Sample count of references to valid blocks. 666system.cpu.icache.tags.avg_refs 371639.827366 # Average number of references to valid blocks. 667system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 668system.cpu.icache.tags.occ_blocks::cpu.inst 629.635316 # Average occupied blocks per requestor 669system.cpu.icache.tags.occ_percent::cpu.inst 0.307439 # Average percentage of cache occupancy 670system.cpu.icache.tags.occ_percent::total 0.307439 # Average percentage of cache occupancy 671system.cpu.icache.ReadReq_hits::cpu.inst 290622345 # number of ReadReq hits 672system.cpu.icache.ReadReq_hits::total 290622345 # number of ReadReq hits 673system.cpu.icache.demand_hits::cpu.inst 290622345 # number of demand (read+write) hits 674system.cpu.icache.demand_hits::total 290622345 # number of demand (read+write) hits 675system.cpu.icache.overall_hits::cpu.inst 290622345 # number of overall hits 676system.cpu.icache.overall_hits::total 290622345 # number of overall hits 677system.cpu.icache.ReadReq_misses::cpu.inst 1216 # number of ReadReq misses 678system.cpu.icache.ReadReq_misses::total 1216 # number of ReadReq misses 679system.cpu.icache.demand_misses::cpu.inst 1216 # number of demand (read+write) misses 680system.cpu.icache.demand_misses::total 1216 # number of demand (read+write) misses 681system.cpu.icache.overall_misses::cpu.inst 1216 # number of overall misses 682system.cpu.icache.overall_misses::total 1216 # number of overall misses 683system.cpu.icache.ReadReq_miss_latency::cpu.inst 85849749 # number of ReadReq miss cycles 684system.cpu.icache.ReadReq_miss_latency::total 85849749 # number of ReadReq miss cycles 685system.cpu.icache.demand_miss_latency::cpu.inst 85849749 # number of demand (read+write) miss cycles 686system.cpu.icache.demand_miss_latency::total 85849749 # number of demand (read+write) miss cycles 687system.cpu.icache.overall_miss_latency::cpu.inst 85849749 # number of overall miss cycles 688system.cpu.icache.overall_miss_latency::total 85849749 # number of overall miss cycles 689system.cpu.icache.ReadReq_accesses::cpu.inst 290623561 # number of ReadReq accesses(hits+misses) 690system.cpu.icache.ReadReq_accesses::total 290623561 # number of ReadReq accesses(hits+misses) 691system.cpu.icache.demand_accesses::cpu.inst 290623561 # number of demand (read+write) accesses 692system.cpu.icache.demand_accesses::total 290623561 # number of demand (read+write) accesses 693system.cpu.icache.overall_accesses::cpu.inst 290623561 # number of overall (read+write) accesses 694system.cpu.icache.overall_accesses::total 290623561 # number of overall (read+write) accesses 695system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 696system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 697system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 698system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 699system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 700system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 701system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70600.122533 # average ReadReq miss latency 702system.cpu.icache.ReadReq_avg_miss_latency::total 70600.122533 # average ReadReq miss latency 703system.cpu.icache.demand_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency 704system.cpu.icache.demand_avg_miss_latency::total 70600.122533 # average overall miss latency 705system.cpu.icache.overall_avg_miss_latency::cpu.inst 70600.122533 # average overall miss latency 706system.cpu.icache.overall_avg_miss_latency::total 70600.122533 # average overall miss latency 707system.cpu.icache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked 708system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 709system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked 710system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 711system.cpu.icache.avg_blocked_cycles::no_mshrs 50.250000 # average number of cycles each access was blocked 712system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 713system.cpu.icache.fast_writes 0 # number of fast writes performed 714system.cpu.icache.cache_copies 0 # number of cache copies performed 715system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits 716system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits 717system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits 718system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits 719system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits 720system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits 721system.cpu.icache.ReadReq_mshr_misses::cpu.inst 782 # number of ReadReq MSHR misses 722system.cpu.icache.ReadReq_mshr_misses::total 782 # number of ReadReq MSHR misses 723system.cpu.icache.demand_mshr_misses::cpu.inst 782 # number of demand (read+write) MSHR misses 724system.cpu.icache.demand_mshr_misses::total 782 # number of demand (read+write) MSHR misses 725system.cpu.icache.overall_mshr_misses::cpu.inst 782 # number of overall MSHR misses 726system.cpu.icache.overall_mshr_misses::total 782 # number of overall MSHR misses 727system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59439751 # number of ReadReq MSHR miss cycles 728system.cpu.icache.ReadReq_mshr_miss_latency::total 59439751 # number of ReadReq MSHR miss cycles 729system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59439751 # number of demand (read+write) MSHR miss cycles 730system.cpu.icache.demand_mshr_miss_latency::total 59439751 # number of demand (read+write) MSHR miss cycles 731system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59439751 # number of overall MSHR miss cycles 732system.cpu.icache.overall_mshr_miss_latency::total 59439751 # number of overall MSHR miss cycles 733system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 734system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 735system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 736system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 737system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 738system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 739system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76009.911765 # average ReadReq mshr miss latency 740system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76009.911765 # average ReadReq mshr miss latency 741system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency 742system.cpu.icache.demand_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency 743system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76009.911765 # average overall mshr miss latency 744system.cpu.icache.overall_avg_mshr_miss_latency::total 76009.911765 # average overall mshr miss latency 745system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 746system.cpu.l2cache.tags.replacements 2213775 # number of replacements 747system.cpu.l2cache.tags.tagsinuse 31546.363307 # Cycle average of tags in use 748system.cpu.l2cache.tags.total_refs 9248170 # Total number of references to valid blocks. 749system.cpu.l2cache.tags.sampled_refs 2243553 # Sample count of references to valid blocks. 750system.cpu.l2cache.tags.avg_refs 4.122109 # Average number of references to valid blocks. 751system.cpu.l2cache.tags.warmup_cycle 21352949250 # Cycle when the warmup percentage was hit. 752system.cpu.l2cache.tags.occ_blocks::writebacks 14312.491305 # Average occupied blocks per requestor 753system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.144724 # Average occupied blocks per requestor 754system.cpu.l2cache.tags.occ_blocks::cpu.data 17213.727277 # Average occupied blocks per requestor 755system.cpu.l2cache.tags.occ_percent::writebacks 0.436783 # Average percentage of cache occupancy 756system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000615 # Average percentage of cache occupancy 757system.cpu.l2cache.tags.occ_percent::cpu.data 0.525321 # Average percentage of cache occupancy 758system.cpu.l2cache.tags.occ_percent::total 0.962719 # Average percentage of cache occupancy 759system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits 760system.cpu.l2cache.ReadReq_hits::cpu.data 6289580 # number of ReadReq hits 761system.cpu.l2cache.ReadReq_hits::total 6289609 # number of ReadReq hits 762system.cpu.l2cache.Writeback_hits::writebacks 3782769 # number of Writeback hits 763system.cpu.l2cache.Writeback_hits::total 3782769 # number of Writeback hits 764system.cpu.l2cache.ReadExReq_hits::cpu.data 1067024 # number of ReadExReq hits 765system.cpu.l2cache.ReadExReq_hits::total 1067024 # number of ReadExReq hits 766system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits 767system.cpu.l2cache.demand_hits::cpu.data 7356604 # number of demand (read+write) hits 768system.cpu.l2cache.demand_hits::total 7356633 # number of demand (read+write) hits 769system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits 770system.cpu.l2cache.overall_hits::cpu.data 7356604 # number of overall hits 771system.cpu.l2cache.overall_hits::total 7356633 # number of overall hits 772system.cpu.l2cache.ReadReq_misses::cpu.inst 753 # number of ReadReq misses 773system.cpu.l2cache.ReadReq_misses::cpu.data 1419326 # number of ReadReq misses 774system.cpu.l2cache.ReadReq_misses::total 1420079 # number of ReadReq misses 775system.cpu.l2cache.ReadExReq_misses::cpu.data 826393 # number of ReadExReq misses 776system.cpu.l2cache.ReadExReq_misses::total 826393 # number of ReadExReq misses 777system.cpu.l2cache.demand_misses::cpu.inst 753 # number of demand (read+write) misses 778system.cpu.l2cache.demand_misses::cpu.data 2245719 # number of demand (read+write) misses 779system.cpu.l2cache.demand_misses::total 2246472 # number of demand (read+write) misses 780system.cpu.l2cache.overall_misses::cpu.inst 753 # number of overall misses 781system.cpu.l2cache.overall_misses::cpu.data 2245719 # number of overall misses 782system.cpu.l2cache.overall_misses::total 2246472 # number of overall misses 783system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58361250 # number of ReadReq miss cycles 784system.cpu.l2cache.ReadReq_miss_latency::cpu.data 138416431000 # number of ReadReq miss cycles 785system.cpu.l2cache.ReadReq_miss_latency::total 138474792250 # number of ReadReq miss cycles 786system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84266311250 # number of ReadExReq miss cycles 787system.cpu.l2cache.ReadExReq_miss_latency::total 84266311250 # number of ReadExReq miss cycles 788system.cpu.l2cache.demand_miss_latency::cpu.inst 58361250 # number of demand (read+write) miss cycles 789system.cpu.l2cache.demand_miss_latency::cpu.data 222682742250 # number of demand (read+write) miss cycles 790system.cpu.l2cache.demand_miss_latency::total 222741103500 # number of demand (read+write) miss cycles 791system.cpu.l2cache.overall_miss_latency::cpu.inst 58361250 # number of overall miss cycles 792system.cpu.l2cache.overall_miss_latency::cpu.data 222682742250 # number of overall miss cycles 793system.cpu.l2cache.overall_miss_latency::total 222741103500 # number of overall miss cycles 794system.cpu.l2cache.ReadReq_accesses::cpu.inst 782 # number of ReadReq accesses(hits+misses) 795system.cpu.l2cache.ReadReq_accesses::cpu.data 7708906 # number of ReadReq accesses(hits+misses) 796system.cpu.l2cache.ReadReq_accesses::total 7709688 # number of ReadReq accesses(hits+misses) 797system.cpu.l2cache.Writeback_accesses::writebacks 3782769 # number of Writeback accesses(hits+misses) 798system.cpu.l2cache.Writeback_accesses::total 3782769 # number of Writeback accesses(hits+misses) 799system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893417 # number of ReadExReq accesses(hits+misses) 800system.cpu.l2cache.ReadExReq_accesses::total 1893417 # number of ReadExReq accesses(hits+misses) 801system.cpu.l2cache.demand_accesses::cpu.inst 782 # number of demand (read+write) accesses 802system.cpu.l2cache.demand_accesses::cpu.data 9602323 # number of demand (read+write) accesses 803system.cpu.l2cache.demand_accesses::total 9603105 # number of demand (read+write) accesses 804system.cpu.l2cache.overall_accesses::cpu.inst 782 # number of overall (read+write) accesses 805system.cpu.l2cache.overall_accesses::cpu.data 9602323 # number of overall (read+write) accesses 806system.cpu.l2cache.overall_accesses::total 9603105 # number of overall (read+write) accesses 807system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962916 # miss rate for ReadReq accesses 808system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184115 # miss rate for ReadReq accesses 809system.cpu.l2cache.ReadReq_miss_rate::total 0.184194 # miss rate for ReadReq accesses 810system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436456 # miss rate for ReadExReq accesses 811system.cpu.l2cache.ReadExReq_miss_rate::total 0.436456 # miss rate for ReadExReq accesses 812system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962916 # miss rate for demand accesses 813system.cpu.l2cache.demand_miss_rate::cpu.data 0.233872 # miss rate for demand accesses 814system.cpu.l2cache.demand_miss_rate::total 0.233932 # miss rate for demand accesses 815system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962916 # miss rate for overall accesses 816system.cpu.l2cache.overall_miss_rate::cpu.data 0.233872 # miss rate for overall accesses 817system.cpu.l2cache.overall_miss_rate::total 0.233932 # miss rate for overall accesses 818system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77504.980080 # average ReadReq miss latency 819system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97522.648778 # average ReadReq miss latency 820system.cpu.l2cache.ReadReq_avg_miss_latency::total 97512.034366 # average ReadReq miss latency 821system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101968.810542 # average ReadExReq miss latency 822system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101968.810542 # average ReadExReq miss latency 823system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77504.980080 # average overall miss latency 824system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99158.773760 # average overall miss latency 825system.cpu.l2cache.demand_avg_miss_latency::total 99151.515576 # average overall miss latency 826system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77504.980080 # average overall miss latency 827system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99158.773760 # average overall miss latency 828system.cpu.l2cache.overall_avg_miss_latency::total 99151.515576 # average overall miss latency 829system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 830system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 831system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 832system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 833system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 834system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 835system.cpu.l2cache.fast_writes 0 # number of fast writes performed 836system.cpu.l2cache.cache_copies 0 # number of cache copies performed 837system.cpu.l2cache.writebacks::writebacks 1100477 # number of writebacks 838system.cpu.l2cache.writebacks::total 1100477 # number of writebacks 839system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 840system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits 841system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits 842system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 843system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits 844system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 845system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 846system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits 847system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits 848system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 752 # number of ReadReq MSHR misses 849system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419319 # number of ReadReq MSHR misses 850system.cpu.l2cache.ReadReq_mshr_misses::total 1420071 # number of ReadReq MSHR misses 851system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826393 # number of ReadExReq MSHR misses 852system.cpu.l2cache.ReadExReq_mshr_misses::total 826393 # number of ReadExReq MSHR misses 853system.cpu.l2cache.demand_mshr_misses::cpu.inst 752 # number of demand (read+write) MSHR misses 854system.cpu.l2cache.demand_mshr_misses::cpu.data 2245712 # number of demand (read+write) MSHR misses 855system.cpu.l2cache.demand_mshr_misses::total 2246464 # number of demand (read+write) MSHR misses 856system.cpu.l2cache.overall_mshr_misses::cpu.inst 752 # number of overall MSHR misses 857system.cpu.l2cache.overall_mshr_misses::cpu.data 2245712 # number of overall MSHR misses 858system.cpu.l2cache.overall_mshr_misses::total 2246464 # number of overall MSHR misses 859system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48787000 # number of ReadReq MSHR miss cycles 860system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 120499016750 # number of ReadReq MSHR miss cycles 861system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120547803750 # number of ReadReq MSHR miss cycles 862system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73852563750 # number of ReadExReq MSHR miss cycles 863system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73852563750 # number of ReadExReq MSHR miss cycles 864system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48787000 # number of demand (read+write) MSHR miss cycles 865system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 194351580500 # number of demand (read+write) MSHR miss cycles 866system.cpu.l2cache.demand_mshr_miss_latency::total 194400367500 # number of demand (read+write) MSHR miss cycles 867system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48787000 # number of overall MSHR miss cycles 868system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 194351580500 # number of overall MSHR miss cycles 869system.cpu.l2cache.overall_mshr_miss_latency::total 194400367500 # number of overall MSHR miss cycles 870system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for ReadReq accesses 871system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184114 # mshr miss rate for ReadReq accesses 872system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184193 # mshr miss rate for ReadReq accesses 873system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436456 # mshr miss rate for ReadExReq accesses 874system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436456 # mshr miss rate for ReadExReq accesses 875system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for demand accesses 876system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for demand accesses 877system.cpu.l2cache.demand_mshr_miss_rate::total 0.233931 # mshr miss rate for demand accesses 878system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961637 # mshr miss rate for overall accesses 879system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233872 # mshr miss rate for overall accesses 880system.cpu.l2cache.overall_mshr_miss_rate::total 0.233931 # mshr miss rate for overall accesses 881system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64876.329787 # average ReadReq mshr miss latency 882system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84899.178233 # average ReadReq mshr miss latency 883system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84888.575113 # average ReadReq mshr miss latency 884system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89367.363651 # average ReadExReq mshr miss latency 885system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89367.363651 # average ReadExReq mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency 887system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64876.329787 # average overall mshr miss latency 890system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86543.412735 # average overall mshr miss latency 891system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86536.159716 # average overall mshr miss latency 892system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 893system.cpu.dcache.tags.replacements 9598226 # number of replacements 894system.cpu.dcache.tags.tagsinuse 4088.205485 # Cycle average of tags in use 895system.cpu.dcache.tags.total_refs 655929620 # Total number of references to valid blocks. 896system.cpu.dcache.tags.sampled_refs 9602322 # Sample count of references to valid blocks. 897system.cpu.dcache.tags.avg_refs 68.309480 # Average number of references to valid blocks. 898system.cpu.dcache.tags.warmup_cycle 3516509250 # Cycle when the warmup percentage was hit. 899system.cpu.dcache.tags.occ_blocks::cpu.data 4088.205485 # Average occupied blocks per requestor 900system.cpu.dcache.tags.occ_percent::cpu.data 0.998097 # Average percentage of cache occupancy 901system.cpu.dcache.tags.occ_percent::total 0.998097 # Average percentage of cache occupancy 902system.cpu.dcache.ReadReq_hits::cpu.data 488969047 # number of ReadReq hits 903system.cpu.dcache.ReadReq_hits::total 488969047 # number of ReadReq hits 904system.cpu.dcache.WriteReq_hits::cpu.data 166960447 # number of WriteReq hits 905system.cpu.dcache.WriteReq_hits::total 166960447 # number of WriteReq hits 906system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits 907system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits 908system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 909system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 910system.cpu.dcache.demand_hits::cpu.data 655929494 # number of demand (read+write) hits 911system.cpu.dcache.demand_hits::total 655929494 # number of demand (read+write) hits 912system.cpu.dcache.overall_hits::cpu.data 655929494 # number of overall hits 913system.cpu.dcache.overall_hits::total 655929494 # number of overall hits 914system.cpu.dcache.ReadReq_misses::cpu.data 11507818 # number of ReadReq misses 915system.cpu.dcache.ReadReq_misses::total 11507818 # number of ReadReq misses 916system.cpu.dcache.WriteReq_misses::cpu.data 5625600 # number of WriteReq misses 917system.cpu.dcache.WriteReq_misses::total 5625600 # number of WriteReq misses 918system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 919system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 920system.cpu.dcache.demand_misses::cpu.data 17133418 # number of demand (read+write) misses 921system.cpu.dcache.demand_misses::total 17133418 # number of demand (read+write) misses 922system.cpu.dcache.overall_misses::cpu.data 17133418 # number of overall misses 923system.cpu.dcache.overall_misses::total 17133418 # number of overall misses 924system.cpu.dcache.ReadReq_miss_latency::cpu.data 381897864985 # number of ReadReq miss cycles 925system.cpu.dcache.ReadReq_miss_latency::total 381897864985 # number of ReadReq miss cycles 926system.cpu.dcache.WriteReq_miss_latency::cpu.data 310946372440 # number of WriteReq miss cycles 927system.cpu.dcache.WriteReq_miss_latency::total 310946372440 # number of WriteReq miss cycles 928system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles 929system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles 930system.cpu.dcache.demand_miss_latency::cpu.data 692844237425 # number of demand (read+write) miss cycles 931system.cpu.dcache.demand_miss_latency::total 692844237425 # number of demand (read+write) miss cycles 932system.cpu.dcache.overall_miss_latency::cpu.data 692844237425 # number of overall miss cycles 933system.cpu.dcache.overall_miss_latency::total 692844237425 # number of overall miss cycles 934system.cpu.dcache.ReadReq_accesses::cpu.data 500476865 # number of ReadReq accesses(hits+misses) 935system.cpu.dcache.ReadReq_accesses::total 500476865 # number of ReadReq accesses(hits+misses) 936system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 937system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 938system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) 939system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) 940system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 941system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 942system.cpu.dcache.demand_accesses::cpu.data 673062912 # number of demand (read+write) accesses 943system.cpu.dcache.demand_accesses::total 673062912 # number of demand (read+write) accesses 944system.cpu.dcache.overall_accesses::cpu.data 673062912 # number of overall (read+write) accesses 945system.cpu.dcache.overall_accesses::total 673062912 # number of overall (read+write) accesses 946system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022994 # miss rate for ReadReq accesses 947system.cpu.dcache.ReadReq_miss_rate::total 0.022994 # miss rate for ReadReq accesses 948system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032596 # miss rate for WriteReq accesses 949system.cpu.dcache.WriteReq_miss_rate::total 0.032596 # miss rate for WriteReq accesses 950system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses 951system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses 952system.cpu.dcache.demand_miss_rate::cpu.data 0.025456 # miss rate for demand accesses 953system.cpu.dcache.demand_miss_rate::total 0.025456 # miss rate for demand accesses 954system.cpu.dcache.overall_miss_rate::cpu.data 0.025456 # miss rate for overall accesses 955system.cpu.dcache.overall_miss_rate::total 0.025456 # miss rate for overall accesses 956system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33185.949325 # average ReadReq miss latency 957system.cpu.dcache.ReadReq_avg_miss_latency::total 33185.949325 # average ReadReq miss latency 958system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55273.459265 # average WriteReq miss latency 959system.cpu.dcache.WriteReq_avg_miss_latency::total 55273.459265 # average WriteReq miss latency 960system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency 961system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency 962system.cpu.dcache.demand_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency 963system.cpu.dcache.demand_avg_miss_latency::total 40438.179786 # average overall miss latency 964system.cpu.dcache.overall_avg_miss_latency::cpu.data 40438.179786 # average overall miss latency 965system.cpu.dcache.overall_avg_miss_latency::total 40438.179786 # average overall miss latency 966system.cpu.dcache.blocked_cycles::no_mshrs 29551948 # number of cycles access was blocked 967system.cpu.dcache.blocked_cycles::no_targets 3560628 # number of cycles access was blocked 968system.cpu.dcache.blocked::no_mshrs 1217583 # number of cycles access was blocked 969system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked 970system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.270993 # average number of cycles each access was blocked 971system.cpu.dcache.avg_blocked_cycles::no_targets 54.667874 # average number of cycles each access was blocked 972system.cpu.dcache.fast_writes 0 # number of fast writes performed 973system.cpu.dcache.cache_copies 0 # number of cache copies performed 974system.cpu.dcache.writebacks::writebacks 3782769 # number of writebacks 975system.cpu.dcache.writebacks::total 3782769 # number of writebacks 976system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798912 # number of ReadReq MSHR hits 977system.cpu.dcache.ReadReq_mshr_hits::total 3798912 # number of ReadReq MSHR hits 978system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732183 # number of WriteReq MSHR hits 979system.cpu.dcache.WriteReq_mshr_hits::total 3732183 # number of WriteReq MSHR hits 980system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 981system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 982system.cpu.dcache.demand_mshr_hits::cpu.data 7531095 # number of demand (read+write) MSHR hits 983system.cpu.dcache.demand_mshr_hits::total 7531095 # number of demand (read+write) MSHR hits 984system.cpu.dcache.overall_mshr_hits::cpu.data 7531095 # number of overall MSHR hits 985system.cpu.dcache.overall_mshr_hits::total 7531095 # number of overall MSHR hits 986system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708906 # number of ReadReq MSHR misses 987system.cpu.dcache.ReadReq_mshr_misses::total 7708906 # number of ReadReq MSHR misses 988system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893417 # number of WriteReq MSHR misses 989system.cpu.dcache.WriteReq_mshr_misses::total 1893417 # number of WriteReq MSHR misses 990system.cpu.dcache.demand_mshr_misses::cpu.data 9602323 # number of demand (read+write) MSHR misses 991system.cpu.dcache.demand_mshr_misses::total 9602323 # number of demand (read+write) MSHR misses 992system.cpu.dcache.overall_mshr_misses::cpu.data 9602323 # number of overall MSHR misses 993system.cpu.dcache.overall_mshr_misses::total 9602323 # number of overall MSHR misses 994system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210908812007 # number of ReadReq MSHR miss cycles 995system.cpu.dcache.ReadReq_mshr_miss_latency::total 210908812007 # number of ReadReq MSHR miss cycles 996system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97317389015 # number of WriteReq MSHR miss cycles 997system.cpu.dcache.WriteReq_mshr_miss_latency::total 97317389015 # number of WriteReq MSHR miss cycles 998system.cpu.dcache.demand_mshr_miss_latency::cpu.data 308226201022 # number of demand (read+write) MSHR miss cycles 999system.cpu.dcache.demand_mshr_miss_latency::total 308226201022 # number of demand (read+write) MSHR miss cycles 1000system.cpu.dcache.overall_mshr_miss_latency::cpu.data 308226201022 # number of overall MSHR miss cycles 1001system.cpu.dcache.overall_mshr_miss_latency::total 308226201022 # number of overall MSHR miss cycles 1002system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses 1003system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses 1004system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses 1005system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses 1006system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for demand accesses 1007system.cpu.dcache.demand_mshr_miss_rate::total 0.014267 # mshr miss rate for demand accesses 1008system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for overall accesses 1009system.cpu.dcache.overall_mshr_miss_rate::total 0.014267 # mshr miss rate for overall accesses 1010system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27359.110619 # average ReadReq mshr miss latency 1011system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27359.110619 # average ReadReq mshr miss latency 1012system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51397.758135 # average WriteReq mshr miss latency 1013system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51397.758135 # average WriteReq mshr miss latency 1014system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency 1015system.cpu.dcache.demand_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency 1016system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32099.128619 # average overall mshr miss latency 1017system.cpu.dcache.overall_avg_mshr_miss_latency::total 32099.128619 # average overall mshr miss latency 1018system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1019 1020---------- End Simulation Statistics ---------- 1021