stats.txt revision 9729:e2fafd224f43
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.540696 # Number of seconds simulated 4sim_ticks 540696400000 # Number of ticks simulated 5final_tick 540696400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 169038 # Simulator instruction rate (inst/s) 8host_op_rate 188575 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59174301 # Simulator tick rate (ticks/s) 10host_mem_usage 246336 # Number of bytes of host memory used 11host_seconds 9137.35 # Real time elapsed on the host 12sim_insts 1544563023 # Number of instructions simulated 13sim_ops 1723073835 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 143740608 # Number of bytes read from this memory 16system.physmem.bytes_read::total 143788736 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 70441600 # Number of bytes written to this memory 20system.physmem.bytes_written::total 70441600 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2245947 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2246699 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1100650 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1100650 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 89011 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 265843471 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 265932483 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 89011 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 89011 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 130279395 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 130279395 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 130279395 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 89011 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 265843471 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 396211878 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 2246699 # Total number of read requests seen 38system.physmem.writeReqs 1100650 # Total number of write requests seen 39system.physmem.cpureqs 3347359 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 143788736 # Total number of bytes read from memory 41system.physmem.bytesWritten 70441600 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 143788736 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 70441600 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 675 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 139594 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 136159 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 133894 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 136244 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 134956 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 135313 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 136207 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 136262 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 143860 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 146526 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 144286 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 146187 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 145855 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 146147 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 142095 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 142439 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 69117 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 67412 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 65719 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 66245 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 66183 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 66419 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 67973 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 68813 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 70394 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 70993 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 70492 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 70984 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 70346 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 70810 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 69619 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 69131 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry 80system.physmem.totGap 540696152000 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 2246699 # Categorize read packet sizes 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes 94system.physmem.writePktSize::6 1100650 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 1614963 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 444775 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 139732 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 46537 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 127system.physmem.wrQLenPdf::0 45615 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 47508 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 47801 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 47831 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 47837 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 47840 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 47843 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 47854 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 47854 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 47854 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 47854 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 47854 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 47854 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 47854 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 47854 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 47854 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 47854 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 47854 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 47854 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 47854 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 47854 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 2240 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 347 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 54 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see 159system.physmem.bytesPerActivate::samples 1997676 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::mean 107.204860 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::gmean 79.811800 # Bytes accessed per row activation 162system.physmem.bytesPerActivate::stdev 283.656472 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::64-65 1593756 79.78% 79.78% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::128-129 230264 11.53% 91.31% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::192-193 68043 3.41% 94.71% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::256-257 32667 1.64% 96.35% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::320-321 17678 0.88% 97.23% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::384-385 10939 0.55% 97.78% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::448-449 7434 0.37% 98.15% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::512-513 7476 0.37% 98.53% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::576-577 4079 0.20% 98.73% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::640-641 3182 0.16% 98.89% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::704-705 2817 0.14% 99.03% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::768-769 2754 0.14% 99.17% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::832-833 1425 0.07% 99.24% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::896-897 1138 0.06% 99.30% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::960-961 999 0.05% 99.35% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1024-1025 880 0.04% 99.39% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1088-1089 791 0.04% 99.43% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1152-1153 732 0.04% 99.47% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1216-1217 642 0.03% 99.50% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1280-1281 540 0.03% 99.53% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1344-1345 574 0.03% 99.56% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1408-1409 838 0.04% 99.60% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1472-1473 3581 0.18% 99.78% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1536-1537 454 0.02% 99.80% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1600-1601 187 0.01% 99.81% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1664-1665 173 0.01% 99.82% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1728-1729 114 0.01% 99.82% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1792-1793 112 0.01% 99.83% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1856-1857 90 0.00% 99.83% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1920-1921 76 0.00% 99.84% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1984-1985 95 0.00% 99.84% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2048-2049 66 0.00% 99.85% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.85% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2176-2177 55 0.00% 99.85% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2240-2241 44 0.00% 99.85% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2304-2305 45 0.00% 99.86% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2368-2369 44 0.00% 99.86% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2432-2433 34 0.00% 99.86% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2496-2497 42 0.00% 99.86% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2560-2561 31 0.00% 99.86% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2624-2625 27 0.00% 99.87% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2688-2689 29 0.00% 99.87% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2752-2753 30 0.00% 99.87% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2816-2817 32 0.00% 99.87% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2880-2881 28 0.00% 99.87% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2944-2945 35 0.00% 99.87% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::3008-3009 28 0.00% 99.87% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::3072-3073 31 0.00% 99.88% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.88% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3264-3265 18 0.00% 99.88% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.88% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.88% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3520-3521 12 0.00% 99.88% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3584-3585 21 0.00% 99.88% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.89% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3712-3713 16 0.00% 99.89% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3776-3777 19 0.00% 99.89% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.89% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.89% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::4032-4033 29 0.00% 99.89% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4096-4097 20 0.00% 99.89% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4160-4161 29 0.00% 99.89% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4224-4225 15 0.00% 99.89% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.89% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4352-4353 6 0.00% 99.89% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.90% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4480-4481 17 0.00% 99.90% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4544-4545 10 0.00% 99.90% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4608-4609 9 0.00% 99.90% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.90% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.90% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4800-4801 11 0.00% 99.90% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.90% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4928-4929 8 0.00% 99.90% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4992-4993 13 0.00% 99.90% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5120-5121 13 0.00% 99.90% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.90% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.90% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.90% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5376-5377 17 0.00% 99.90% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.90% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.90% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5568-5569 7 0.00% 99.90% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.91% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5696-5697 11 0.00% 99.91% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.91% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5888-5889 9 0.00% 99.91% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.91% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.91% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::6080-6081 21 0.00% 99.91% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.91% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.91% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.91% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6528-6529 15 0.00% 99.91% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.91% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.91% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.91% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6784-6785 7 0.00% 99.91% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6848-6849 4 0.00% 99.91% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.91% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.91% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.91% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::7104-7105 16 0.00% 99.91% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.92% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7232-7233 15 0.00% 99.92% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7360-7361 3 0.00% 99.92% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7424-7425 3 0.00% 99.92% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.92% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7552-7553 9 0.00% 99.92% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7616-7617 9 0.00% 99.92% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7680-7681 124 0.01% 99.92% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7744-7745 13 0.00% 99.92% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7808-7809 13 0.00% 99.93% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7872-7873 8 0.00% 99.93% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.93% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::8064-8065 12 0.00% 99.93% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8128-8129 22 0.00% 99.93% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8192-8193 1443 0.07% 100.00% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::total 1997676 # Bytes accessed per row activation 292system.physmem.totQLat 50306526000 # Total cycles spent in queuing delays 293system.physmem.totMemAccLat 124453758500 # Sum of mem lat for all requests 294system.physmem.totBusLat 11230120000 # Total cycles spent in databus access 295system.physmem.totBankLat 62917112500 # Total cycles spent in bank access 296system.physmem.avgQLat 22398.04 # Average queueing delay per request 297system.physmem.avgBankLat 28012.66 # Average bank access latency per request 298system.physmem.avgBusLat 5000.00 # Average bus latency per request 299system.physmem.avgMemAccLat 55410.70 # Average memory access latency 300system.physmem.avgRdBW 265.93 # Average achieved read bandwidth in MB/s 301system.physmem.avgWrBW 130.28 # Average achieved write bandwidth in MB/s 302system.physmem.avgConsumedRdBW 265.93 # Average consumed read bandwidth in MB/s 303system.physmem.avgConsumedWrBW 130.28 # Average consumed write bandwidth in MB/s 304system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 305system.physmem.busUtil 3.10 # Data bus utilization in percentage 306system.physmem.avgRdQLen 0.23 # Average read queue length over time 307system.physmem.avgWrQLen 10.44 # Average write queue length over time 308system.physmem.readRowHits 1005962 # Number of row buffer hits during reads 309system.physmem.writeRowHits 343028 # Number of row buffer hits during writes 310system.physmem.readRowHitRate 44.79 # Row buffer hit rate for reads 311system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes 312system.physmem.avgGap 161529.66 # Average gap between requests 313system.membus.throughput 396211878 # Throughput (bytes/s) 314system.membus.trans_dist::ReadReq 1420214 # Transaction distribution 315system.membus.trans_dist::ReadResp 1420214 # Transaction distribution 316system.membus.trans_dist::Writeback 1100650 # Transaction distribution 317system.membus.trans_dist::ReadExReq 826485 # Transaction distribution 318system.membus.trans_dist::ReadExResp 826485 # Transaction distribution 319system.membus.pkt_count_system.cpu.l2cache.mem_side 5594048 # Packet count per connected master and slave (bytes) 320system.membus.pkt_count 5594048 # Packet count per connected master and slave (bytes) 321system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214230336 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size 214230336 # Cumulative packet size per connected master and slave (bytes) 323system.membus.data_through_bus 214230336 # Total data (bytes) 324system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 325system.membus.reqLayer0.occupancy 12859707750 # Layer occupancy (ticks) 326system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 327system.membus.respLayer1.occupancy 21134071500 # Layer occupancy (ticks) 328system.membus.respLayer1.utilization 3.9 # Layer utilization (%) 329system.cpu.branchPred.lookups 304230401 # Number of BP lookups 330system.cpu.branchPred.condPredicted 250450611 # Number of conditional branches predicted 331system.cpu.branchPred.condIncorrect 15192997 # Number of conditional branches incorrect 332system.cpu.branchPred.BTBLookups 172575058 # Number of BTB lookups 333system.cpu.branchPred.BTBHits 162497547 # Number of BTB hits 334system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 335system.cpu.branchPred.BTBHitPct 94.160506 # BTB Hit Percentage 336system.cpu.branchPred.usedRAS 17547944 # Number of times the RAS was used to get a target. 337system.cpu.branchPred.RASInCorrect 207 # Number of incorrect RAS predictions. 338system.cpu.dtb.inst_hits 0 # ITB inst hits 339system.cpu.dtb.inst_misses 0 # ITB inst misses 340system.cpu.dtb.read_hits 0 # DTB read hits 341system.cpu.dtb.read_misses 0 # DTB read misses 342system.cpu.dtb.write_hits 0 # DTB write hits 343system.cpu.dtb.write_misses 0 # DTB write misses 344system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 345system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 346system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 347system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 348system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 349system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 350system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 351system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.dtb.read_accesses 0 # DTB read accesses 354system.cpu.dtb.write_accesses 0 # DTB write accesses 355system.cpu.dtb.inst_accesses 0 # ITB inst accesses 356system.cpu.dtb.hits 0 # DTB hits 357system.cpu.dtb.misses 0 # DTB misses 358system.cpu.dtb.accesses 0 # DTB accesses 359system.cpu.itb.inst_hits 0 # ITB inst hits 360system.cpu.itb.inst_misses 0 # ITB inst misses 361system.cpu.itb.read_hits 0 # DTB read hits 362system.cpu.itb.read_misses 0 # DTB read misses 363system.cpu.itb.write_hits 0 # DTB write hits 364system.cpu.itb.write_misses 0 # DTB write misses 365system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 366system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 367system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 368system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 369system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 370system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 371system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 372system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 373system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 374system.cpu.itb.read_accesses 0 # DTB read accesses 375system.cpu.itb.write_accesses 0 # DTB write accesses 376system.cpu.itb.inst_accesses 0 # ITB inst accesses 377system.cpu.itb.hits 0 # DTB hits 378system.cpu.itb.misses 0 # DTB misses 379system.cpu.itb.accesses 0 # DTB accesses 380system.cpu.workload.num_syscalls 46 # Number of system calls 381system.cpu.numCycles 1081392801 # number of cpu cycles simulated 382system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 383system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 384system.cpu.fetch.icacheStallCycles 300338229 # Number of cycles fetch is stalled on an Icache miss 385system.cpu.fetch.Insts 2194868023 # Number of instructions fetch has processed 386system.cpu.fetch.Branches 304230401 # Number of branches that fetch encountered 387system.cpu.fetch.predictedBranches 180045491 # Number of branches that fetch has predicted taken 388system.cpu.fetch.Cycles 436913465 # Number of cycles fetch has run and was not squashing or blocked 389system.cpu.fetch.SquashCycles 88946702 # Number of cycles fetch has spent squashing 390system.cpu.fetch.BlockedCycles 165329116 # Number of cycles fetch has spent blocked 391system.cpu.fetch.PendingTrapStallCycles 33 # Number of stall cycles due to pending traps 392system.cpu.fetch.CacheLines 290586210 # Number of cache lines fetched 393system.cpu.fetch.IcacheSquashes 6069176 # Number of outstanding Icache misses that were squashed 394system.cpu.fetch.rateDist::samples 973112936 # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::mean 2.494450 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::stdev 3.204820 # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::0 536199557 55.10% 55.10% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::1 25797166 2.65% 57.75% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::2 39079992 4.02% 61.77% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::3 48369850 4.97% 66.74% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::4 43937617 4.52% 71.25% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::5 46464611 4.77% 76.03% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::6 38405061 3.95% 79.98% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::7 19061800 1.96% 81.93% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::8 175797282 18.07% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::total 973112936 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.branchRate 0.281332 # Number of branch fetches per cycle 412system.cpu.fetch.rate 2.029668 # Number of inst fetches per cycle 413system.cpu.decode.IdleCycles 332624022 # Number of cycles decode is idle 414system.cpu.decode.BlockedCycles 143219561 # Number of cycles decode is blocked 415system.cpu.decode.RunCycles 406441589 # Number of cycles decode is running 416system.cpu.decode.UnblockCycles 20296480 # Number of cycles decode is unblocking 417system.cpu.decode.SquashCycles 70531284 # Number of cycles decode is squashing 418system.cpu.decode.BranchResolved 46039188 # Number of times decode resolved a branch 419system.cpu.decode.BranchMispred 865 # Number of times decode detected a branch misprediction 420system.cpu.decode.DecodedInsts 2374316328 # Number of instructions handled by decode 421system.cpu.decode.SquashedInsts 2545 # Number of squashed instructions handled by decode 422system.cpu.rename.SquashCycles 70531284 # Number of cycles rename is squashing 423system.cpu.rename.IdleCycles 356409274 # Number of cycles rename is idle 424system.cpu.rename.BlockCycles 71650111 # Number of cycles rename is blocking 425system.cpu.rename.serializeStallCycles 21139 # count of cycles rename stalled for serializing inst 426system.cpu.rename.RunCycles 401304268 # Number of cycles rename is running 427system.cpu.rename.UnblockCycles 73196860 # Number of cycles rename is unblocking 428system.cpu.rename.RenamedInsts 2310523412 # Number of instructions processed by rename 429system.cpu.rename.ROBFullEvents 156231 # Number of times rename has blocked due to ROB full 430system.cpu.rename.IQFullEvents 5060521 # Number of times rename has blocked due to IQ full 431system.cpu.rename.LSQFullEvents 60179356 # Number of times rename has blocked due to LSQ full 432system.cpu.rename.FullRegisterEvents 18 # Number of times there has been no free registers 433system.cpu.rename.RenamedOperands 2286636992 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 10669420338 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 10669417166 # Number of integer rename lookups 436system.cpu.rename.fp_rename_lookups 3172 # Number of floating rename lookups 437system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed 438system.cpu.rename.UndoneMaps 580317062 # Number of HB maps that are undone due to squashing 439system.cpu.rename.serializingInsts 904 # count of serializing insts renamed 440system.cpu.rename.tempSerializingInsts 901 # count of temporary serializing insts renamed 441system.cpu.rename.skidInsts 161063694 # count of insts added to the skid buffer 442system.cpu.memDep0.insertedLoads 625481573 # Number of loads inserted to the mem dependence unit. 443system.cpu.memDep0.insertedStores 221078320 # Number of stores inserted to the mem dependence unit. 444system.cpu.memDep0.conflictingLoads 85817344 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 70539912 # Number of conflicting stores. 446system.cpu.iq.iqInstsAdded 2205002740 # Number of instructions added to the IQ (excludes non-spec) 447system.cpu.iq.iqNonSpecInstsAdded 913 # Number of non-speculative instructions added to the IQ 448system.cpu.iq.iqInstsIssued 2019903116 # Number of instructions issued 449system.cpu.iq.iqSquashedInstsIssued 4041921 # Number of squashed instructions issued 450system.cpu.iq.iqSquashedInstsExamined 477338341 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 1137890497 # Number of squashed operands that are examined and possibly removed from graph 452system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed 453system.cpu.iq.issued_per_cycle::samples 973112936 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 2.075713 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 1.906230 # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::0 289817184 29.78% 29.78% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 153400597 15.76% 45.55% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 161373326 16.58% 62.13% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 120291643 12.36% 74.49% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::4 123812966 12.72% 87.21% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::5 73732869 7.58% 94.79% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 38377982 3.94% 98.74% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::7 9754115 1.00% 99.74% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 2552254 0.26% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::total 973112936 # Number of insts issued each cycle 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntAlu 873823 3.65% 3.65% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 5574 0.02% 3.68% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemRead 18262233 76.32% 80.00% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 4786578 20.00% 100.00% # attempts to use FU when none available 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 505system.cpu.iq.FU_type_0::IntAlu 1237523467 61.27% 61.27% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 925246 0.05% 61.31% # Type of FU issued 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.31% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.31% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.31% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.31% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.31% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.31% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.31% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.31% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.31% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.31% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.31% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.31% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.31% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.31% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 44 0.00% 61.31% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.31% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.31% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued 534system.cpu.iq.FU_type_0::MemRead 588384414 29.13% 90.44% # Type of FU issued 535system.cpu.iq.FU_type_0::MemWrite 193069911 9.56% 100.00% # Type of FU issued 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 538system.cpu.iq.FU_type_0::total 2019903116 # Type of FU issued 539system.cpu.iq.rate 1.867872 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 23928208 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.011846 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 5040888987 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 2682531512 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 1957653574 # Number of integer instruction queue wakeup accesses 545system.cpu.iq.fp_inst_queue_reads 310 # Number of floating instruction queue reads 546system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes 547system.cpu.iq.fp_inst_queue_wakeup_accesses 122 # Number of floating instruction queue wakeup accesses 548system.cpu.iq.int_alu_accesses 2043831169 # Number of integer alu accesses 549system.cpu.iq.fp_alu_accesses 155 # Number of floating point alu accesses 550system.cpu.iew.lsq.thread0.forwLoads 64629118 # Number of loads that had data forwarded from stores 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 552system.cpu.iew.lsq.thread0.squashedLoads 139554804 # Number of loads squashed 553system.cpu.iew.lsq.thread0.ignoredResponses 275861 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 192692 # Number of memory ordering violations 555system.cpu.iew.lsq.thread0.squashedStores 46231275 # Number of stores squashed 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 558system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 5362990 # Number of times an access to memory failed due to the cache being blocked 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 561system.cpu.iew.iewSquashCycles 70531284 # Number of cycles IEW is squashing 562system.cpu.iew.iewBlockCycles 34407025 # Number of cycles IEW is blocking 563system.cpu.iew.iewUnblockCycles 1609544 # Number of cycles IEW is unblocking 564system.cpu.iew.iewDispatchedInsts 2205003765 # Number of instructions dispatched to IQ 565system.cpu.iew.iewDispSquashedInsts 7646058 # Number of squashed instructions skipped by dispatch 566system.cpu.iew.iewDispLoadInsts 625481573 # Number of dispatched load instructions 567system.cpu.iew.iewDispStoreInsts 221078320 # Number of dispatched store instructions 568system.cpu.iew.iewDispNonSpecInsts 851 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 482587 # Number of times the IQ has become full, causing a stall 570system.cpu.iew.iewLSQFullEvents 96102 # Number of times the LSQ has become full, causing a stall 571system.cpu.iew.memOrderViolationEvents 192692 # Number of memory order violations 572system.cpu.iew.predictedTakenIncorrect 8138129 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 9602458 # Number of branches that were predicted not taken incorrectly 574system.cpu.iew.branchMispredicts 17740587 # Number of branch mispredicts detected at execute 575system.cpu.iew.iewExecutedInsts 1988966025 # Number of executed instructions 576system.cpu.iew.iewExecLoadInsts 574553789 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 30937091 # Number of squashed instructions skipped in execute 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 112 # number of nop insts executed 580system.cpu.iew.exec_refs 764737764 # number of memory reference insts executed 581system.cpu.iew.exec_branches 238303653 # Number of branches executed 582system.cpu.iew.exec_stores 190183975 # Number of stores executed 583system.cpu.iew.exec_rate 1.839263 # Inst execution rate 584system.cpu.iew.wb_sent 1966073864 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 1957653696 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 1295701173 # num instructions producing a value 587system.cpu.iew.wb_consumers 2059307469 # num instructions consuming a value 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 589system.cpu.iew.wb_rate 1.810308 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.629193 # average fanout of values written-back 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 592system.cpu.commit.commitSquashedInsts 482029293 # The number of squashed insts skipped by commit 593system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 594system.cpu.commit.branchMispredicts 15192188 # The number of times a branch was mispredicted 595system.cpu.commit.committed_per_cycle::samples 902581652 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 1.909050 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 2.715598 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::0 414112551 45.88% 45.88% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 193170118 21.40% 67.28% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 72777120 8.06% 75.35% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 35259342 3.91% 79.25% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 18942446 2.10% 81.35% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 30787152 3.41% 84.76% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 19991978 2.21% 86.98% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 11413503 1.26% 88.24% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 106127442 11.76% 100.00% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::total 902581652 # Number of insts commited each cycle 612system.cpu.commit.committedInsts 1544563041 # Number of instructions committed 613system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 660773814 # Number of memory references committed 616system.cpu.commit.loads 485926769 # Number of loads committed 617system.cpu.commit.membars 62 # Number of memory barriers committed 618system.cpu.commit.branches 213462426 # Number of branches committed 619system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 620system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. 621system.cpu.commit.function_calls 13665177 # Number of function calls committed. 622system.cpu.commit.bw_lim_events 106127442 # number cycles where commit BW limit reached 623system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 624system.cpu.rob.rob_reads 3001556757 # The number of ROB reads 625system.cpu.rob.rob_writes 4480884032 # The number of ROB writes 626system.cpu.timesIdled 1155619 # Number of times that the entire CPU went into an idle state and unscheduled itself 627system.cpu.idleCycles 108279865 # Total number of cycles that the CPU has spent unscheduled due to idling 628system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 629system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated 630system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated 631system.cpu.cpi 0.700129 # CPI: Cycles Per Instruction 632system.cpu.cpi_total 0.700129 # CPI: Total CPI of All Threads 633system.cpu.ipc 1.428309 # IPC: Instructions Per Cycle 634system.cpu.ipc_total 1.428309 # IPC: Total IPC of All Threads 635system.cpu.int_regfile_reads 9959942925 # number of integer regfile reads 636system.cpu.int_regfile_writes 1937523681 # number of integer regfile writes 637system.cpu.fp_regfile_reads 126 # number of floating regfile reads 638system.cpu.fp_regfile_writes 125 # number of floating regfile writes 639system.cpu.misc_regfile_reads 737562736 # number of misc regfile reads 640system.cpu.misc_regfile_writes 124 # number of misc regfile writes 641system.cpu.toL2Bus.throughput 1584099202 # Throughput (bytes/s) 642system.cpu.toL2Bus.trans_dist::ReadReq 7708436 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::ReadResp 7708436 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::Writeback 3781153 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::ReadExReq 1893485 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExResp 1893485 # Transaction distribution 647system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1562 # Packet count per connected master and slave (bytes) 648system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22983433 # Packet count per connected master and slave (bytes) 649system.cpu.toL2Bus.pkt_count 22984995 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 49984 # Cumulative packet size per connected master and slave (bytes) 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856466752 # Cumulative packet size per connected master and slave (bytes) 652system.cpu.toL2Bus.tot_pkt_size 856516736 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) 654system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 655system.cpu.toL2Bus.reqLayer0.occupancy 10472863577 # Layer occupancy (ticks) 656system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) 657system.cpu.toL2Bus.respLayer0.occupancy 1171999 # Layer occupancy (ticks) 658system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 659system.cpu.toL2Bus.respLayer1.occupancy 14401713992 # Layer occupancy (ticks) 660system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) 661system.cpu.icache.replacements 22 # number of replacements 662system.cpu.icache.tagsinuse 627.830229 # Cycle average of tags in use 663system.cpu.icache.total_refs 290585017 # Total number of references to valid blocks. 664system.cpu.icache.sampled_refs 781 # Sample count of references to valid blocks. 665system.cpu.icache.avg_refs 372067.883483 # Average number of references to valid blocks. 666system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 667system.cpu.icache.occ_blocks::cpu.inst 627.830229 # Average occupied blocks per requestor 668system.cpu.icache.occ_percent::cpu.inst 0.306558 # Average percentage of cache occupancy 669system.cpu.icache.occ_percent::total 0.306558 # Average percentage of cache occupancy 670system.cpu.icache.ReadReq_hits::cpu.inst 290585017 # number of ReadReq hits 671system.cpu.icache.ReadReq_hits::total 290585017 # number of ReadReq hits 672system.cpu.icache.demand_hits::cpu.inst 290585017 # number of demand (read+write) hits 673system.cpu.icache.demand_hits::total 290585017 # number of demand (read+write) hits 674system.cpu.icache.overall_hits::cpu.inst 290585017 # number of overall hits 675system.cpu.icache.overall_hits::total 290585017 # number of overall hits 676system.cpu.icache.ReadReq_misses::cpu.inst 1193 # number of ReadReq misses 677system.cpu.icache.ReadReq_misses::total 1193 # number of ReadReq misses 678system.cpu.icache.demand_misses::cpu.inst 1193 # number of demand (read+write) misses 679system.cpu.icache.demand_misses::total 1193 # number of demand (read+write) misses 680system.cpu.icache.overall_misses::cpu.inst 1193 # number of overall misses 681system.cpu.icache.overall_misses::total 1193 # number of overall misses 682system.cpu.icache.ReadReq_miss_latency::cpu.inst 86035500 # number of ReadReq miss cycles 683system.cpu.icache.ReadReq_miss_latency::total 86035500 # number of ReadReq miss cycles 684system.cpu.icache.demand_miss_latency::cpu.inst 86035500 # number of demand (read+write) miss cycles 685system.cpu.icache.demand_miss_latency::total 86035500 # number of demand (read+write) miss cycles 686system.cpu.icache.overall_miss_latency::cpu.inst 86035500 # number of overall miss cycles 687system.cpu.icache.overall_miss_latency::total 86035500 # number of overall miss cycles 688system.cpu.icache.ReadReq_accesses::cpu.inst 290586210 # number of ReadReq accesses(hits+misses) 689system.cpu.icache.ReadReq_accesses::total 290586210 # number of ReadReq accesses(hits+misses) 690system.cpu.icache.demand_accesses::cpu.inst 290586210 # number of demand (read+write) accesses 691system.cpu.icache.demand_accesses::total 290586210 # number of demand (read+write) accesses 692system.cpu.icache.overall_accesses::cpu.inst 290586210 # number of overall (read+write) accesses 693system.cpu.icache.overall_accesses::total 290586210 # number of overall (read+write) accesses 694system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 695system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 696system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 697system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 698system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 699system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 700system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72116.932104 # average ReadReq miss latency 701system.cpu.icache.ReadReq_avg_miss_latency::total 72116.932104 # average ReadReq miss latency 702system.cpu.icache.demand_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency 703system.cpu.icache.demand_avg_miss_latency::total 72116.932104 # average overall miss latency 704system.cpu.icache.overall_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency 705system.cpu.icache.overall_avg_miss_latency::total 72116.932104 # average overall miss latency 706system.cpu.icache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked 707system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 708system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked 709system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 710system.cpu.icache.avg_blocked_cycles::no_mshrs 49.750000 # average number of cycles each access was blocked 711system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu.icache.fast_writes 0 # number of fast writes performed 713system.cpu.icache.cache_copies 0 # number of cache copies performed 714system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits 715system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits 716system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits 717system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits 718system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits 719system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits 720system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses 721system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses 722system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses 723system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses 724system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses 725system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses 726system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59384001 # number of ReadReq MSHR miss cycles 727system.cpu.icache.ReadReq_mshr_miss_latency::total 59384001 # number of ReadReq MSHR miss cycles 728system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59384001 # number of demand (read+write) MSHR miss cycles 729system.cpu.icache.demand_mshr_miss_latency::total 59384001 # number of demand (read+write) MSHR miss cycles 730system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59384001 # number of overall MSHR miss cycles 731system.cpu.icache.overall_mshr_miss_latency::total 59384001 # number of overall MSHR miss cycles 732system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 733system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 734system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 735system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 736system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 737system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 738system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76035.852753 # average ReadReq mshr miss latency 739system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76035.852753 # average ReadReq mshr miss latency 740system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76035.852753 # average overall mshr miss latency 741system.cpu.icache.demand_avg_mshr_miss_latency::total 76035.852753 # average overall mshr miss latency 742system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76035.852753 # average overall mshr miss latency 743system.cpu.icache.overall_avg_mshr_miss_latency::total 76035.852753 # average overall mshr miss latency 744system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 745system.cpu.l2cache.replacements 2214008 # number of replacements 746system.cpu.l2cache.tagsinuse 31545.875472 # Cycle average of tags in use 747system.cpu.l2cache.total_refs 9245067 # Total number of references to valid blocks. 748system.cpu.l2cache.sampled_refs 2243786 # Sample count of references to valid blocks. 749system.cpu.l2cache.avg_refs 4.120298 # Average number of references to valid blocks. 750system.cpu.l2cache.warmup_cycle 21328593250 # Cycle when the warmup percentage was hit. 751system.cpu.l2cache.occ_blocks::writebacks 14315.671297 # Average occupied blocks per requestor 752system.cpu.l2cache.occ_blocks::cpu.inst 19.864874 # Average occupied blocks per requestor 753system.cpu.l2cache.occ_blocks::cpu.data 17210.339300 # Average occupied blocks per requestor 754system.cpu.l2cache.occ_percent::writebacks 0.436880 # Average percentage of cache occupancy 755system.cpu.l2cache.occ_percent::cpu.inst 0.000606 # Average percentage of cache occupancy 756system.cpu.l2cache.occ_percent::cpu.data 0.525218 # Average percentage of cache occupancy 757system.cpu.l2cache.occ_percent::total 0.962704 # Average percentage of cache occupancy 758system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits 759system.cpu.l2cache.ReadReq_hits::cpu.data 6288185 # number of ReadReq hits 760system.cpu.l2cache.ReadReq_hits::total 6288213 # number of ReadReq hits 761system.cpu.l2cache.Writeback_hits::writebacks 3781153 # number of Writeback hits 762system.cpu.l2cache.Writeback_hits::total 3781153 # number of Writeback hits 763system.cpu.l2cache.ReadExReq_hits::cpu.data 1067000 # number of ReadExReq hits 764system.cpu.l2cache.ReadExReq_hits::total 1067000 # number of ReadExReq hits 765system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits 766system.cpu.l2cache.demand_hits::cpu.data 7355185 # number of demand (read+write) hits 767system.cpu.l2cache.demand_hits::total 7355213 # number of demand (read+write) hits 768system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits 769system.cpu.l2cache.overall_hits::cpu.data 7355185 # number of overall hits 770system.cpu.l2cache.overall_hits::total 7355213 # number of overall hits 771system.cpu.l2cache.ReadReq_misses::cpu.inst 753 # number of ReadReq misses 772system.cpu.l2cache.ReadReq_misses::cpu.data 1419470 # number of ReadReq misses 773system.cpu.l2cache.ReadReq_misses::total 1420223 # number of ReadReq misses 774system.cpu.l2cache.ReadExReq_misses::cpu.data 826485 # number of ReadExReq misses 775system.cpu.l2cache.ReadExReq_misses::total 826485 # number of ReadExReq misses 776system.cpu.l2cache.demand_misses::cpu.inst 753 # number of demand (read+write) misses 777system.cpu.l2cache.demand_misses::cpu.data 2245955 # number of demand (read+write) misses 778system.cpu.l2cache.demand_misses::total 2246708 # number of demand (read+write) misses 779system.cpu.l2cache.overall_misses::cpu.inst 753 # number of overall misses 780system.cpu.l2cache.overall_misses::cpu.data 2245955 # number of overall misses 781system.cpu.l2cache.overall_misses::total 2246708 # number of overall misses 782system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58316000 # number of ReadReq miss cycles 783system.cpu.l2cache.ReadReq_miss_latency::cpu.data 138202856500 # number of ReadReq miss cycles 784system.cpu.l2cache.ReadReq_miss_latency::total 138261172500 # number of ReadReq miss cycles 785system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84038252500 # number of ReadExReq miss cycles 786system.cpu.l2cache.ReadExReq_miss_latency::total 84038252500 # number of ReadExReq miss cycles 787system.cpu.l2cache.demand_miss_latency::cpu.inst 58316000 # number of demand (read+write) miss cycles 788system.cpu.l2cache.demand_miss_latency::cpu.data 222241109000 # number of demand (read+write) miss cycles 789system.cpu.l2cache.demand_miss_latency::total 222299425000 # number of demand (read+write) miss cycles 790system.cpu.l2cache.overall_miss_latency::cpu.inst 58316000 # number of overall miss cycles 791system.cpu.l2cache.overall_miss_latency::cpu.data 222241109000 # number of overall miss cycles 792system.cpu.l2cache.overall_miss_latency::total 222299425000 # number of overall miss cycles 793system.cpu.l2cache.ReadReq_accesses::cpu.inst 781 # number of ReadReq accesses(hits+misses) 794system.cpu.l2cache.ReadReq_accesses::cpu.data 7707655 # number of ReadReq accesses(hits+misses) 795system.cpu.l2cache.ReadReq_accesses::total 7708436 # number of ReadReq accesses(hits+misses) 796system.cpu.l2cache.Writeback_accesses::writebacks 3781153 # number of Writeback accesses(hits+misses) 797system.cpu.l2cache.Writeback_accesses::total 3781153 # number of Writeback accesses(hits+misses) 798system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893485 # number of ReadExReq accesses(hits+misses) 799system.cpu.l2cache.ReadExReq_accesses::total 1893485 # number of ReadExReq accesses(hits+misses) 800system.cpu.l2cache.demand_accesses::cpu.inst 781 # number of demand (read+write) accesses 801system.cpu.l2cache.demand_accesses::cpu.data 9601140 # number of demand (read+write) accesses 802system.cpu.l2cache.demand_accesses::total 9601921 # number of demand (read+write) accesses 803system.cpu.l2cache.overall_accesses::cpu.inst 781 # number of overall (read+write) accesses 804system.cpu.l2cache.overall_accesses::cpu.data 9601140 # number of overall (read+write) accesses 805system.cpu.l2cache.overall_accesses::total 9601921 # number of overall (read+write) accesses 806system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964149 # miss rate for ReadReq accesses 807system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184164 # miss rate for ReadReq accesses 808system.cpu.l2cache.ReadReq_miss_rate::total 0.184243 # miss rate for ReadReq accesses 809system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436489 # miss rate for ReadExReq accesses 810system.cpu.l2cache.ReadExReq_miss_rate::total 0.436489 # miss rate for ReadExReq accesses 811system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964149 # miss rate for demand accesses 812system.cpu.l2cache.demand_miss_rate::cpu.data 0.233926 # miss rate for demand accesses 813system.cpu.l2cache.demand_miss_rate::total 0.233985 # miss rate for demand accesses 814system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964149 # miss rate for overall accesses 815system.cpu.l2cache.overall_miss_rate::cpu.data 0.233926 # miss rate for overall accesses 816system.cpu.l2cache.overall_miss_rate::total 0.233985 # miss rate for overall accesses 817system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77444.887118 # average ReadReq miss latency 818system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97362.294730 # average ReadReq miss latency 819system.cpu.l2cache.ReadReq_avg_miss_latency::total 97351.734552 # average ReadReq miss latency 820system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101681.521746 # average ReadExReq miss latency 821system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101681.521746 # average ReadExReq miss latency 822system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77444.887118 # average overall miss latency 823system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98951.719424 # average overall miss latency 824system.cpu.l2cache.demand_avg_miss_latency::total 98944.511258 # average overall miss latency 825system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77444.887118 # average overall miss latency 826system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98951.719424 # average overall miss latency 827system.cpu.l2cache.overall_avg_miss_latency::total 98944.511258 # average overall miss latency 828system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 829system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 830system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 831system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 832system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 833system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 834system.cpu.l2cache.fast_writes 0 # number of fast writes performed 835system.cpu.l2cache.cache_copies 0 # number of cache copies performed 836system.cpu.l2cache.writebacks::writebacks 1100650 # number of writebacks 837system.cpu.l2cache.writebacks::total 1100650 # number of writebacks 838system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 839system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits 840system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 841system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 842system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits 843system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 844system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 845system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits 846system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits 847system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 752 # number of ReadReq MSHR misses 848system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419462 # number of ReadReq MSHR misses 849system.cpu.l2cache.ReadReq_mshr_misses::total 1420214 # number of ReadReq MSHR misses 850system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826485 # number of ReadExReq MSHR misses 851system.cpu.l2cache.ReadExReq_mshr_misses::total 826485 # number of ReadExReq MSHR misses 852system.cpu.l2cache.demand_mshr_misses::cpu.inst 752 # number of demand (read+write) MSHR misses 853system.cpu.l2cache.demand_mshr_misses::cpu.data 2245947 # number of demand (read+write) MSHR misses 854system.cpu.l2cache.demand_mshr_misses::total 2246699 # number of demand (read+write) MSHR misses 855system.cpu.l2cache.overall_mshr_misses::cpu.inst 752 # number of overall MSHR misses 856system.cpu.l2cache.overall_mshr_misses::cpu.data 2245947 # number of overall MSHR misses 857system.cpu.l2cache.overall_mshr_misses::total 2246699 # number of overall MSHR misses 858system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48914000 # number of ReadReq MSHR miss cycles 859system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 120590551250 # number of ReadReq MSHR miss cycles 860system.cpu.l2cache.ReadReq_mshr_miss_latency::total 120639465250 # number of ReadReq MSHR miss cycles 861system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 73785244750 # number of ReadExReq MSHR miss cycles 862system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 73785244750 # number of ReadExReq MSHR miss cycles 863system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48914000 # number of demand (read+write) MSHR miss cycles 864system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 194375796000 # number of demand (read+write) MSHR miss cycles 865system.cpu.l2cache.demand_mshr_miss_latency::total 194424710000 # number of demand (read+write) MSHR miss cycles 866system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48914000 # number of overall MSHR miss cycles 867system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 194375796000 # number of overall MSHR miss cycles 868system.cpu.l2cache.overall_mshr_miss_latency::total 194424710000 # number of overall MSHR miss cycles 869system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for ReadReq accesses 870system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184163 # mshr miss rate for ReadReq accesses 871system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184242 # mshr miss rate for ReadReq accesses 872system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436489 # mshr miss rate for ReadExReq accesses 873system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436489 # mshr miss rate for ReadExReq accesses 874system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for demand accesses 875system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233925 # mshr miss rate for demand accesses 876system.cpu.l2cache.demand_mshr_miss_rate::total 0.233984 # mshr miss rate for demand accesses 877system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962868 # mshr miss rate for overall accesses 878system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233925 # mshr miss rate for overall accesses 879system.cpu.l2cache.overall_mshr_miss_rate::total 0.233984 # mshr miss rate for overall accesses 880system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65045.212766 # average ReadReq mshr miss latency 881system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 84955.110633 # average ReadReq mshr miss latency 882system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 84944.568389 # average ReadReq mshr miss latency 883system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89275.963569 # average ReadExReq mshr miss latency 884system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89275.963569 # average ReadExReq mshr miss latency 885system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65045.212766 # average overall mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86545.139311 # average overall mshr miss latency 887system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86537.943000 # average overall mshr miss latency 888system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65045.212766 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86545.139311 # average overall mshr miss latency 890system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86537.943000 # average overall mshr miss latency 891system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 892system.cpu.dcache.replacements 9597044 # number of replacements 893system.cpu.dcache.tagsinuse 4088.193523 # Cycle average of tags in use 894system.cpu.dcache.total_refs 655932792 # Total number of references to valid blocks. 895system.cpu.dcache.sampled_refs 9601140 # Sample count of references to valid blocks. 896system.cpu.dcache.avg_refs 68.318220 # Average number of references to valid blocks. 897system.cpu.dcache.warmup_cycle 3513476000 # Cycle when the warmup percentage was hit. 898system.cpu.dcache.occ_blocks::cpu.data 4088.193523 # Average occupied blocks per requestor 899system.cpu.dcache.occ_percent::cpu.data 0.998094 # Average percentage of cache occupancy 900system.cpu.dcache.occ_percent::total 0.998094 # Average percentage of cache occupancy 901system.cpu.dcache.ReadReq_hits::cpu.data 488973029 # number of ReadReq hits 902system.cpu.dcache.ReadReq_hits::total 488973029 # number of ReadReq hits 903system.cpu.dcache.WriteReq_hits::cpu.data 166959638 # number of WriteReq hits 904system.cpu.dcache.WriteReq_hits::total 166959638 # number of WriteReq hits 905system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits 906system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits 907system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 908system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 909system.cpu.dcache.demand_hits::cpu.data 655932667 # number of demand (read+write) hits 910system.cpu.dcache.demand_hits::total 655932667 # number of demand (read+write) hits 911system.cpu.dcache.overall_hits::cpu.data 655932667 # number of overall hits 912system.cpu.dcache.overall_hits::total 655932667 # number of overall hits 913system.cpu.dcache.ReadReq_misses::cpu.data 11505709 # number of ReadReq misses 914system.cpu.dcache.ReadReq_misses::total 11505709 # number of ReadReq misses 915system.cpu.dcache.WriteReq_misses::cpu.data 5626409 # number of WriteReq misses 916system.cpu.dcache.WriteReq_misses::total 5626409 # number of WriteReq misses 917system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 918system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 919system.cpu.dcache.demand_misses::cpu.data 17132118 # number of demand (read+write) misses 920system.cpu.dcache.demand_misses::total 17132118 # number of demand (read+write) misses 921system.cpu.dcache.overall_misses::cpu.data 17132118 # number of overall misses 922system.cpu.dcache.overall_misses::total 17132118 # number of overall misses 923system.cpu.dcache.ReadReq_miss_latency::cpu.data 379498751500 # number of ReadReq miss cycles 924system.cpu.dcache.ReadReq_miss_latency::total 379498751500 # number of ReadReq miss cycles 925system.cpu.dcache.WriteReq_miss_latency::cpu.data 307395824029 # number of WriteReq miss cycles 926system.cpu.dcache.WriteReq_miss_latency::total 307395824029 # number of WriteReq miss cycles 927system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 651000 # number of LoadLockedReq miss cycles 928system.cpu.dcache.LoadLockedReq_miss_latency::total 651000 # number of LoadLockedReq miss cycles 929system.cpu.dcache.demand_miss_latency::cpu.data 686894575529 # number of demand (read+write) miss cycles 930system.cpu.dcache.demand_miss_latency::total 686894575529 # number of demand (read+write) miss cycles 931system.cpu.dcache.overall_miss_latency::cpu.data 686894575529 # number of overall miss cycles 932system.cpu.dcache.overall_miss_latency::total 686894575529 # number of overall miss cycles 933system.cpu.dcache.ReadReq_accesses::cpu.data 500478738 # number of ReadReq accesses(hits+misses) 934system.cpu.dcache.ReadReq_accesses::total 500478738 # number of ReadReq accesses(hits+misses) 935system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 936system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 937system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) 938system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) 939system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 940system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 941system.cpu.dcache.demand_accesses::cpu.data 673064785 # number of demand (read+write) accesses 942system.cpu.dcache.demand_accesses::total 673064785 # number of demand (read+write) accesses 943system.cpu.dcache.overall_accesses::cpu.data 673064785 # number of overall (read+write) accesses 944system.cpu.dcache.overall_accesses::total 673064785 # number of overall (read+write) accesses 945system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses 946system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses 947system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032601 # miss rate for WriteReq accesses 948system.cpu.dcache.WriteReq_miss_rate::total 0.032601 # miss rate for WriteReq accesses 949system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses 950system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses 951system.cpu.dcache.demand_miss_rate::cpu.data 0.025454 # miss rate for demand accesses 952system.cpu.dcache.demand_miss_rate::total 0.025454 # miss rate for demand accesses 953system.cpu.dcache.overall_miss_rate::cpu.data 0.025454 # miss rate for overall accesses 954system.cpu.dcache.overall_miss_rate::total 0.025454 # miss rate for overall accesses 955system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32983.517270 # average ReadReq miss latency 956system.cpu.dcache.ReadReq_avg_miss_latency::total 32983.517270 # average ReadReq miss latency 957system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54634.461169 # average WriteReq miss latency 958system.cpu.dcache.WriteReq_avg_miss_latency::total 54634.461169 # average WriteReq miss latency 959system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 217000 # average LoadLockedReq miss latency 960system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 217000 # average LoadLockedReq miss latency 961system.cpu.dcache.demand_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency 962system.cpu.dcache.demand_avg_miss_latency::total 40093.967105 # average overall miss latency 963system.cpu.dcache.overall_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency 964system.cpu.dcache.overall_avg_miss_latency::total 40093.967105 # average overall miss latency 965system.cpu.dcache.blocked_cycles::no_mshrs 29400681 # number of cycles access was blocked 966system.cpu.dcache.blocked_cycles::no_targets 3494014 # number of cycles access was blocked 967system.cpu.dcache.blocked::no_mshrs 1217576 # number of cycles access was blocked 968system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked 969system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.146896 # average number of cycles each access was blocked 970system.cpu.dcache.avg_blocked_cycles::no_targets 53.645121 # average number of cycles each access was blocked 971system.cpu.dcache.fast_writes 0 # number of fast writes performed 972system.cpu.dcache.cache_copies 0 # number of cache copies performed 973system.cpu.dcache.writebacks::writebacks 3781153 # number of writebacks 974system.cpu.dcache.writebacks::total 3781153 # number of writebacks 975system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798054 # number of ReadReq MSHR hits 976system.cpu.dcache.ReadReq_mshr_hits::total 3798054 # number of ReadReq MSHR hits 977system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732924 # number of WriteReq MSHR hits 978system.cpu.dcache.WriteReq_mshr_hits::total 3732924 # number of WriteReq MSHR hits 979system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 980system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 981system.cpu.dcache.demand_mshr_hits::cpu.data 7530978 # number of demand (read+write) MSHR hits 982system.cpu.dcache.demand_mshr_hits::total 7530978 # number of demand (read+write) MSHR hits 983system.cpu.dcache.overall_mshr_hits::cpu.data 7530978 # number of overall MSHR hits 984system.cpu.dcache.overall_mshr_hits::total 7530978 # number of overall MSHR hits 985system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707655 # number of ReadReq MSHR misses 986system.cpu.dcache.ReadReq_mshr_misses::total 7707655 # number of ReadReq MSHR misses 987system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893485 # number of WriteReq MSHR misses 988system.cpu.dcache.WriteReq_mshr_misses::total 1893485 # number of WriteReq MSHR misses 989system.cpu.dcache.demand_mshr_misses::cpu.data 9601140 # number of demand (read+write) MSHR misses 990system.cpu.dcache.demand_mshr_misses::total 9601140 # number of demand (read+write) MSHR misses 991system.cpu.dcache.overall_mshr_misses::cpu.data 9601140 # number of overall MSHR misses 992system.cpu.dcache.overall_mshr_misses::total 9601140 # number of overall MSHR misses 993system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210632290508 # number of ReadReq MSHR miss cycles 994system.cpu.dcache.ReadReq_mshr_miss_latency::total 210632290508 # number of ReadReq MSHR miss cycles 995system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97135590826 # number of WriteReq MSHR miss cycles 996system.cpu.dcache.WriteReq_mshr_miss_latency::total 97135590826 # number of WriteReq MSHR miss cycles 997system.cpu.dcache.demand_mshr_miss_latency::cpu.data 307767881334 # number of demand (read+write) MSHR miss cycles 998system.cpu.dcache.demand_mshr_miss_latency::total 307767881334 # number of demand (read+write) MSHR miss cycles 999system.cpu.dcache.overall_mshr_miss_latency::cpu.data 307767881334 # number of overall MSHR miss cycles 1000system.cpu.dcache.overall_mshr_miss_latency::total 307767881334 # number of overall MSHR miss cycles 1001system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses 1002system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses 1003system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses 1004system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses 1005system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses 1006system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses 1007system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses 1008system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses 1009system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27327.674955 # average ReadReq mshr miss latency 1010system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27327.674955 # average ReadReq mshr miss latency 1011system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51299.899828 # average WriteReq mshr miss latency 1012system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51299.899828 # average WriteReq mshr miss latency 1013system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency 1014system.cpu.dcache.demand_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency 1015system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency 1016system.cpu.dcache.overall_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency 1017system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1018 1019---------- End Simulation Statistics ---------- 1020