stats.txt revision 9481:b0fa6b872f40
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.506354 # Number of seconds simulated 4sim_ticks 506353996500 # Number of ticks simulated 5final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 105319 # Simulator instruction rate (inst/s) 8host_op_rate 117491 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34526611 # Simulator tick rate (ticks/s) 10host_mem_usage 552892 # Number of bytes of host memory used 11host_seconds 14665.62 # Real time elapsed on the host 12sim_insts 1544563023 # Number of instructions simulated 13sim_ops 1723073835 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 143771904 # Number of bytes read from this memory 16system.physmem.bytes_read::total 143819904 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 48000 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 48000 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 70451968 # Number of bytes written to this memory 20system.physmem.bytes_written::total 70451968 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 750 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2246436 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2247186 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1100812 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1100812 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 94795 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 283935557 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 284030352 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 94795 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 94795 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 139135799 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 139135799 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 139135799 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 94795 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 283935557 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 423166152 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 2247186 # Total number of read requests seen 38system.physmem.writeReqs 1100812 # Total number of write requests seen 39system.physmem.cpureqs 3347998 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 143819904 # Total number of bytes read from memory 41system.physmem.bytesWritten 70451968 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 143819904 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 70451968 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 672 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 139825 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 143804 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 141798 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 141106 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 137923 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 140335 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 141438 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 140855 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 141349 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 139500 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 140412 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 140930 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 137255 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 141125 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 138862 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 139997 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 69198 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 70413 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 69591 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 68873 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 67768 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 68429 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 68697 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 68477 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 68286 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 68308 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 68629 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 68528 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 67273 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 70384 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 69023 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 68935 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 506353933500 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 2247186 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 1100812 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 1577555 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 446581 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 156376 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 65982 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 45520 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 47517 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 47811 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 47856 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 47861 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 47862 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 47862 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 47862 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 47862 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 47861 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 47861 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 47861 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 47861 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 47861 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 47861 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 47861 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 47861 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 47861 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 47861 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 47861 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 47861 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 47861 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 47861 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 2342 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 345 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 27009597750 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 102747541750 # Sum of mem lat for all requests 176system.physmem.totBusLat 8986056000 # Total cycles spent in databus access 177system.physmem.totBankLat 66751888000 # Total cycles spent in bank access 178system.physmem.avgQLat 12022.89 # Average queueing delay per request 179system.physmem.avgBankLat 29713.54 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 45736.44 # Average memory access latency 182system.physmem.avgRdBW 284.03 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 139.14 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 284.03 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 139.14 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 2.64 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.20 # Average read queue length over time 189system.physmem.avgWrQLen 11.52 # Average write queue length over time 190system.physmem.readRowHits 914505 # Number of row buffer hits during reads 191system.physmem.writeRowHits 189005 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes 194system.physmem.avgGap 151240.81 # Average gap between requests 195system.cpu.branchPred.lookups 301930111 # Number of BP lookups 196system.cpu.branchPred.condPredicted 248173247 # Number of conditional branches predicted 197system.cpu.branchPred.condIncorrect 15201095 # Number of conditional branches incorrect 198system.cpu.branchPred.BTBLookups 171785530 # Number of BTB lookups 199system.cpu.branchPred.BTBHits 160276899 # Number of BTB hits 200system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 201system.cpu.branchPred.BTBHitPct 93.300582 # BTB Hit Percentage 202system.cpu.branchPred.usedRAS 17551988 # Number of times the RAS was used to get a target. 203system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions. 204system.cpu.dtb.inst_hits 0 # ITB inst hits 205system.cpu.dtb.inst_misses 0 # ITB inst misses 206system.cpu.dtb.read_hits 0 # DTB read hits 207system.cpu.dtb.read_misses 0 # DTB read misses 208system.cpu.dtb.write_hits 0 # DTB write hits 209system.cpu.dtb.write_misses 0 # DTB write misses 210system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 211system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 212system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 213system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 214system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 215system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 216system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 217system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 218system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 219system.cpu.dtb.read_accesses 0 # DTB read accesses 220system.cpu.dtb.write_accesses 0 # DTB write accesses 221system.cpu.dtb.inst_accesses 0 # ITB inst accesses 222system.cpu.dtb.hits 0 # DTB hits 223system.cpu.dtb.misses 0 # DTB misses 224system.cpu.dtb.accesses 0 # DTB accesses 225system.cpu.itb.inst_hits 0 # ITB inst hits 226system.cpu.itb.inst_misses 0 # ITB inst misses 227system.cpu.itb.read_hits 0 # DTB read hits 228system.cpu.itb.read_misses 0 # DTB read misses 229system.cpu.itb.write_hits 0 # DTB write hits 230system.cpu.itb.write_misses 0 # DTB write misses 231system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 232system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 233system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 234system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 235system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 236system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 237system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 238system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 239system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 240system.cpu.itb.read_accesses 0 # DTB read accesses 241system.cpu.itb.write_accesses 0 # DTB write accesses 242system.cpu.itb.inst_accesses 0 # ITB inst accesses 243system.cpu.itb.hits 0 # DTB hits 244system.cpu.itb.misses 0 # DTB misses 245system.cpu.itb.accesses 0 # DTB accesses 246system.cpu.workload.num_syscalls 46 # Number of system calls 247system.cpu.numCycles 1012707994 # number of cpu cycles simulated 248system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 249system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 250system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss 251system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed 252system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered 253system.cpu.fetch.predictedBranches 177828887 # Number of branches that fetch has predicted taken 254system.cpu.fetch.Cycles 433076308 # Number of cycles fetch has run and was not squashing or blocked 255system.cpu.fetch.SquashCycles 86433742 # Number of cycles fetch has spent squashing 256system.cpu.fetch.BlockedCycles 153009166 # Number of cycles fetch has spent blocked 257system.cpu.fetch.PendingTrapStallCycles 127 # Number of stall cycles due to pending traps 258system.cpu.fetch.CacheLines 286734480 # Number of cache lines fetched 259system.cpu.fetch.IcacheSquashes 5522368 # Number of outstanding Icache misses that were squashed 260system.cpu.fetch.rateDist::samples 951217236 # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::mean 2.532975 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::stdev 3.216056 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::0 518141000 54.47% 54.47% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::1 25031243 2.63% 57.10% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::2 39020791 4.10% 61.21% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::3 48260411 5.07% 66.28% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::4 42551008 4.47% 70.75% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::5 46329866 4.87% 75.62% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::6 38408585 4.04% 79.66% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::7 18543654 1.95% 81.61% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::8 174930678 18.39% 100.00% # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::total 951217236 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.branchRate 0.298141 # Number of branch fetches per cycle 278system.cpu.fetch.rate 2.149522 # Number of inst fetches per cycle 279system.cpu.decode.IdleCycles 327471231 # Number of cycles decode is idle 280system.cpu.decode.BlockedCycles 131306156 # Number of cycles decode is blocked 281system.cpu.decode.RunCycles 403441377 # Number of cycles decode is running 282system.cpu.decode.UnblockCycles 20045518 # Number of cycles decode is unblocking 283system.cpu.decode.SquashCycles 68952954 # Number of cycles decode is squashing 284system.cpu.decode.BranchResolved 46012127 # Number of times decode resolved a branch 285system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction 286system.cpu.decode.DecodedInsts 2358019040 # Number of instructions handled by decode 287system.cpu.decode.SquashedInsts 2460 # Number of squashed instructions handled by decode 288system.cpu.rename.SquashCycles 68952954 # Number of cycles rename is squashing 289system.cpu.rename.IdleCycles 350612417 # Number of cycles rename is idle 290system.cpu.rename.BlockCycles 61250936 # Number of cycles rename is blocking 291system.cpu.rename.serializeStallCycles 16584 # count of cycles rename stalled for serializing inst 292system.cpu.rename.RunCycles 398830274 # Number of cycles rename is running 293system.cpu.rename.UnblockCycles 71554071 # Number of cycles rename is unblocking 294system.cpu.rename.RenamedInsts 2297211554 # Number of instructions processed by rename 295system.cpu.rename.ROBFullEvents 127534 # Number of times rename has blocked due to ROB full 296system.cpu.rename.IQFullEvents 5036199 # Number of times rename has blocked due to IQ full 297system.cpu.rename.LSQFullEvents 58405264 # Number of times rename has blocked due to LSQ full 298system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers 299system.cpu.rename.RenamedOperands 2272168650 # Number of destination operands rename has renamed 300system.cpu.rename.RenameLookups 10608574023 # Number of register rename lookups that rename has made 301system.cpu.rename.int_rename_lookups 10608571065 # Number of integer rename lookups 302system.cpu.rename.fp_rename_lookups 2958 # Number of floating rename lookups 303system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed 304system.cpu.rename.UndoneMaps 565848720 # Number of HB maps that are undone due to squashing 305system.cpu.rename.serializingInsts 855 # count of serializing insts renamed 306system.cpu.rename.tempSerializingInsts 852 # count of temporary serializing insts renamed 307system.cpu.rename.skidInsts 158388501 # count of insts added to the skid buffer 308system.cpu.memDep0.insertedLoads 623121269 # Number of loads inserted to the mem dependence unit. 309system.cpu.memDep0.insertedStores 220470896 # Number of stores inserted to the mem dependence unit. 310system.cpu.memDep0.conflictingLoads 86042540 # Number of conflicting loads. 311system.cpu.memDep0.conflictingStores 70771050 # Number of conflicting stores. 312system.cpu.iq.iqInstsAdded 2196546407 # Number of instructions added to the IQ (excludes non-spec) 313system.cpu.iq.iqNonSpecInstsAdded 888 # Number of non-speculative instructions added to the IQ 314system.cpu.iq.iqInstsIssued 2016009796 # Number of instructions issued 315system.cpu.iq.iqSquashedInstsIssued 3969588 # Number of squashed instructions issued 316system.cpu.iq.iqSquashedInstsExamined 468927262 # Number of squashed instructions iterated over during squash; mainly for profiling 317system.cpu.iq.iqSquashedOperandsExamined 1107841980 # Number of squashed operands that are examined and possibly removed from graph 318system.cpu.iq.iqSquashedNonSpecRemoved 718 # Number of squashed non-spec instructions that were removed 319system.cpu.iq.issued_per_cycle::samples 951217236 # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::mean 2.119400 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::stdev 1.906359 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::0 271448438 28.54% 28.54% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::1 150881497 15.86% 44.40% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::2 160823100 16.91% 61.31% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::3 119315575 12.54% 73.85% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::4 124031902 13.04% 86.89% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::5 73881034 7.77% 94.66% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::6 38429694 4.04% 98.70% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::7 9823536 1.03% 99.73% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::8 2582460 0.27% 100.00% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::total 951217236 # Number of insts issued each cycle 336system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 337system.cpu.iq.fu_full::IntAlu 875964 3.67% 3.67% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntMult 5764 0.02% 3.70% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntDiv 0 0.00% 3.70% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.70% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.70% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.70% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatMult 0 0.00% 3.70% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.70% # attempts to use FU when none available 345system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.70% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.70% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.70% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.70% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.70% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.70% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.70% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdMult 0 0.00% 3.70% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.70% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdShift 0 0.00% 3.70% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.70% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.70% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.70% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.70% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.70% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.70% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.70% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.70% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.70% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.70% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.70% # attempts to use FU when none available 366system.cpu.iq.fu_full::MemRead 18242361 76.45% 80.15% # attempts to use FU when none available 367system.cpu.iq.fu_full::MemWrite 4736544 19.85% 100.00% # attempts to use FU when none available 368system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 369system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 370system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 371system.cpu.iq.FU_type_0::IntAlu 1235492979 61.28% 61.28% # Type of FU issued 372system.cpu.iq.FU_type_0::IntMult 925544 0.05% 61.33% # Type of FU issued 373system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatCvt 40 0.00% 61.33% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.33% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.33% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued 400system.cpu.iq.FU_type_0::MemRead 586540633 29.09% 90.42% # Type of FU issued 401system.cpu.iq.FU_type_0::MemWrite 193050569 9.58% 100.00% # Type of FU issued 402system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 403system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 404system.cpu.iq.FU_type_0::total 2016009796 # Type of FU issued 405system.cpu.iq.rate 1.990712 # Inst issue rate 406system.cpu.iq.fu_busy_cnt 23860633 # FU busy when requested 407system.cpu.iq.fu_busy_rate 0.011836 # FU busy rate (busy events/executed inst) 408system.cpu.iq.int_inst_queue_reads 5011066759 # Number of integer instruction queue reads 409system.cpu.iq.int_inst_queue_writes 2665664471 # Number of integer instruction queue writes 410system.cpu.iq.int_inst_queue_wakeup_accesses 1956606463 # Number of integer instruction queue wakeup accesses 411system.cpu.iq.fp_inst_queue_reads 290 # Number of floating instruction queue reads 412system.cpu.iq.fp_inst_queue_writes 554 # Number of floating instruction queue writes 413system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses 414system.cpu.iq.int_alu_accesses 2039870285 # Number of integer alu accesses 415system.cpu.iq.fp_alu_accesses 144 # Number of floating point alu accesses 416system.cpu.iew.lsq.thread0.forwLoads 64705720 # Number of loads that had data forwarded from stores 417system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 418system.cpu.iew.lsq.thread0.squashedLoads 137194500 # Number of loads squashed 419system.cpu.iew.lsq.thread0.ignoredResponses 273797 # Number of memory responses ignored because the instruction is squashed 420system.cpu.iew.lsq.thread0.memOrderViolation 192943 # Number of memory ordering violations 421system.cpu.iew.lsq.thread0.squashedStores 45623851 # Number of stores squashed 422system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 423system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 424system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled 425system.cpu.iew.lsq.thread0.cacheBlocked 3807412 # Number of times an access to memory failed due to the cache being blocked 426system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 427system.cpu.iew.iewSquashCycles 68952954 # Number of cycles IEW is squashing 428system.cpu.iew.iewBlockCycles 27155997 # Number of cycles IEW is blocking 429system.cpu.iew.iewUnblockCycles 1495704 # Number of cycles IEW is unblocking 430system.cpu.iew.iewDispatchedInsts 2196547422 # Number of instructions dispatched to IQ 431system.cpu.iew.iewDispSquashedInsts 6100181 # Number of squashed instructions skipped by dispatch 432system.cpu.iew.iewDispLoadInsts 623121269 # Number of dispatched load instructions 433system.cpu.iew.iewDispStoreInsts 220470896 # Number of dispatched store instructions 434system.cpu.iew.iewDispNonSpecInsts 826 # Number of dispatched non-speculative instructions 435system.cpu.iew.iewIQFullEvents 473871 # Number of times the IQ has become full, causing a stall 436system.cpu.iew.iewLSQFullEvents 90052 # Number of times the LSQ has become full, causing a stall 437system.cpu.iew.memOrderViolationEvents 192943 # Number of memory order violations 438system.cpu.iew.predictedTakenIncorrect 8142096 # Number of branches that were predicted taken incorrectly 439system.cpu.iew.predictedNotTakenIncorrect 9608050 # Number of branches that were predicted not taken incorrectly 440system.cpu.iew.branchMispredicts 17750146 # Number of branch mispredicts detected at execute 441system.cpu.iew.iewExecutedInsts 1986410888 # Number of executed instructions 442system.cpu.iew.iewExecLoadInsts 573023734 # Number of load instructions executed 443system.cpu.iew.iewExecSquashedInsts 29598908 # Number of squashed instructions skipped in execute 444system.cpu.iew.exec_swp 0 # number of swp insts executed 445system.cpu.iew.exec_nop 127 # number of nop insts executed 446system.cpu.iew.exec_refs 763190345 # number of memory reference insts executed 447system.cpu.iew.exec_branches 238305534 # Number of branches executed 448system.cpu.iew.exec_stores 190166611 # Number of stores executed 449system.cpu.iew.exec_rate 1.961484 # Inst execution rate 450system.cpu.iew.wb_sent 1965043499 # cumulative count of insts sent to commit 451system.cpu.iew.wb_count 1956606576 # cumulative count of insts written-back 452system.cpu.iew.wb_producers 1295701772 # num instructions producing a value 453system.cpu.iew.wb_consumers 2060221208 # num instructions consuming a value 454system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 455system.cpu.iew.wb_rate 1.932054 # insts written-back per cycle 456system.cpu.iew.wb_fanout 0.628914 # average fanout of values written-back 457system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 458system.cpu.commit.commitSquashedInsts 473572340 # The number of squashed insts skipped by commit 459system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 460system.cpu.commit.branchMispredicts 15200427 # The number of times a branch was mispredicted 461system.cpu.commit.committed_per_cycle::samples 882264282 # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::mean 1.953013 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::stdev 2.733344 # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::0 395036396 44.78% 44.78% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::1 191994213 21.76% 66.54% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::2 72477507 8.21% 74.75% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::3 35260039 4.00% 78.75% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::4 18947912 2.15% 80.90% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::5 30765236 3.49% 84.38% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::6 20067867 2.27% 86.66% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::7 11401417 1.29% 87.95% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::8 106313695 12.05% 100.00% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::total 882264282 # Number of insts commited each cycle 478system.cpu.commit.committedInsts 1544563041 # Number of instructions committed 479system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed 480system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 481system.cpu.commit.refs 660773814 # Number of memory references committed 482system.cpu.commit.loads 485926769 # Number of loads committed 483system.cpu.commit.membars 62 # Number of memory barriers committed 484system.cpu.commit.branches 213462426 # Number of branches committed 485system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 486system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. 487system.cpu.commit.function_calls 13665177 # Number of function calls committed. 488system.cpu.commit.bw_lim_events 106313695 # number cycles where commit BW limit reached 489system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 490system.cpu.rob.rob_reads 2972596181 # The number of ROB reads 491system.cpu.rob.rob_writes 4462393115 # The number of ROB writes 492system.cpu.timesIdled 1008109 # Number of times that the entire CPU went into an idle state and unscheduled itself 493system.cpu.idleCycles 61490758 # Total number of cycles that the CPU has spent unscheduled due to idling 494system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 495system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated 496system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated 497system.cpu.cpi 0.655660 # CPI: Cycles Per Instruction 498system.cpu.cpi_total 0.655660 # CPI: Total CPI of All Threads 499system.cpu.ipc 1.525181 # IPC: Instructions Per Cycle 500system.cpu.ipc_total 1.525181 # IPC: Total IPC of All Threads 501system.cpu.int_regfile_reads 9949148949 # number of integer regfile reads 502system.cpu.int_regfile_writes 1936492974 # number of integer regfile writes 503system.cpu.fp_regfile_reads 113 # number of floating regfile reads 504system.cpu.fp_regfile_writes 115 # number of floating regfile writes 505system.cpu.misc_regfile_reads 737540247 # number of misc regfile reads 506system.cpu.misc_regfile_writes 124 # number of misc regfile writes 507system.cpu.icache.replacements 23 # number of replacements 508system.cpu.icache.tagsinuse 625.185145 # Cycle average of tags in use 509system.cpu.icache.total_refs 286733320 # Total number of references to valid blocks. 510system.cpu.icache.sampled_refs 778 # Sample count of references to valid blocks. 511system.cpu.icache.avg_refs 368551.825193 # Average number of references to valid blocks. 512system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 513system.cpu.icache.occ_blocks::cpu.inst 625.185145 # Average occupied blocks per requestor 514system.cpu.icache.occ_percent::cpu.inst 0.305266 # Average percentage of cache occupancy 515system.cpu.icache.occ_percent::total 0.305266 # Average percentage of cache occupancy 516system.cpu.icache.ReadReq_hits::cpu.inst 286733320 # number of ReadReq hits 517system.cpu.icache.ReadReq_hits::total 286733320 # number of ReadReq hits 518system.cpu.icache.demand_hits::cpu.inst 286733320 # number of demand (read+write) hits 519system.cpu.icache.demand_hits::total 286733320 # number of demand (read+write) hits 520system.cpu.icache.overall_hits::cpu.inst 286733320 # number of overall hits 521system.cpu.icache.overall_hits::total 286733320 # number of overall hits 522system.cpu.icache.ReadReq_misses::cpu.inst 1160 # number of ReadReq misses 523system.cpu.icache.ReadReq_misses::total 1160 # number of ReadReq misses 524system.cpu.icache.demand_misses::cpu.inst 1160 # number of demand (read+write) misses 525system.cpu.icache.demand_misses::total 1160 # number of demand (read+write) misses 526system.cpu.icache.overall_misses::cpu.inst 1160 # number of overall misses 527system.cpu.icache.overall_misses::total 1160 # number of overall misses 528system.cpu.icache.ReadReq_miss_latency::cpu.inst 59910000 # number of ReadReq miss cycles 529system.cpu.icache.ReadReq_miss_latency::total 59910000 # number of ReadReq miss cycles 530system.cpu.icache.demand_miss_latency::cpu.inst 59910000 # number of demand (read+write) miss cycles 531system.cpu.icache.demand_miss_latency::total 59910000 # number of demand (read+write) miss cycles 532system.cpu.icache.overall_miss_latency::cpu.inst 59910000 # number of overall miss cycles 533system.cpu.icache.overall_miss_latency::total 59910000 # number of overall miss cycles 534system.cpu.icache.ReadReq_accesses::cpu.inst 286734480 # number of ReadReq accesses(hits+misses) 535system.cpu.icache.ReadReq_accesses::total 286734480 # number of ReadReq accesses(hits+misses) 536system.cpu.icache.demand_accesses::cpu.inst 286734480 # number of demand (read+write) accesses 537system.cpu.icache.demand_accesses::total 286734480 # number of demand (read+write) accesses 538system.cpu.icache.overall_accesses::cpu.inst 286734480 # number of overall (read+write) accesses 539system.cpu.icache.overall_accesses::total 286734480 # number of overall (read+write) accesses 540system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 541system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 542system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 543system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 544system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 545system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 546system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51646.551724 # average ReadReq miss latency 547system.cpu.icache.ReadReq_avg_miss_latency::total 51646.551724 # average ReadReq miss latency 548system.cpu.icache.demand_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency 549system.cpu.icache.demand_avg_miss_latency::total 51646.551724 # average overall miss latency 550system.cpu.icache.overall_avg_miss_latency::cpu.inst 51646.551724 # average overall miss latency 551system.cpu.icache.overall_avg_miss_latency::total 51646.551724 # average overall miss latency 552system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked 553system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 555system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.icache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked 557system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu.icache.fast_writes 0 # number of fast writes performed 559system.cpu.icache.cache_copies 0 # number of cache copies performed 560system.cpu.icache.ReadReq_mshr_hits::cpu.inst 382 # number of ReadReq MSHR hits 561system.cpu.icache.ReadReq_mshr_hits::total 382 # number of ReadReq MSHR hits 562system.cpu.icache.demand_mshr_hits::cpu.inst 382 # number of demand (read+write) MSHR hits 563system.cpu.icache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits 564system.cpu.icache.overall_mshr_hits::cpu.inst 382 # number of overall MSHR hits 565system.cpu.icache.overall_mshr_hits::total 382 # number of overall MSHR hits 566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses 567system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses 568system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses 569system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses 570system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses 571system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses 572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43554500 # number of ReadReq MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_latency::total 43554500 # number of ReadReq MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43554500 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::total 43554500 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43554500 # number of overall MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::total 43554500 # number of overall MSHR miss cycles 578system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 579system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 580system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 581system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 582system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 583system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55982.647815 # average ReadReq mshr miss latency 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55982.647815 # average ReadReq mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55982.647815 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::total 55982.647815 # average overall mshr miss latency 590system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 591system.cpu.l2cache.replacements 2214498 # number of replacements 592system.cpu.l2cache.tagsinuse 31523.726273 # Cycle average of tags in use 593system.cpu.l2cache.total_refs 9246379 # Total number of references to valid blocks. 594system.cpu.l2cache.sampled_refs 2244276 # Sample count of references to valid blocks. 595system.cpu.l2cache.avg_refs 4.119983 # Average number of references to valid blocks. 596system.cpu.l2cache.warmup_cycle 20414306502 # Cycle when the warmup percentage was hit. 597system.cpu.l2cache.occ_blocks::writebacks 14432.975360 # Average occupied blocks per requestor 598system.cpu.l2cache.occ_blocks::cpu.inst 20.502484 # Average occupied blocks per requestor 599system.cpu.l2cache.occ_blocks::cpu.data 17070.248430 # Average occupied blocks per requestor 600system.cpu.l2cache.occ_percent::writebacks 0.440459 # Average percentage of cache occupancy 601system.cpu.l2cache.occ_percent::cpu.inst 0.000626 # Average percentage of cache occupancy 602system.cpu.l2cache.occ_percent::cpu.data 0.520943 # Average percentage of cache occupancy 603system.cpu.l2cache.occ_percent::total 0.962028 # Average percentage of cache occupancy 604system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits 605system.cpu.l2cache.ReadReq_hits::cpu.data 6289310 # number of ReadReq hits 606system.cpu.l2cache.ReadReq_hits::total 6289336 # number of ReadReq hits 607system.cpu.l2cache.Writeback_hits::writebacks 3781550 # number of Writeback hits 608system.cpu.l2cache.Writeback_hits::total 3781550 # number of Writeback hits 609system.cpu.l2cache.ReadExReq_hits::cpu.data 1066723 # number of ReadExReq hits 610system.cpu.l2cache.ReadExReq_hits::total 1066723 # number of ReadExReq hits 611system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits 612system.cpu.l2cache.demand_hits::cpu.data 7356033 # number of demand (read+write) hits 613system.cpu.l2cache.demand_hits::total 7356059 # number of demand (read+write) hits 614system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits 615system.cpu.l2cache.overall_hits::cpu.data 7356033 # number of overall hits 616system.cpu.l2cache.overall_hits::total 7356059 # number of overall hits 617system.cpu.l2cache.ReadReq_misses::cpu.inst 752 # number of ReadReq misses 618system.cpu.l2cache.ReadReq_misses::cpu.data 1419753 # number of ReadReq misses 619system.cpu.l2cache.ReadReq_misses::total 1420505 # number of ReadReq misses 620system.cpu.l2cache.ReadExReq_misses::cpu.data 826690 # number of ReadExReq misses 621system.cpu.l2cache.ReadExReq_misses::total 826690 # number of ReadExReq misses 622system.cpu.l2cache.demand_misses::cpu.inst 752 # number of demand (read+write) misses 623system.cpu.l2cache.demand_misses::cpu.data 2246443 # number of demand (read+write) misses 624system.cpu.l2cache.demand_misses::total 2247195 # number of demand (read+write) misses 625system.cpu.l2cache.overall_misses::cpu.inst 752 # number of overall misses 626system.cpu.l2cache.overall_misses::cpu.data 2246443 # number of overall misses 627system.cpu.l2cache.overall_misses::total 2247195 # number of overall misses 628system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42504500 # number of ReadReq miss cycles 629system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98123407500 # number of ReadReq miss cycles 630system.cpu.l2cache.ReadReq_miss_latency::total 98165912000 # number of ReadReq miss cycles 631system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58742590000 # number of ReadExReq miss cycles 632system.cpu.l2cache.ReadExReq_miss_latency::total 58742590000 # number of ReadExReq miss cycles 633system.cpu.l2cache.demand_miss_latency::cpu.inst 42504500 # number of demand (read+write) miss cycles 634system.cpu.l2cache.demand_miss_latency::cpu.data 156865997500 # number of demand (read+write) miss cycles 635system.cpu.l2cache.demand_miss_latency::total 156908502000 # number of demand (read+write) miss cycles 636system.cpu.l2cache.overall_miss_latency::cpu.inst 42504500 # number of overall miss cycles 637system.cpu.l2cache.overall_miss_latency::cpu.data 156865997500 # number of overall miss cycles 638system.cpu.l2cache.overall_miss_latency::total 156908502000 # number of overall miss cycles 639system.cpu.l2cache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) 640system.cpu.l2cache.ReadReq_accesses::cpu.data 7709063 # number of ReadReq accesses(hits+misses) 641system.cpu.l2cache.ReadReq_accesses::total 7709841 # number of ReadReq accesses(hits+misses) 642system.cpu.l2cache.Writeback_accesses::writebacks 3781550 # number of Writeback accesses(hits+misses) 643system.cpu.l2cache.Writeback_accesses::total 3781550 # number of Writeback accesses(hits+misses) 644system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893413 # number of ReadExReq accesses(hits+misses) 645system.cpu.l2cache.ReadExReq_accesses::total 1893413 # number of ReadExReq accesses(hits+misses) 646system.cpu.l2cache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses 647system.cpu.l2cache.demand_accesses::cpu.data 9602476 # number of demand (read+write) accesses 648system.cpu.l2cache.demand_accesses::total 9603254 # number of demand (read+write) accesses 649system.cpu.l2cache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses 650system.cpu.l2cache.overall_accesses::cpu.data 9602476 # number of overall (read+write) accesses 651system.cpu.l2cache.overall_accesses::total 9603254 # number of overall (read+write) accesses 652system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.966581 # miss rate for ReadReq accesses 653system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184167 # miss rate for ReadReq accesses 654system.cpu.l2cache.ReadReq_miss_rate::total 0.184246 # miss rate for ReadReq accesses 655system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436614 # miss rate for ReadExReq accesses 656system.cpu.l2cache.ReadExReq_miss_rate::total 0.436614 # miss rate for ReadExReq accesses 657system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966581 # miss rate for demand accesses 658system.cpu.l2cache.demand_miss_rate::cpu.data 0.233944 # miss rate for demand accesses 659system.cpu.l2cache.demand_miss_rate::total 0.234003 # miss rate for demand accesses 660system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966581 # miss rate for overall accesses 661system.cpu.l2cache.overall_miss_rate::cpu.data 0.233944 # miss rate for overall accesses 662system.cpu.l2cache.overall_miss_rate::total 0.234003 # miss rate for overall accesses 663system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56521.941489 # average ReadReq miss latency 664system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69113.012968 # average ReadReq miss latency 665system.cpu.l2cache.ReadReq_avg_miss_latency::total 69106.347391 # average ReadReq miss latency 666system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71057.579020 # average ReadExReq miss latency 667system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71057.579020 # average ReadExReq miss latency 668system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56521.941489 # average overall miss latency 669system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69828.612389 # average overall miss latency 670system.cpu.l2cache.demand_avg_miss_latency::total 69824.159452 # average overall miss latency 671system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56521.941489 # average overall miss latency 672system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69828.612389 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::total 69824.159452 # average overall miss latency 674system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 675system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 679system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.l2cache.fast_writes 0 # number of fast writes performed 681system.cpu.l2cache.cache_copies 0 # number of cache copies performed 682system.cpu.l2cache.writebacks::writebacks 1100812 # number of writebacks 683system.cpu.l2cache.writebacks::total 1100812 # number of writebacks 684system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 685system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits 686system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 687system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 688system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits 689system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 690system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 691system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits 692system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits 693system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 750 # number of ReadReq MSHR misses 694system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419746 # number of ReadReq MSHR misses 695system.cpu.l2cache.ReadReq_mshr_misses::total 1420496 # number of ReadReq MSHR misses 696system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826690 # number of ReadExReq MSHR misses 697system.cpu.l2cache.ReadExReq_mshr_misses::total 826690 # number of ReadExReq MSHR misses 698system.cpu.l2cache.demand_mshr_misses::cpu.inst 750 # number of demand (read+write) MSHR misses 699system.cpu.l2cache.demand_mshr_misses::cpu.data 2246436 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.demand_mshr_misses::total 2247186 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.overall_mshr_misses::cpu.inst 750 # number of overall MSHR misses 702system.cpu.l2cache.overall_mshr_misses::cpu.data 2246436 # number of overall MSHR misses 703system.cpu.l2cache.overall_mshr_misses::total 2247186 # number of overall MSHR misses 704system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32919184 # number of ReadReq MSHR miss cycles 705system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80176207714 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80209126898 # number of ReadReq MSHR miss cycles 707system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48315790009 # number of ReadExReq MSHR miss cycles 708system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48315790009 # number of ReadExReq MSHR miss cycles 709system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32919184 # number of demand (read+write) MSHR miss cycles 710system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128491997723 # number of demand (read+write) MSHR miss cycles 711system.cpu.l2cache.demand_mshr_miss_latency::total 128524916907 # number of demand (read+write) MSHR miss cycles 712system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32919184 # number of overall MSHR miss cycles 713system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128491997723 # number of overall MSHR miss cycles 714system.cpu.l2cache.overall_mshr_miss_latency::total 128524916907 # number of overall MSHR miss cycles 715system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for ReadReq accesses 716system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184166 # mshr miss rate for ReadReq accesses 717system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184245 # mshr miss rate for ReadReq accesses 718system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436614 # mshr miss rate for ReadExReq accesses 719system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436614 # mshr miss rate for ReadExReq accesses 720system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for demand accesses 721system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for demand accesses 722system.cpu.l2cache.demand_mshr_miss_rate::total 0.234003 # mshr miss rate for demand accesses 723system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964010 # mshr miss rate for overall accesses 724system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233943 # mshr miss rate for overall accesses 725system.cpu.l2cache.overall_mshr_miss_rate::total 0.234003 # mshr miss rate for overall accesses 726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43892.245333 # average ReadReq mshr miss latency 727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56472.219477 # average ReadReq mshr miss latency 728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56465.577445 # average ReadReq mshr miss latency 729system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58444.870519 # average ReadExReq mshr miss latency 730system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58444.870519 # average ReadExReq mshr miss latency 731system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency 732system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency 733system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency 734system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43892.245333 # average overall mshr miss latency 735system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57198.156423 # average overall mshr miss latency 736system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57193.715566 # average overall mshr miss latency 737system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 738system.cpu.dcache.replacements 9598379 # number of replacements 739system.cpu.dcache.tagsinuse 4087.934747 # Cycle average of tags in use 740system.cpu.dcache.total_refs 656008169 # Total number of references to valid blocks. 741system.cpu.dcache.sampled_refs 9602475 # Sample count of references to valid blocks. 742system.cpu.dcache.avg_refs 68.316571 # Average number of references to valid blocks. 743system.cpu.dcache.warmup_cycle 3424422000 # Cycle when the warmup percentage was hit. 744system.cpu.dcache.occ_blocks::cpu.data 4087.934747 # Average occupied blocks per requestor 745system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy 746system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy 747system.cpu.dcache.ReadReq_hits::cpu.data 488954223 # number of ReadReq hits 748system.cpu.dcache.ReadReq_hits::total 488954223 # number of ReadReq hits 749system.cpu.dcache.WriteReq_hits::cpu.data 167053823 # number of WriteReq hits 750system.cpu.dcache.WriteReq_hits::total 167053823 # number of WriteReq hits 751system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits 752system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits 753system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 754system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 755system.cpu.dcache.demand_hits::cpu.data 656008046 # number of demand (read+write) hits 756system.cpu.dcache.demand_hits::total 656008046 # number of demand (read+write) hits 757system.cpu.dcache.overall_hits::cpu.data 656008046 # number of overall hits 758system.cpu.dcache.overall_hits::total 656008046 # number of overall hits 759system.cpu.dcache.ReadReq_misses::cpu.data 11476242 # number of ReadReq misses 760system.cpu.dcache.ReadReq_misses::total 11476242 # number of ReadReq misses 761system.cpu.dcache.WriteReq_misses::cpu.data 5532224 # number of WriteReq misses 762system.cpu.dcache.WriteReq_misses::total 5532224 # number of WriteReq misses 763system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 764system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 765system.cpu.dcache.demand_misses::cpu.data 17008466 # number of demand (read+write) misses 766system.cpu.dcache.demand_misses::total 17008466 # number of demand (read+write) misses 767system.cpu.dcache.overall_misses::cpu.data 17008466 # number of overall misses 768system.cpu.dcache.overall_misses::total 17008466 # number of overall misses 769system.cpu.dcache.ReadReq_miss_latency::cpu.data 299283762000 # number of ReadReq miss cycles 770system.cpu.dcache.ReadReq_miss_latency::total 299283762000 # number of ReadReq miss cycles 771system.cpu.dcache.WriteReq_miss_latency::cpu.data 216949721927 # number of WriteReq miss cycles 772system.cpu.dcache.WriteReq_miss_latency::total 216949721927 # number of WriteReq miss cycles 773system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles 774system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles 775system.cpu.dcache.demand_miss_latency::cpu.data 516233483927 # number of demand (read+write) miss cycles 776system.cpu.dcache.demand_miss_latency::total 516233483927 # number of demand (read+write) miss cycles 777system.cpu.dcache.overall_miss_latency::cpu.data 516233483927 # number of overall miss cycles 778system.cpu.dcache.overall_miss_latency::total 516233483927 # number of overall miss cycles 779system.cpu.dcache.ReadReq_accesses::cpu.data 500430465 # number of ReadReq accesses(hits+misses) 780system.cpu.dcache.ReadReq_accesses::total 500430465 # number of ReadReq accesses(hits+misses) 781system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 782system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 783system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) 784system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) 785system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 786system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 787system.cpu.dcache.demand_accesses::cpu.data 673016512 # number of demand (read+write) accesses 788system.cpu.dcache.demand_accesses::total 673016512 # number of demand (read+write) accesses 789system.cpu.dcache.overall_accesses::cpu.data 673016512 # number of overall (read+write) accesses 790system.cpu.dcache.overall_accesses::total 673016512 # number of overall (read+write) accesses 791system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses 792system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses 793system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032055 # miss rate for WriteReq accesses 794system.cpu.dcache.WriteReq_miss_rate::total 0.032055 # miss rate for WriteReq accesses 795system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses 796system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses 797system.cpu.dcache.demand_miss_rate::cpu.data 0.025272 # miss rate for demand accesses 798system.cpu.dcache.demand_miss_rate::total 0.025272 # miss rate for demand accesses 799system.cpu.dcache.overall_miss_rate::cpu.data 0.025272 # miss rate for overall accesses 800system.cpu.dcache.overall_miss_rate::total 0.025272 # miss rate for overall accesses 801system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26078.550975 # average ReadReq miss latency 802system.cpu.dcache.ReadReq_avg_miss_latency::total 26078.550975 # average ReadReq miss latency 803system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39215.643099 # average WriteReq miss latency 804system.cpu.dcache.WriteReq_avg_miss_latency::total 39215.643099 # average WriteReq miss latency 805system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency 806system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency 807system.cpu.dcache.demand_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency 808system.cpu.dcache.demand_avg_miss_latency::total 30351.560448 # average overall miss latency 809system.cpu.dcache.overall_avg_miss_latency::cpu.data 30351.560448 # average overall miss latency 810system.cpu.dcache.overall_avg_miss_latency::total 30351.560448 # average overall miss latency 811system.cpu.dcache.blocked_cycles::no_mshrs 19781174 # number of cycles access was blocked 812system.cpu.dcache.blocked_cycles::no_targets 987477 # number of cycles access was blocked 813system.cpu.dcache.blocked::no_mshrs 1172505 # number of cycles access was blocked 814system.cpu.dcache.blocked::no_targets 64541 # number of cycles access was blocked 815system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.870865 # average number of cycles each access was blocked 816system.cpu.dcache.avg_blocked_cycles::no_targets 15.299995 # average number of cycles each access was blocked 817system.cpu.dcache.fast_writes 0 # number of fast writes performed 818system.cpu.dcache.cache_copies 0 # number of cache copies performed 819system.cpu.dcache.writebacks::writebacks 3781550 # number of writebacks 820system.cpu.dcache.writebacks::total 3781550 # number of writebacks 821system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767179 # number of ReadReq MSHR hits 822system.cpu.dcache.ReadReq_mshr_hits::total 3767179 # number of ReadReq MSHR hits 823system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638811 # number of WriteReq MSHR hits 824system.cpu.dcache.WriteReq_mshr_hits::total 3638811 # number of WriteReq MSHR hits 825system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 826system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 827system.cpu.dcache.demand_mshr_hits::cpu.data 7405990 # number of demand (read+write) MSHR hits 828system.cpu.dcache.demand_mshr_hits::total 7405990 # number of demand (read+write) MSHR hits 829system.cpu.dcache.overall_mshr_hits::cpu.data 7405990 # number of overall MSHR hits 830system.cpu.dcache.overall_mshr_hits::total 7405990 # number of overall MSHR hits 831system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709063 # number of ReadReq MSHR misses 832system.cpu.dcache.ReadReq_mshr_misses::total 7709063 # number of ReadReq MSHR misses 833system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893413 # number of WriteReq MSHR misses 834system.cpu.dcache.WriteReq_mshr_misses::total 1893413 # number of WriteReq MSHR misses 835system.cpu.dcache.demand_mshr_misses::cpu.data 9602476 # number of demand (read+write) MSHR misses 836system.cpu.dcache.demand_mshr_misses::total 9602476 # number of demand (read+write) MSHR misses 837system.cpu.dcache.overall_mshr_misses::cpu.data 9602476 # number of overall MSHR misses 838system.cpu.dcache.overall_mshr_misses::total 9602476 # number of overall MSHR misses 839system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170550521000 # number of ReadReq MSHR miss cycles 840system.cpu.dcache.ReadReq_mshr_miss_latency::total 170550521000 # number of ReadReq MSHR miss cycles 841system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71842126604 # number of WriteReq MSHR miss cycles 842system.cpu.dcache.WriteReq_mshr_miss_latency::total 71842126604 # number of WriteReq MSHR miss cycles 843system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242392647604 # number of demand (read+write) MSHR miss cycles 844system.cpu.dcache.demand_mshr_miss_latency::total 242392647604 # number of demand (read+write) MSHR miss cycles 845system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242392647604 # number of overall MSHR miss cycles 846system.cpu.dcache.overall_mshr_miss_latency::total 242392647604 # number of overall MSHR miss cycles 847system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses 848system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses 849system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses 850system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses 851system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses 852system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses 853system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses 854system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses 855system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22123.378808 # average ReadReq mshr miss latency 856system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22123.378808 # average ReadReq mshr miss latency 857system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37943.188625 # average WriteReq mshr miss latency 858system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37943.188625 # average WriteReq mshr miss latency 859system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency 860system.cpu.dcache.demand_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency 861system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25242.723606 # average overall mshr miss latency 862system.cpu.dcache.overall_avg_mshr_miss_latency::total 25242.723606 # average overall mshr miss latency 863system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 864 865---------- End Simulation Statistics ---------- 866