stats.txt revision 9055:38f1926fb599
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.463994 # Number of seconds simulated 4sim_ticks 463993693500 # Number of ticks simulated 5final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 128371 # Simulator instruction rate (inst/s) 8host_op_rate 143208 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38563333 # Simulator tick rate (ticks/s) 10host_mem_usage 232076 # Number of bytes of host memory used 11host_seconds 12031.99 # Real time elapsed on the host 12sim_insts 1544563066 # Number of instructions simulated 13sim_ops 1723073879 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 49344 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 189746304 # Number of bytes read from this memory 16system.physmem.bytes_read::total 189795648 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 49344 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 49344 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 78222144 # Number of bytes written to this memory 20system.physmem.bytes_written::total 78222144 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 771 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2964786 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2965557 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1222221 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1222221 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 106346 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 408941558 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 409047904 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 106346 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 106346 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 168584498 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 168584498 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 168584498 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 106346 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 408941558 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 577632403 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 46system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 48system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 49system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 50system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 51system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52system.cpu.dtb.read_accesses 0 # DTB read accesses 53system.cpu.dtb.write_accesses 0 # DTB write accesses 54system.cpu.dtb.inst_accesses 0 # ITB inst accesses 55system.cpu.dtb.hits 0 # DTB hits 56system.cpu.dtb.misses 0 # DTB misses 57system.cpu.dtb.accesses 0 # DTB accesses 58system.cpu.itb.inst_hits 0 # ITB inst hits 59system.cpu.itb.inst_misses 0 # ITB inst misses 60system.cpu.itb.read_hits 0 # DTB read hits 61system.cpu.itb.read_misses 0 # DTB read misses 62system.cpu.itb.write_hits 0 # DTB write hits 63system.cpu.itb.write_misses 0 # DTB write misses 64system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 65system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 66system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 67system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 69system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 70system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 71system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 46 # Number of system calls 80system.cpu.numCycles 927987388 # number of cpu cycles simulated 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 83system.cpu.BPredUnit.lookups 300553850 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 246366147 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 16098585 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 170916236 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 156311774 # Number of BTB hits 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 89system.cpu.BPredUnit.usedRAS 18335288 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 425 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 292740519 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 2158326699 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 300553850 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 174647062 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 429206926 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 83759589 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 129259054 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 200 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 283730265 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 5372560 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 918446800 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.613763 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.238744 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::0 489239924 53.27% 53.27% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 23020148 2.51% 55.77% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 38764254 4.22% 60.00% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 47809734 5.21% 65.20% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 40766066 4.44% 69.64% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 46976906 5.11% 74.75% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 39072572 4.25% 79.01% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 18137057 1.97% 80.98% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 174660139 19.02% 100.00% # Number of instructions fetched each cycle (Total) 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 118system.cpu.fetch.rateDist::total 918446800 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.323877 # Number of branch fetches per cycle 120system.cpu.fetch.rate 2.325815 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 322039794 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 109288431 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 403236235 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 16643003 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 67239337 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 46165390 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 810 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 2346870217 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 2646 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 67239337 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 343676895 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 50827249 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 9551 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 397069716 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 59624052 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 2289998307 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 23088 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 4666333 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 46320806 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 2264655243 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 10570139009 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 10570134861 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 4148 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 1706319999 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 558335244 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 4462 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 4454 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 136929133 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 624839821 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 218742392 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 85961960 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 66558298 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 2190567677 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 692 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 2016055896 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 4892741 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 462785080 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 1074735939 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 515 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 918446800 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 2.195071 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.923309 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::0 251194344 27.35% 27.35% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 138877340 15.12% 42.47% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 158309179 17.24% 59.71% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 116273452 12.66% 72.37% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 125754756 13.69% 86.06% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 75525220 8.22% 94.28% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 39163504 4.26% 98.55% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 10678346 1.16% 99.71% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 2670659 0.29% 100.00% # Number of insts issued each cycle 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 177system.cpu.iq.issued_per_cycle::total 918446800 # Number of insts issued each cycle 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 179system.cpu.iq.fu_full::IntAlu 824240 3.28% 3.28% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 4827 0.02% 3.30% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 19025079 75.82% 79.12% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 5238831 20.88% 100.00% # attempts to use FU when none available 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 213system.cpu.iq.FU_type_0::IntAlu 1234276939 61.22% 61.22% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 932607 0.05% 61.27% # Type of FU issued 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.27% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.27% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 29 0.00% 61.27% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.27% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued 242system.cpu.iq.FU_type_0::MemRead 587048024 29.12% 90.39% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 193798201 9.61% 100.00% # Type of FU issued 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 246system.cpu.iq.FU_type_0::total 2016055896 # Type of FU issued 247system.cpu.iq.rate 2.172504 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 25092977 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.012447 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 4980543862 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 2653539100 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 1958126109 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 448 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 790 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 2041148646 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 227 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 63700277 # Number of loads that had data forwarded from stores 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 260system.cpu.iew.lsq.thread0.squashedLoads 138913044 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 284373 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 189336 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 43895340 # Number of stores squashed 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 266system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 267system.cpu.iew.lsq.thread0.cacheBlocked 451092 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 269system.cpu.iew.iewSquashCycles 67239337 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 23164250 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 1316440 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 2190576494 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 5585867 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 624839821 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 218742392 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 626 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 207277 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 49894 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 189336 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 8626288 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 10208500 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 18834788 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 1986583692 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 572477440 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 29472204 # Number of squashed instructions skipped in execute 286system.cpu.iew.exec_swp 0 # number of swp insts executed 287system.cpu.iew.exec_nop 8125 # number of nop insts executed 288system.cpu.iew.exec_refs 763312359 # number of memory reference insts executed 289system.cpu.iew.exec_branches 238194699 # Number of branches executed 290system.cpu.iew.exec_stores 190834919 # Number of stores executed 291system.cpu.iew.exec_rate 2.140744 # Inst execution rate 292system.cpu.iew.wb_sent 1967109112 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 1958126281 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 1296093484 # num instructions producing a value 295system.cpu.iew.wb_consumers 2068479796 # num instructions consuming a value 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 297system.cpu.iew.wb_rate 2.110079 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.626592 # average fanout of values written-back 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 300system.cpu.commit.commitCommittedInsts 1544563084 # The number of committed instructions 301system.cpu.commit.commitCommittedOps 1723073897 # The number of committed instructions 302system.cpu.commit.commitSquashedInsts 467569115 # The number of squashed insts skipped by commit 303system.cpu.commit.commitNonSpecStalls 177 # The number of times commit has been forced to stall to communicate backwards 304system.cpu.commit.branchMispredicts 16098007 # The number of times a branch was mispredicted 305system.cpu.commit.committed_per_cycle::samples 851207464 # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::mean 2.024270 # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::stdev 2.756192 # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::0 362905349 42.63% 42.63% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::1 192760849 22.65% 65.28% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::2 73571189 8.64% 73.92% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::3 35131293 4.13% 78.05% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::4 18689200 2.20% 80.25% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::5 30622248 3.60% 83.84% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::6 19666355 2.31% 86.15% # Number of insts commited each cycle 316system.cpu.commit.committed_per_cycle::7 10977227 1.29% 87.44% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::8 106883754 12.56% 100.00% # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 319system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 320system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 321system.cpu.commit.committed_per_cycle::total 851207464 # Number of insts commited each cycle 322system.cpu.commit.committedInsts 1544563084 # Number of instructions committed 323system.cpu.commit.committedOps 1723073897 # Number of ops (including micro ops) committed 324system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 325system.cpu.commit.refs 660773829 # Number of memory references committed 326system.cpu.commit.loads 485926777 # Number of loads committed 327system.cpu.commit.membars 62 # Number of memory barriers committed 328system.cpu.commit.branches 213462371 # Number of branches committed 329system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 330system.cpu.commit.int_insts 1536941877 # Number of committed integer instructions. 331system.cpu.commit.function_calls 13665177 # Number of function calls committed. 332system.cpu.commit.bw_lim_events 106883754 # number cycles where commit BW limit reached 333system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 334system.cpu.rob.rob_reads 2934966123 # The number of ROB reads 335system.cpu.rob.rob_writes 4448699546 # The number of ROB writes 336system.cpu.timesIdled 899596 # Number of times that the entire CPU went into an idle state and unscheduled itself 337system.cpu.idleCycles 9540588 # Total number of cycles that the CPU has spent unscheduled due to idling 338system.cpu.committedInsts 1544563066 # Number of Instructions Simulated 339system.cpu.committedOps 1723073879 # Number of Ops (including micro ops) Simulated 340system.cpu.committedInsts_total 1544563066 # Number of Instructions Simulated 341system.cpu.cpi 0.600809 # CPI: Cycles Per Instruction 342system.cpu.cpi_total 0.600809 # CPI: Total CPI of All Threads 343system.cpu.ipc 1.664422 # IPC: Instructions Per Cycle 344system.cpu.ipc_total 1.664422 # IPC: Total IPC of All Threads 345system.cpu.int_regfile_reads 9951953141 # number of integer regfile reads 346system.cpu.int_regfile_writes 1938266429 # number of integer regfile writes 347system.cpu.fp_regfile_reads 186 # number of floating regfile reads 348system.cpu.fp_regfile_writes 205 # number of floating regfile writes 349system.cpu.misc_regfile_reads 2897977277 # number of misc regfile reads 350system.cpu.misc_regfile_writes 138 # number of misc regfile writes 351system.cpu.icache.replacements 28 # number of replacements 352system.cpu.icache.tagsinuse 641.389873 # Cycle average of tags in use 353system.cpu.icache.total_refs 283729068 # Total number of references to valid blocks. 354system.cpu.icache.sampled_refs 801 # Sample count of references to valid blocks. 355system.cpu.icache.avg_refs 354218.561798 # Average number of references to valid blocks. 356system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 357system.cpu.icache.occ_blocks::cpu.inst 641.389873 # Average occupied blocks per requestor 358system.cpu.icache.occ_percent::cpu.inst 0.313179 # Average percentage of cache occupancy 359system.cpu.icache.occ_percent::total 0.313179 # Average percentage of cache occupancy 360system.cpu.icache.ReadReq_hits::cpu.inst 283729068 # number of ReadReq hits 361system.cpu.icache.ReadReq_hits::total 283729068 # number of ReadReq hits 362system.cpu.icache.demand_hits::cpu.inst 283729068 # number of demand (read+write) hits 363system.cpu.icache.demand_hits::total 283729068 # number of demand (read+write) hits 364system.cpu.icache.overall_hits::cpu.inst 283729068 # number of overall hits 365system.cpu.icache.overall_hits::total 283729068 # number of overall hits 366system.cpu.icache.ReadReq_misses::cpu.inst 1197 # number of ReadReq misses 367system.cpu.icache.ReadReq_misses::total 1197 # number of ReadReq misses 368system.cpu.icache.demand_misses::cpu.inst 1197 # number of demand (read+write) misses 369system.cpu.icache.demand_misses::total 1197 # number of demand (read+write) misses 370system.cpu.icache.overall_misses::cpu.inst 1197 # number of overall misses 371system.cpu.icache.overall_misses::total 1197 # number of overall misses 372system.cpu.icache.ReadReq_miss_latency::cpu.inst 39840000 # number of ReadReq miss cycles 373system.cpu.icache.ReadReq_miss_latency::total 39840000 # number of ReadReq miss cycles 374system.cpu.icache.demand_miss_latency::cpu.inst 39840000 # number of demand (read+write) miss cycles 375system.cpu.icache.demand_miss_latency::total 39840000 # number of demand (read+write) miss cycles 376system.cpu.icache.overall_miss_latency::cpu.inst 39840000 # number of overall miss cycles 377system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles 378system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses) 379system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses) 380system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses 381system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses 382system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses 383system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses 384system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 385system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 386system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 387system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 388system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 389system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 390system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency 391system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020 # average ReadReq miss latency 392system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency 393system.cpu.icache.demand_avg_miss_latency::total 33283.208020 # average overall miss latency 394system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency 395system.cpu.icache.overall_avg_miss_latency::total 33283.208020 # average overall miss latency 396system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 400system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 401system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.cpu.icache.fast_writes 0 # number of fast writes performed 403system.cpu.icache.cache_copies 0 # number of cache copies performed 404system.cpu.icache.ReadReq_mshr_hits::cpu.inst 396 # number of ReadReq MSHR hits 405system.cpu.icache.ReadReq_mshr_hits::total 396 # number of ReadReq MSHR hits 406system.cpu.icache.demand_mshr_hits::cpu.inst 396 # number of demand (read+write) MSHR hits 407system.cpu.icache.demand_mshr_hits::total 396 # number of demand (read+write) MSHR hits 408system.cpu.icache.overall_mshr_hits::cpu.inst 396 # number of overall MSHR hits 409system.cpu.icache.overall_mshr_hits::total 396 # number of overall MSHR hits 410system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses 411system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses 412system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses 413system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses 414system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses 415system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses 416system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27579500 # number of ReadReq MSHR miss cycles 417system.cpu.icache.ReadReq_mshr_miss_latency::total 27579500 # number of ReadReq MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27579500 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::total 27579500 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 423system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 424system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 425system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 426system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 427system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34431.335830 # average ReadReq mshr miss latency 430system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency 431system.cpu.icache.demand_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency 432system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency 433system.cpu.icache.overall_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency 434system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 435system.cpu.dcache.replacements 9619302 # number of replacements 436system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use 437system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks. 438system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks. 439system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks. 440system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit. 441system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor 442system.cpu.dcache.occ_percent::cpu.data 0.997987 # Average percentage of cache occupancy 443system.cpu.dcache.occ_percent::total 0.997987 # Average percentage of cache occupancy 444system.cpu.dcache.ReadReq_hits::cpu.data 493348220 # number of ReadReq hits 445system.cpu.dcache.ReadReq_hits::total 493348220 # number of ReadReq hits 446system.cpu.dcache.WriteReq_hits::cpu.data 167378287 # number of WriteReq hits 447system.cpu.dcache.WriteReq_hits::total 167378287 # number of WriteReq hits 448system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits 449system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits 450system.cpu.dcache.StoreCondReq_hits::cpu.data 68 # number of StoreCondReq hits 451system.cpu.dcache.StoreCondReq_hits::total 68 # number of StoreCondReq hits 452system.cpu.dcache.demand_hits::cpu.data 660726507 # number of demand (read+write) hits 453system.cpu.dcache.demand_hits::total 660726507 # number of demand (read+write) hits 454system.cpu.dcache.overall_hits::cpu.data 660726507 # number of overall hits 455system.cpu.dcache.overall_hits::total 660726507 # number of overall hits 456system.cpu.dcache.ReadReq_misses::cpu.data 10693817 # number of ReadReq misses 457system.cpu.dcache.ReadReq_misses::total 10693817 # number of ReadReq misses 458system.cpu.dcache.WriteReq_misses::cpu.data 5207760 # number of WriteReq misses 459system.cpu.dcache.WriteReq_misses::total 5207760 # number of WriteReq misses 460system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 461system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 462system.cpu.dcache.demand_misses::cpu.data 15901577 # number of demand (read+write) misses 463system.cpu.dcache.demand_misses::total 15901577 # number of demand (read+write) misses 464system.cpu.dcache.overall_misses::cpu.data 15901577 # number of overall misses 465system.cpu.dcache.overall_misses::total 15901577 # number of overall misses 466system.cpu.dcache.ReadReq_miss_latency::cpu.data 189065481500 # number of ReadReq miss cycles 467system.cpu.dcache.ReadReq_miss_latency::total 189065481500 # number of ReadReq miss cycles 468system.cpu.dcache.WriteReq_miss_latency::cpu.data 129319032251 # number of WriteReq miss cycles 469system.cpu.dcache.WriteReq_miss_latency::total 129319032251 # number of WriteReq miss cycles 470system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles 471system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles 472system.cpu.dcache.demand_miss_latency::cpu.data 318384513751 # number of demand (read+write) miss cycles 473system.cpu.dcache.demand_miss_latency::total 318384513751 # number of demand (read+write) miss cycles 474system.cpu.dcache.overall_miss_latency::cpu.data 318384513751 # number of overall miss cycles 475system.cpu.dcache.overall_miss_latency::total 318384513751 # number of overall miss cycles 476system.cpu.dcache.ReadReq_accesses::cpu.data 504042037 # number of ReadReq accesses(hits+misses) 477system.cpu.dcache.ReadReq_accesses::total 504042037 # number of ReadReq accesses(hits+misses) 478system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 479system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 480system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) 481system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses 485system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses 486system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses 487system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses 488system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses 489system.cpu.dcache.ReadReq_miss_rate::total 0.021216 # miss rate for ReadReq accesses 490system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses 491system.cpu.dcache.WriteReq_miss_rate::total 0.030175 # miss rate for WriteReq accesses 492system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses 493system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses 494system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses 495system.cpu.dcache.demand_miss_rate::total 0.023501 # miss rate for demand accesses 496system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses 497system.cpu.dcache.overall_miss_rate::total 0.023501 # miss rate for overall accesses 498system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency 499system.cpu.dcache.ReadReq_avg_miss_latency::total 17679.887499 # average ReadReq miss latency 500system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency 501system.cpu.dcache.WriteReq_avg_miss_latency::total 24831.987697 # average WriteReq miss latency 502system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency 503system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency 504system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency 505system.cpu.dcache.demand_avg_miss_latency::total 20022.197405 # average overall miss latency 506system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency 507system.cpu.dcache.overall_avg_miss_latency::total 20022.197405 # average overall miss latency 508system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked 509system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked 510system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked 512system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked 514system.cpu.dcache.fast_writes 0 # number of fast writes performed 515system.cpu.dcache.cache_copies 0 # number of cache copies performed 516system.cpu.dcache.writebacks::writebacks 3133684 # number of writebacks 517system.cpu.dcache.writebacks::total 3133684 # number of writebacks 518system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2964371 # number of ReadReq MSHR hits 519system.cpu.dcache.ReadReq_mshr_hits::total 2964371 # number of ReadReq MSHR hits 520system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313808 # number of WriteReq MSHR hits 521system.cpu.dcache.WriteReq_mshr_hits::total 3313808 # number of WriteReq MSHR hits 522system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 523system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 524system.cpu.dcache.demand_mshr_hits::cpu.data 6278179 # number of demand (read+write) MSHR hits 525system.cpu.dcache.demand_mshr_hits::total 6278179 # number of demand (read+write) MSHR hits 526system.cpu.dcache.overall_mshr_hits::cpu.data 6278179 # number of overall MSHR hits 527system.cpu.dcache.overall_mshr_hits::total 6278179 # number of overall MSHR hits 528system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729446 # number of ReadReq MSHR misses 529system.cpu.dcache.ReadReq_mshr_misses::total 7729446 # number of ReadReq MSHR misses 530system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893952 # number of WriteReq MSHR misses 531system.cpu.dcache.WriteReq_mshr_misses::total 1893952 # number of WriteReq MSHR misses 532system.cpu.dcache.demand_mshr_misses::cpu.data 9623398 # number of demand (read+write) MSHR misses 533system.cpu.dcache.demand_mshr_misses::total 9623398 # number of demand (read+write) MSHR misses 534system.cpu.dcache.overall_mshr_misses::cpu.data 9623398 # number of overall MSHR misses 535system.cpu.dcache.overall_mshr_misses::total 9623398 # number of overall MSHR misses 536system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93061119500 # number of ReadReq MSHR miss cycles 537system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles 538system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles 539system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles 540system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles 541system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles 542system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles 543system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles 544system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses 545system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015335 # mshr miss rate for ReadReq accesses 546system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses 547system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses 548system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses 549system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses 550system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses 551system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses 552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.817537 # average ReadReq mshr miss latency 554system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23955.185749 # average WriteReq mshr miss latency 556system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency 557system.cpu.dcache.demand_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency 558system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency 559system.cpu.dcache.overall_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency 560system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 561system.cpu.l2cache.replacements 2953110 # number of replacements 562system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use 563system.cpu.l2cache.total_refs 7878336 # Total number of references to valid blocks. 564system.cpu.l2cache.sampled_refs 2980430 # Sample count of references to valid blocks. 565system.cpu.l2cache.avg_refs 2.643355 # Average number of references to valid blocks. 566system.cpu.l2cache.warmup_cycle 100989511500 # Cycle when the warmup percentage was hit. 567system.cpu.l2cache.occ_blocks::writebacks 10758.137226 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_blocks::cpu.inst 11.396468 # Average occupied blocks per requestor 569system.cpu.l2cache.occ_blocks::cpu.data 16105.809458 # Average occupied blocks per requestor 570system.cpu.l2cache.occ_percent::writebacks 0.328312 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::cpu.inst 0.000348 # Average percentage of cache occupancy 572system.cpu.l2cache.occ_percent::cpu.data 0.491510 # Average percentage of cache occupancy 573system.cpu.l2cache.occ_percent::total 0.820170 # Average percentage of cache occupancy 574system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits 575system.cpu.l2cache.ReadReq_hits::cpu.data 5680299 # number of ReadReq hits 576system.cpu.l2cache.ReadReq_hits::total 5680328 # number of ReadReq hits 577system.cpu.l2cache.Writeback_hits::writebacks 3133684 # number of Writeback hits 578system.cpu.l2cache.Writeback_hits::total 3133684 # number of Writeback hits 579system.cpu.l2cache.ReadExReq_hits::cpu.data 978305 # number of ReadExReq hits 580system.cpu.l2cache.ReadExReq_hits::total 978305 # number of ReadExReq hits 581system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits 582system.cpu.l2cache.demand_hits::cpu.data 6658604 # number of demand (read+write) hits 583system.cpu.l2cache.demand_hits::total 6658633 # number of demand (read+write) hits 584system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits 585system.cpu.l2cache.overall_hits::cpu.data 6658604 # number of overall hits 586system.cpu.l2cache.overall_hits::total 6658633 # number of overall hits 587system.cpu.l2cache.ReadReq_misses::cpu.inst 772 # number of ReadReq misses 588system.cpu.l2cache.ReadReq_misses::cpu.data 2049145 # number of ReadReq misses 589system.cpu.l2cache.ReadReq_misses::total 2049917 # number of ReadReq misses 590system.cpu.l2cache.ReadExReq_misses::cpu.data 915649 # number of ReadExReq misses 591system.cpu.l2cache.ReadExReq_misses::total 915649 # number of ReadExReq misses 592system.cpu.l2cache.demand_misses::cpu.inst 772 # number of demand (read+write) misses 593system.cpu.l2cache.demand_misses::cpu.data 2964794 # number of demand (read+write) misses 594system.cpu.l2cache.demand_misses::total 2965566 # number of demand (read+write) misses 595system.cpu.l2cache.overall_misses::cpu.inst 772 # number of overall misses 596system.cpu.l2cache.overall_misses::cpu.data 2964794 # number of overall misses 597system.cpu.l2cache.overall_misses::total 2965566 # number of overall misses 598system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26523500 # number of ReadReq miss cycles 599system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70343968500 # number of ReadReq miss cycles 600system.cpu.l2cache.ReadReq_miss_latency::total 70370492000 # number of ReadReq miss cycles 601system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31764549000 # number of ReadExReq miss cycles 602system.cpu.l2cache.ReadExReq_miss_latency::total 31764549000 # number of ReadExReq miss cycles 603system.cpu.l2cache.demand_miss_latency::cpu.inst 26523500 # number of demand (read+write) miss cycles 604system.cpu.l2cache.demand_miss_latency::cpu.data 102108517500 # number of demand (read+write) miss cycles 605system.cpu.l2cache.demand_miss_latency::total 102135041000 # number of demand (read+write) miss cycles 606system.cpu.l2cache.overall_miss_latency::cpu.inst 26523500 # number of overall miss cycles 607system.cpu.l2cache.overall_miss_latency::cpu.data 102108517500 # number of overall miss cycles 608system.cpu.l2cache.overall_miss_latency::total 102135041000 # number of overall miss cycles 609system.cpu.l2cache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses) 610system.cpu.l2cache.ReadReq_accesses::cpu.data 7729444 # number of ReadReq accesses(hits+misses) 611system.cpu.l2cache.ReadReq_accesses::total 7730245 # number of ReadReq accesses(hits+misses) 612system.cpu.l2cache.Writeback_accesses::writebacks 3133684 # number of Writeback accesses(hits+misses) 613system.cpu.l2cache.Writeback_accesses::total 3133684 # number of Writeback accesses(hits+misses) 614system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893954 # number of ReadExReq accesses(hits+misses) 615system.cpu.l2cache.ReadExReq_accesses::total 1893954 # number of ReadExReq accesses(hits+misses) 616system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses 617system.cpu.l2cache.demand_accesses::cpu.data 9623398 # number of demand (read+write) accesses 618system.cpu.l2cache.demand_accesses::total 9624199 # number of demand (read+write) accesses 619system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses 620system.cpu.l2cache.overall_accesses::cpu.data 9623398 # number of overall (read+write) accesses 621system.cpu.l2cache.overall_accesses::total 9624199 # number of overall (read+write) accesses 622system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963795 # miss rate for ReadReq accesses 623system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265109 # miss rate for ReadReq accesses 624system.cpu.l2cache.ReadReq_miss_rate::total 0.265181 # miss rate for ReadReq accesses 625system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483459 # miss rate for ReadExReq accesses 626system.cpu.l2cache.ReadExReq_miss_rate::total 0.483459 # miss rate for ReadExReq accesses 627system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963795 # miss rate for demand accesses 628system.cpu.l2cache.demand_miss_rate::cpu.data 0.308082 # miss rate for demand accesses 629system.cpu.l2cache.demand_miss_rate::total 0.308136 # miss rate for demand accesses 630system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963795 # miss rate for overall accesses 631system.cpu.l2cache.overall_miss_rate::cpu.data 0.308082 # miss rate for overall accesses 632system.cpu.l2cache.overall_miss_rate::total 0.308136 # miss rate for overall accesses 633system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285 # average ReadReq miss latency 634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450 # average ReadReq miss latency 635system.cpu.l2cache.ReadReq_avg_miss_latency::total 34328.459152 # average ReadReq miss latency 636system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311 # average ReadExReq miss latency 637system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34690.748311 # average ReadExReq miss latency 638system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency 639system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency 640system.cpu.l2cache.demand_avg_miss_latency::total 34440.319656 # average overall miss latency 641system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency 642system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency 643system.cpu.l2cache.overall_avg_miss_latency::total 34440.319656 # average overall miss latency 644system.cpu.l2cache.blocked_cycles::no_mshrs 57329500 # number of cycles access was blocked 645system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked 647system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 648system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8512.175204 # average number of cycles each access was blocked 649system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.l2cache.fast_writes 0 # number of fast writes performed 651system.cpu.l2cache.cache_copies 0 # number of cache copies performed 652system.cpu.l2cache.writebacks::writebacks 1222221 # number of writebacks 653system.cpu.l2cache.writebacks::total 1222221 # number of writebacks 654system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 655system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits 656system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 657system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 658system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits 659system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 660system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 661system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits 662system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits 663system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 771 # number of ReadReq MSHR misses 664system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2049137 # number of ReadReq MSHR misses 665system.cpu.l2cache.ReadReq_mshr_misses::total 2049908 # number of ReadReq MSHR misses 666system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915649 # number of ReadExReq MSHR misses 667system.cpu.l2cache.ReadExReq_mshr_misses::total 915649 # number of ReadExReq MSHR misses 668system.cpu.l2cache.demand_mshr_misses::cpu.inst 771 # number of demand (read+write) MSHR misses 669system.cpu.l2cache.demand_mshr_misses::cpu.data 2964786 # number of demand (read+write) MSHR misses 670system.cpu.l2cache.demand_mshr_misses::total 2965557 # number of demand (read+write) MSHR misses 671system.cpu.l2cache.overall_mshr_misses::cpu.inst 771 # number of overall MSHR misses 672system.cpu.l2cache.overall_mshr_misses::cpu.data 2964786 # number of overall MSHR misses 673system.cpu.l2cache.overall_mshr_misses::total 2965557 # number of overall MSHR misses 674system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24050500 # number of ReadReq MSHR miss cycles 675system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63906561000 # number of ReadReq MSHR miss cycles 676system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63930611500 # number of ReadReq MSHR miss cycles 677system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28918183500 # number of ReadExReq MSHR miss cycles 678system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28918183500 # number of ReadExReq MSHR miss cycles 679system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24050500 # number of demand (read+write) MSHR miss cycles 680system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92824744500 # number of demand (read+write) MSHR miss cycles 681system.cpu.l2cache.demand_mshr_miss_latency::total 92848795000 # number of demand (read+write) MSHR miss cycles 682system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24050500 # number of overall MSHR miss cycles 683system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 # number of overall MSHR miss cycles 684system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles 685system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses 686system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses 687system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.265180 # mshr miss rate for ReadReq accesses 688system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses 689system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.483459 # mshr miss rate for ReadExReq accesses 690system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses 691system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses 692system.cpu.l2cache.demand_mshr_miss_rate::total 0.308135 # mshr miss rate for demand accesses 693system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses 694system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses 695system.cpu.l2cache.overall_mshr_miss_rate::total 0.308135 # mshr miss rate for overall accesses 696system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency 697system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency 698system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31187.063761 # average ReadReq mshr miss latency 699system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency 700system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.171225 # average ReadExReq mshr miss latency 701system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency 702system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency 703system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency 704system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency 705system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency 706system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency 707system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 708 709---------- End Simulation Statistics ---------- 710