stats.txt revision 10736:4433fb00fa7d
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.771783 # Number of seconds simulated 4sim_ticks 771782683000 # Number of ticks simulated 5final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 141348 # Simulator instruction rate (inst/s) 8host_op_rate 152281 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 70628369 # Simulator tick rate (ticks/s) 10host_mem_usage 310548 # Number of bytes of host memory used 11host_seconds 10927.38 # Real time elapsed on the host 12sim_insts 1544563023 # Number of instructions simulated 13sim_ops 1664032415 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 66112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 238756480 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 63336128 # Number of bytes read from this memory 19system.physmem.bytes_read::total 302158720 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 66112 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 66112 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 104900608 # Number of bytes written to this memory 23system.physmem.bytes_written::total 104900608 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1033 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 3730570 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 989627 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 4721230 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 1639072 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 1639072 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 85661 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 309357135 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 82064718 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 391507515 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 85661 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 85661 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 135919878 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 135919878 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 135919878 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 85661 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 309357135 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 82064718 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 527427392 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 4721230 # Number of read requests accepted 44system.physmem.writeReqs 1639072 # Number of write requests accepted 45system.physmem.readBursts 4721230 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 1639072 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 301708544 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 450176 # Total number of bytes read from write queue 49system.physmem.bytesWritten 104898432 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 302158720 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 104900608 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 7034 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 296496 # Per bank write bursts 56system.physmem.perBankRdBursts::1 294922 # Per bank write bursts 57system.physmem.perBankRdBursts::2 288553 # Per bank write bursts 58system.physmem.perBankRdBursts::3 293200 # Per bank write bursts 59system.physmem.perBankRdBursts::4 290519 # Per bank write bursts 60system.physmem.perBankRdBursts::5 289057 # Per bank write bursts 61system.physmem.perBankRdBursts::6 284695 # Per bank write bursts 62system.physmem.perBankRdBursts::7 280747 # Per bank write bursts 63system.physmem.perBankRdBursts::8 297891 # Per bank write bursts 64system.physmem.perBankRdBursts::9 303659 # Per bank write bursts 65system.physmem.perBankRdBursts::10 295750 # Per bank write bursts 66system.physmem.perBankRdBursts::11 302488 # Per bank write bursts 67system.physmem.perBankRdBursts::12 303486 # Per bank write bursts 68system.physmem.perBankRdBursts::13 302338 # Per bank write bursts 69system.physmem.perBankRdBursts::14 297681 # Per bank write bursts 70system.physmem.perBankRdBursts::15 292714 # Per bank write bursts 71system.physmem.perBankWrBursts::0 104090 # Per bank write bursts 72system.physmem.perBankWrBursts::1 102136 # Per bank write bursts 73system.physmem.perBankWrBursts::2 99204 # Per bank write bursts 74system.physmem.perBankWrBursts::3 100079 # Per bank write bursts 75system.physmem.perBankWrBursts::4 99319 # Per bank write bursts 76system.physmem.perBankWrBursts::5 99058 # Per bank write bursts 77system.physmem.perBankWrBursts::6 102867 # Per bank write bursts 78system.physmem.perBankWrBursts::7 104266 # Per bank write bursts 79system.physmem.perBankWrBursts::8 105488 # Per bank write bursts 80system.physmem.perBankWrBursts::9 104503 # Per bank write bursts 81system.physmem.perBankWrBursts::10 102301 # Per bank write bursts 82system.physmem.perBankWrBursts::11 102956 # Per bank write bursts 83system.physmem.perBankWrBursts::12 103260 # Per bank write bursts 84system.physmem.perBankWrBursts::13 102520 # Per bank write bursts 85system.physmem.perBankWrBursts::14 104484 # Per bank write bursts 86system.physmem.perBankWrBursts::15 102507 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 771782536000 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 4721230 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 1639072 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 2775597 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1044443 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 331745 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 234202 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 153941 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 85295 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 39428 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 23872 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 18360 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 4183 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1645 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 788 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 22873 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 24573 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 60114 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 75847 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 85447 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 93235 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 99435 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 103341 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 105611 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 106420 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 106485 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 107133 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 108359 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 110847 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 113228 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 106323 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 103422 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 101669 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 2755 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 1061 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 485 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 99 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 22 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 4289012 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 94.801701 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 78.923105 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 101.558340 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 3414847 79.62% 79.62% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 675748 15.76% 95.37% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 96615 2.25% 97.63% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 35482 0.83% 98.45% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 22807 0.53% 98.99% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 12154 0.28% 99.27% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 7173 0.17% 99.44% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 5164 0.12% 99.56% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 19022 0.44% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 4289012 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 98837 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 47.696531 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 32.309771 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 98.301255 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-127 95044 96.16% 96.16% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::128-255 1344 1.36% 97.52% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::384-511 419 0.42% 98.73% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::512-639 374 0.38% 99.10% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::640-767 356 0.36% 99.46% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::768-895 254 0.26% 99.72% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::896-1023 146 0.15% 99.87% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::1024-1151 62 0.06% 99.93% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::1152-1279 41 0.04% 99.97% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::1280-1407 8 0.01% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1536-1663 2 0.00% 99.99% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::2560-2687 3 0.00% 100.00% # Reads before turning the bus around for writes 235system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes 236system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes 237system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes 238system.physmem.rdPerTurnAround::total 98837 # Reads before turning the bus around for writes 239system.physmem.wrPerTurnAround::samples 98837 # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::mean 16.583243 # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::gmean 16.550199 # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::stdev 1.089458 # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::16 73410 74.27% 74.27% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::17 1674 1.69% 75.97% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::18 18461 18.68% 94.65% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::19 3603 3.65% 98.29% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::20 928 0.94% 99.23% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::21 388 0.39% 99.62% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::22 174 0.18% 99.80% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::23 100 0.10% 99.90% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::24 61 0.06% 99.96% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::25 27 0.03% 99.99% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::26 7 0.01% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::27 4 0.00% 100.00% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::total 98837 # Writes before turning the bus around for reads 256system.physmem.totQLat 132409571838 # Total ticks spent queuing 257system.physmem.totMemAccLat 220800746838 # Total ticks spent from burst creation until serviced by the DRAM 258system.physmem.totBusLat 23570980000 # Total ticks spent in databus transfers 259system.physmem.avgQLat 28087.41 # Average queueing delay per DRAM burst 260system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 261system.physmem.avgMemAccLat 46837.41 # Average memory access latency per DRAM burst 262system.physmem.avgRdBW 390.92 # Average DRAM read bandwidth in MiByte/s 263system.physmem.avgWrBW 135.92 # Average achieved write bandwidth in MiByte/s 264system.physmem.avgRdBWSys 391.51 # Average system read bandwidth in MiByte/s 265system.physmem.avgWrBWSys 135.92 # Average system write bandwidth in MiByte/s 266system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 267system.physmem.busUtil 4.12 # Data bus utilization in percentage 268system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads 269system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes 270system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing 271system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing 272system.physmem.readRowHits 1710867 # Number of row buffer hits during reads 273system.physmem.writeRowHits 353347 # Number of row buffer hits during writes 274system.physmem.readRowHitRate 36.29 # Row buffer hit rate for reads 275system.physmem.writeRowHitRate 21.56 # Row buffer hit rate for writes 276system.physmem.avgGap 121343.69 # Average gap between requests 277system.physmem.pageHitRate 32.49 # Row buffer hit rate, read and write combined 278system.physmem_0.actEnergy 16078381200 # Energy for activate commands per rank (pJ) 279system.physmem_0.preEnergy 8772926250 # Energy for precharge commands per rank (pJ) 280system.physmem_0.readEnergy 18081671400 # Energy for read commands per rank (pJ) 281system.physmem_0.writeEnergy 5255351280 # Energy for write commands per rank (pJ) 282system.physmem_0.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) 283system.physmem_0.actBackEnergy 410988240855 # Energy for active background per rank (pJ) 284system.physmem_0.preBackEnergy 102552687000 # Energy for precharge background per rank (pJ) 285system.physmem_0.totalEnergy 612138233745 # Total energy per rank (pJ) 286system.physmem_0.averagePower 793.150023 # Core power per rank (mW) 287system.physmem_0.memoryStateTime::IDLE 168058001250 # Time in different power states 288system.physmem_0.memoryStateTime::REF 25771460000 # Time in different power states 289system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 290system.physmem_0.memoryStateTime::ACT 577951698750 # Time in different power states 291system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 292system.physmem_1.actEnergy 16346489040 # Energy for activate commands per rank (pJ) 293system.physmem_1.preEnergy 8919215250 # Energy for precharge commands per rank (pJ) 294system.physmem_1.readEnergy 18688846800 # Energy for read commands per rank (pJ) 295system.physmem_1.writeEnergy 5365504800 # Energy for write commands per rank (pJ) 296system.physmem_1.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) 297system.physmem_1.actBackEnergy 412404849315 # Energy for active background per rank (pJ) 298system.physmem_1.preBackEnergy 101310048000 # Energy for precharge background per rank (pJ) 299system.physmem_1.totalEnergy 613443928965 # Total energy per rank (pJ) 300system.physmem_1.averagePower 794.841817 # Core power per rank (mW) 301system.physmem_1.memoryStateTime::IDLE 165993972457 # Time in different power states 302system.physmem_1.memoryStateTime::REF 25771460000 # Time in different power states 303system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 304system.physmem_1.memoryStateTime::ACT 580015821043 # Time in different power states 305system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 306system.cpu.branchPred.lookups 286268512 # Number of BP lookups 307system.cpu.branchPred.condPredicted 223399208 # Number of conditional branches predicted 308system.cpu.branchPred.condIncorrect 14631885 # Number of conditional branches incorrect 309system.cpu.branchPred.BTBLookups 157652290 # Number of BTB lookups 310system.cpu.branchPred.BTBHits 150341382 # Number of BTB hits 311system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 312system.cpu.branchPred.BTBHitPct 95.362638 # BTB Hit Percentage 313system.cpu.branchPred.usedRAS 16641174 # Number of times the RAS was used to get a target. 314system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. 315system.cpu_clk_domain.clock 500 # Clock period in ticks 316system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 324system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 325system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 326system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 327system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 328system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 329system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 330system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 331system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 332system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 333system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 334system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 335system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 336system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 337system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 338system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 339system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 340system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 341system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 342system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 343system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 344system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 345system.cpu.dtb.walker.walks 0 # Table walker walks requested 346system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 352system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 353system.cpu.dtb.inst_hits 0 # ITB inst hits 354system.cpu.dtb.inst_misses 0 # ITB inst misses 355system.cpu.dtb.read_hits 0 # DTB read hits 356system.cpu.dtb.read_misses 0 # DTB read misses 357system.cpu.dtb.write_hits 0 # DTB write hits 358system.cpu.dtb.write_misses 0 # DTB write misses 359system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 360system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 361system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 362system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 363system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 364system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 365system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 366system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 367system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 368system.cpu.dtb.read_accesses 0 # DTB read accesses 369system.cpu.dtb.write_accesses 0 # DTB write accesses 370system.cpu.dtb.inst_accesses 0 # ITB inst accesses 371system.cpu.dtb.hits 0 # DTB hits 372system.cpu.dtb.misses 0 # DTB misses 373system.cpu.dtb.accesses 0 # DTB accesses 374system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 381system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 382system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 383system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 384system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 385system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 386system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 387system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 388system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 389system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 390system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 391system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 392system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 393system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 394system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 395system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 396system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 398system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 399system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 400system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 401system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 402system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 403system.cpu.itb.walker.walks 0 # Table walker walks requested 404system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 411system.cpu.itb.inst_hits 0 # ITB inst hits 412system.cpu.itb.inst_misses 0 # ITB inst misses 413system.cpu.itb.read_hits 0 # DTB read hits 414system.cpu.itb.read_misses 0 # DTB read misses 415system.cpu.itb.write_hits 0 # DTB write hits 416system.cpu.itb.write_misses 0 # DTB write misses 417system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 418system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 419system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 420system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 421system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 422system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 423system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 424system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 425system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 426system.cpu.itb.read_accesses 0 # DTB read accesses 427system.cpu.itb.write_accesses 0 # DTB write accesses 428system.cpu.itb.inst_accesses 0 # ITB inst accesses 429system.cpu.itb.hits 0 # DTB hits 430system.cpu.itb.misses 0 # DTB misses 431system.cpu.itb.accesses 0 # DTB accesses 432system.cpu.workload.num_syscalls 46 # Number of system calls 433system.cpu.numCycles 1543565367 # number of cpu cycles simulated 434system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 435system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 436system.cpu.fetch.icacheStallCycles 13925779 # Number of cycles fetch is stalled on an Icache miss 437system.cpu.fetch.Insts 2067423618 # Number of instructions fetch has processed 438system.cpu.fetch.Branches 286268512 # Number of branches that fetch encountered 439system.cpu.fetch.predictedBranches 166982556 # Number of branches that fetch has predicted taken 440system.cpu.fetch.Cycles 1514915602 # Number of cycles fetch has run and was not squashing or blocked 441system.cpu.fetch.SquashCycles 29288421 # Number of cycles fetch has spent squashing 442system.cpu.fetch.MiscStallCycles 253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 443system.cpu.fetch.IcacheWaitRetryStallCycles 919 # Number of stall cycles due to full MSHR 444system.cpu.fetch.CacheLines 656914213 # Number of cache lines fetched 445system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed 446system.cpu.fetch.rateDist::samples 1543486763 # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::mean 1.434983 # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::stdev 1.229356 # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::0 461116597 29.87% 29.87% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::1 465422138 30.15% 60.03% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::2 101389056 6.57% 66.60% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::3 515558972 33.40% 100.00% # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.rateDist::total 1543486763 # Number of instructions fetched each cycle (Total) 458system.cpu.fetch.branchRate 0.185459 # Number of branch fetches per cycle 459system.cpu.fetch.rate 1.339382 # Number of inst fetches per cycle 460system.cpu.decode.IdleCycles 74615169 # Number of cycles decode is idle 461system.cpu.decode.BlockedCycles 546131714 # Number of cycles decode is blocked 462system.cpu.decode.RunCycles 850052649 # Number of cycles decode is running 463system.cpu.decode.UnblockCycles 58043724 # Number of cycles decode is unblocking 464system.cpu.decode.SquashCycles 14643507 # Number of cycles decode is squashing 465system.cpu.decode.BranchResolved 42202613 # Number of times decode resolved a branch 466system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction 467system.cpu.decode.DecodedInsts 2037139109 # Number of instructions handled by decode 468system.cpu.decode.SquashedInsts 52472329 # Number of squashed instructions handled by decode 469system.cpu.rename.SquashCycles 14643507 # Number of cycles rename is squashing 470system.cpu.rename.IdleCycles 139680975 # Number of cycles rename is idle 471system.cpu.rename.BlockCycles 464946049 # Number of cycles rename is blocking 472system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst 473system.cpu.rename.RunCycles 837873228 # Number of cycles rename is running 474system.cpu.rename.UnblockCycles 86328827 # Number of cycles rename is unblocking 475system.cpu.rename.RenamedInsts 1976320354 # Number of instructions processed by rename 476system.cpu.rename.SquashedInsts 26732336 # Number of squashed instructions processed by rename 477system.cpu.rename.ROBFullEvents 45128593 # Number of times rename has blocked due to ROB full 478system.cpu.rename.IQFullEvents 125639 # Number of times rename has blocked due to IQ full 479system.cpu.rename.LQFullEvents 1500891 # Number of times rename has blocked due to LQ full 480system.cpu.rename.SQFullEvents 25518898 # Number of times rename has blocked due to SQ full 481system.cpu.rename.RenamedOperands 1985788047 # Number of destination operands rename has renamed 482system.cpu.rename.RenameLookups 9127865226 # Number of register rename lookups that rename has made 483system.cpu.rename.int_rename_lookups 2432787425 # Number of integer rename lookups 484system.cpu.rename.fp_rename_lookups 124 # Number of floating rename lookups 485system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed 486system.cpu.rename.UndoneMaps 310889102 # Number of HB maps that are undone due to squashing 487system.cpu.rename.serializingInsts 151 # count of serializing insts renamed 488system.cpu.rename.tempSerializingInsts 141 # count of temporary serializing insts renamed 489system.cpu.rename.skidInsts 111344488 # count of insts added to the skid buffer 490system.cpu.memDep0.insertedLoads 542536301 # Number of loads inserted to the mem dependence unit. 491system.cpu.memDep0.insertedStores 199301557 # Number of stores inserted to the mem dependence unit. 492system.cpu.memDep0.conflictingLoads 26908887 # Number of conflicting loads. 493system.cpu.memDep0.conflictingStores 29198248 # Number of conflicting stores. 494system.cpu.iq.iqInstsAdded 1947883742 # Number of instructions added to the IQ (excludes non-spec) 495system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ 496system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued 497system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued 498system.cpu.iq.iqSquashedInstsExamined 279518916 # Number of squashed instructions iterated over during squash; mainly for profiling 499system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph 500system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed 501system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::mean 1.203385 # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::stdev 1.151093 # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::0 590762659 38.27% 38.27% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::1 325764931 21.11% 59.38% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::2 378272466 24.51% 83.89% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::3 219653351 14.23% 98.12% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::4 29027182 1.88% 100.00% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::5 6174 0.00% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 517system.cpu.iq.issued_per_cycle::total 1543486763 # Number of insts issued each cycle 518system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 519system.cpu.iq.fu_full::IntAlu 166053840 40.99% 40.99% # attempts to use FU when none available 520system.cpu.iq.fu_full::IntMult 1992 0.00% 40.99% # attempts to use FU when none available 521system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available 526system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available 527system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available 546system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 548system.cpu.iq.fu_full::MemRead 191416352 47.25% 88.24% # attempts to use FU when none available 549system.cpu.iq.fu_full::MemWrite 47630536 11.76% 100.00% # attempts to use FU when none available 550system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 551system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 552system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 553system.cpu.iq.FU_type_0::IntAlu 1138248479 61.28% 61.28% # Type of FU issued 554system.cpu.iq.FU_type_0::IntMult 801009 0.04% 61.32% # Type of FU issued 555system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 560system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 561system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatCvt 26 0.00% 61.32% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued 582system.cpu.iq.FU_type_0::MemRead 532044411 28.64% 89.97% # Type of FU issued 583system.cpu.iq.FU_type_0::MemWrite 186315567 10.03% 100.00% # Type of FU issued 584system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 585system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 586system.cpu.iq.FU_type_0::total 1857409514 # Type of FU issued 587system.cpu.iq.rate 1.203324 # Inst issue rate 588system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested 589system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst) 590system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads 591system.cpu.iq.int_inst_queue_writes 2227415601 # Number of integer instruction queue writes 592system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses 593system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads 594system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes 595system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses 596system.cpu.iq.int_alu_accesses 2262512110 # Number of integer alu accesses 597system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses 598system.cpu.iew.lsq.thread0.forwLoads 17814082 # Number of loads that had data forwarded from stores 599system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 600system.cpu.iew.lsq.thread0.squashedLoads 84229967 # Number of loads squashed 601system.cpu.iew.lsq.thread0.ignoredResponses 66402 # Number of memory responses ignored because the instruction is squashed 602system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations 603system.cpu.iew.lsq.thread0.squashedStores 24454512 # Number of stores squashed 604system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 605system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 606system.cpu.iew.lsq.thread0.rescheduledLoads 4520775 # Number of loads that were rescheduled 607system.cpu.iew.lsq.thread0.cacheBlocked 4802645 # Number of times an access to memory failed due to the cache being blocked 608system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 609system.cpu.iew.iewSquashCycles 14643507 # Number of cycles IEW is squashing 610system.cpu.iew.iewBlockCycles 25316113 # Number of cycles IEW is blocking 611system.cpu.iew.iewUnblockCycles 1330365 # Number of cycles IEW is unblocking 612system.cpu.iew.iewDispatchedInsts 1947884031 # Number of instructions dispatched to IQ 613system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 614system.cpu.iew.iewDispLoadInsts 542536301 # Number of dispatched load instructions 615system.cpu.iew.iewDispStoreInsts 199301557 # Number of dispatched store instructions 616system.cpu.iew.iewDispNonSpecInsts 148 # Number of dispatched non-speculative instructions 617system.cpu.iew.iewIQFullEvents 158933 # Number of times the IQ has become full, causing a stall 618system.cpu.iew.iewLSQFullEvents 1170467 # Number of times the LSQ has become full, causing a stall 619system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations 620system.cpu.iew.predictedTakenIncorrect 7700956 # Number of branches that were predicted taken incorrectly 621system.cpu.iew.predictedNotTakenIncorrect 8705023 # Number of branches that were predicted not taken incorrectly 622system.cpu.iew.branchMispredicts 16405979 # Number of branch mispredicts detected at execute 623system.cpu.iew.iewExecutedInsts 1827745758 # Number of executed instructions 624system.cpu.iew.iewExecLoadInsts 516865735 # Number of load instructions executed 625system.cpu.iew.iewExecSquashedInsts 29663756 # Number of squashed instructions skipped in execute 626system.cpu.iew.exec_swp 0 # number of swp insts executed 627system.cpu.iew.exec_nop 79 # number of nop insts executed 628system.cpu.iew.exec_refs 698617938 # number of memory reference insts executed 629system.cpu.iew.exec_branches 229554698 # Number of branches executed 630system.cpu.iew.exec_stores 181752203 # Number of stores executed 631system.cpu.iew.exec_rate 1.184106 # Inst execution rate 632system.cpu.iew.wb_sent 1808737138 # cumulative count of insts sent to commit 633system.cpu.iew.wb_count 1805707322 # cumulative count of insts written-back 634system.cpu.iew.wb_producers 1169287953 # num instructions producing a value 635system.cpu.iew.wb_consumers 1689671414 # num instructions consuming a value 636system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 637system.cpu.iew.wb_rate 1.169829 # insts written-back per cycle 638system.cpu.iew.wb_fanout 0.692021 # average fanout of values written-back 639system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 640system.cpu.commit.commitSquashedInsts 257958644 # The number of squashed insts skipped by commit 641system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 642system.cpu.commit.branchMispredicts 14631182 # The number of times a branch was mispredicted 643system.cpu.commit.committed_per_cycle::samples 1504006174 # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::mean 1.106400 # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::stdev 2.024308 # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::0 923727407 61.42% 61.42% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::1 250637926 16.66% 78.08% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::2 110048306 7.32% 85.40% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::3 55269063 3.67% 89.07% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::4 29308073 1.95% 91.02% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::5 34102690 2.27% 93.29% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::6 24713726 1.64% 94.93% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::7 18129256 1.21% 96.14% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::8 58069727 3.86% 100.00% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 658system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::total 1504006174 # Number of insts commited each cycle 660system.cpu.commit.committedInsts 1544563041 # Number of instructions committed 661system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed 662system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 663system.cpu.commit.refs 633153379 # Number of memory references committed 664system.cpu.commit.loads 458306334 # Number of loads committed 665system.cpu.commit.membars 62 # Number of memory barriers committed 666system.cpu.commit.branches 213462426 # Number of branches committed 667system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 668system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. 669system.cpu.commit.function_calls 13665177 # Number of function calls committed. 670system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 671system.cpu.commit.op_class_0::IntAlu 1030178729 61.91% 61.91% # Class of committed instruction 672system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 673system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 677system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 678system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 679system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction 697system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 698system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 699system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 700system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 701system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction 702system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 703system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction 705system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached 706system.cpu.rob.rob_reads 3367926925 # The number of ROB reads 707system.cpu.rob.rob_writes 3883468057 # The number of ROB writes 708system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself 709system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling 710system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 711system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated 712system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction 713system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads 714system.cpu.ipc 1.000646 # IPC: Instructions Per Cycle 715system.cpu.ipc_total 1.000646 # IPC: Total IPC of All Threads 716system.cpu.int_regfile_reads 2175695472 # number of integer regfile reads 717system.cpu.int_regfile_writes 1261559121 # number of integer regfile writes 718system.cpu.fp_regfile_reads 38 # number of floating regfile reads 719system.cpu.fp_regfile_writes 48 # number of floating regfile writes 720system.cpu.cc_regfile_reads 6965502930 # number of cc regfile reads 721system.cpu.cc_regfile_writes 551873305 # number of cc regfile writes 722system.cpu.misc_regfile_reads 675842878 # number of misc regfile reads 723system.cpu.misc_regfile_writes 124 # number of misc regfile writes 724system.cpu.dcache.tags.replacements 17005493 # number of replacements 725system.cpu.dcache.tags.tagsinuse 511.964646 # Cycle average of tags in use 726system.cpu.dcache.tags.total_refs 638183172 # Total number of references to valid blocks. 727system.cpu.dcache.tags.sampled_refs 17006005 # Sample count of references to valid blocks. 728system.cpu.dcache.tags.avg_refs 37.526931 # Average number of references to valid blocks. 729system.cpu.dcache.tags.warmup_cycle 79063000 # Cycle when the warmup percentage was hit. 730system.cpu.dcache.tags.occ_blocks::cpu.data 511.964646 # Average occupied blocks per requestor 731system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy 732system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy 733system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 734system.cpu.dcache.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id 735system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 736system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 737system.cpu.dcache.tags.tag_accesses 1335677307 # Number of tag accesses 738system.cpu.dcache.tags.data_accesses 1335677307 # Number of data accesses 739system.cpu.dcache.ReadReq_hits::cpu.data 469397613 # number of ReadReq hits 740system.cpu.dcache.ReadReq_hits::total 469397613 # number of ReadReq hits 741system.cpu.dcache.WriteReq_hits::cpu.data 168785441 # number of WriteReq hits 742system.cpu.dcache.WriteReq_hits::total 168785441 # number of WriteReq hits 743system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 744system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 745system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 746system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 747system.cpu.dcache.demand_hits::cpu.data 638183054 # number of demand (read+write) hits 748system.cpu.dcache.demand_hits::total 638183054 # number of demand (read+write) hits 749system.cpu.dcache.overall_hits::cpu.data 638183054 # number of overall hits 750system.cpu.dcache.overall_hits::total 638183054 # number of overall hits 751system.cpu.dcache.ReadReq_misses::cpu.data 17351867 # number of ReadReq misses 752system.cpu.dcache.ReadReq_misses::total 17351867 # number of ReadReq misses 753system.cpu.dcache.WriteReq_misses::cpu.data 3800606 # number of WriteReq misses 754system.cpu.dcache.WriteReq_misses::total 3800606 # number of WriteReq misses 755system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 756system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 757system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 758system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses 759system.cpu.dcache.demand_misses::cpu.data 21152473 # number of demand (read+write) misses 760system.cpu.dcache.demand_misses::total 21152473 # number of demand (read+write) misses 761system.cpu.dcache.overall_misses::cpu.data 21152475 # number of overall misses 762system.cpu.dcache.overall_misses::total 21152475 # number of overall misses 763system.cpu.dcache.ReadReq_miss_latency::cpu.data 417182903209 # number of ReadReq miss cycles 764system.cpu.dcache.ReadReq_miss_latency::total 417182903209 # number of ReadReq miss cycles 765system.cpu.dcache.WriteReq_miss_latency::cpu.data 149917932873 # number of WriteReq miss cycles 766system.cpu.dcache.WriteReq_miss_latency::total 149917932873 # number of WriteReq miss cycles 767system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358750 # number of LoadLockedReq miss cycles 768system.cpu.dcache.LoadLockedReq_miss_latency::total 358750 # number of LoadLockedReq miss cycles 769system.cpu.dcache.demand_miss_latency::cpu.data 567100836082 # number of demand (read+write) miss cycles 770system.cpu.dcache.demand_miss_latency::total 567100836082 # number of demand (read+write) miss cycles 771system.cpu.dcache.overall_miss_latency::cpu.data 567100836082 # number of overall miss cycles 772system.cpu.dcache.overall_miss_latency::total 567100836082 # number of overall miss cycles 773system.cpu.dcache.ReadReq_accesses::cpu.data 486749480 # number of ReadReq accesses(hits+misses) 774system.cpu.dcache.ReadReq_accesses::total 486749480 # number of ReadReq accesses(hits+misses) 775system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 776system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 777system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) 778system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) 779system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 780system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 781system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 782system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 783system.cpu.dcache.demand_accesses::cpu.data 659335527 # number of demand (read+write) accesses 784system.cpu.dcache.demand_accesses::total 659335527 # number of demand (read+write) accesses 785system.cpu.dcache.overall_accesses::cpu.data 659335529 # number of overall (read+write) accesses 786system.cpu.dcache.overall_accesses::total 659335529 # number of overall (read+write) accesses 787system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035648 # miss rate for ReadReq accesses 788system.cpu.dcache.ReadReq_miss_rate::total 0.035648 # miss rate for ReadReq accesses 789system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022022 # miss rate for WriteReq accesses 790system.cpu.dcache.WriteReq_miss_rate::total 0.022022 # miss rate for WriteReq accesses 791system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 792system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 793system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses 794system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses 795system.cpu.dcache.demand_miss_rate::cpu.data 0.032082 # miss rate for demand accesses 796system.cpu.dcache.demand_miss_rate::total 0.032082 # miss rate for demand accesses 797system.cpu.dcache.overall_miss_rate::cpu.data 0.032082 # miss rate for overall accesses 798system.cpu.dcache.overall_miss_rate::total 0.032082 # miss rate for overall accesses 799system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24042.536933 # average ReadReq miss latency 800system.cpu.dcache.ReadReq_avg_miss_latency::total 24042.536933 # average ReadReq miss latency 801system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39445.797032 # average WriteReq miss latency 802system.cpu.dcache.WriteReq_avg_miss_latency::total 39445.797032 # average WriteReq miss latency 803system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 89687.500000 # average LoadLockedReq miss latency 804system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 89687.500000 # average LoadLockedReq miss latency 805system.cpu.dcache.demand_avg_miss_latency::cpu.data 26810.143480 # average overall miss latency 806system.cpu.dcache.demand_avg_miss_latency::total 26810.143480 # average overall miss latency 807system.cpu.dcache.overall_avg_miss_latency::cpu.data 26810.140945 # average overall miss latency 808system.cpu.dcache.overall_avg_miss_latency::total 26810.140945 # average overall miss latency 809system.cpu.dcache.blocked_cycles::no_mshrs 20723795 # number of cycles access was blocked 810system.cpu.dcache.blocked_cycles::no_targets 3315809 # number of cycles access was blocked 811system.cpu.dcache.blocked::no_mshrs 944207 # number of cycles access was blocked 812system.cpu.dcache.blocked::no_targets 67033 # number of cycles access was blocked 813system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.948360 # average number of cycles each access was blocked 814system.cpu.dcache.avg_blocked_cycles::no_targets 49.465323 # average number of cycles each access was blocked 815system.cpu.dcache.fast_writes 0 # number of fast writes performed 816system.cpu.dcache.cache_copies 0 # number of cache copies performed 817system.cpu.dcache.writebacks::writebacks 4835251 # number of writebacks 818system.cpu.dcache.writebacks::total 4835251 # number of writebacks 819system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3083373 # number of ReadReq MSHR hits 820system.cpu.dcache.ReadReq_mshr_hits::total 3083373 # number of ReadReq MSHR hits 821system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1063096 # number of WriteReq MSHR hits 822system.cpu.dcache.WriteReq_mshr_hits::total 1063096 # number of WriteReq MSHR hits 823system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 824system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 825system.cpu.dcache.demand_mshr_hits::cpu.data 4146469 # number of demand (read+write) MSHR hits 826system.cpu.dcache.demand_mshr_hits::total 4146469 # number of demand (read+write) MSHR hits 827system.cpu.dcache.overall_mshr_hits::cpu.data 4146469 # number of overall MSHR hits 828system.cpu.dcache.overall_mshr_hits::total 4146469 # number of overall MSHR hits 829system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268494 # number of ReadReq MSHR misses 830system.cpu.dcache.ReadReq_mshr_misses::total 14268494 # number of ReadReq MSHR misses 831system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737510 # number of WriteReq MSHR misses 832system.cpu.dcache.WriteReq_mshr_misses::total 2737510 # number of WriteReq MSHR misses 833system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 834system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 835system.cpu.dcache.demand_mshr_misses::cpu.data 17006004 # number of demand (read+write) MSHR misses 836system.cpu.dcache.demand_mshr_misses::total 17006004 # number of demand (read+write) MSHR misses 837system.cpu.dcache.overall_mshr_misses::cpu.data 17006005 # number of overall MSHR misses 838system.cpu.dcache.overall_mshr_misses::total 17006005 # number of overall MSHR misses 839system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 329072767985 # number of ReadReq MSHR miss cycles 840system.cpu.dcache.ReadReq_mshr_miss_latency::total 329072767985 # number of ReadReq MSHR miss cycles 841system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115107857313 # number of WriteReq MSHR miss cycles 842system.cpu.dcache.WriteReq_mshr_miss_latency::total 115107857313 # number of WriteReq MSHR miss cycles 843system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles 844system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles 845system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444180625298 # number of demand (read+write) MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::total 444180625298 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444180693048 # number of overall MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::total 444180693048 # number of overall MSHR miss cycles 849system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses 850system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses 852system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses 854system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses 855system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses 856system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses 857system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses 858system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses 859system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23062.894233 # average ReadReq mshr miss latency 860system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23062.894233 # average ReadReq mshr miss latency 861system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42048.378750 # average WriteReq mshr miss latency 862system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42048.378750 # average WriteReq mshr miss latency 863system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency 864system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency 865system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26119.047443 # average overall mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::total 26119.047443 # average overall mshr miss latency 867system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26119.049891 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::total 26119.049891 # average overall mshr miss latency 869system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 870system.cpu.icache.tags.replacements 588 # number of replacements 871system.cpu.icache.tags.tagsinuse 446.068543 # Cycle average of tags in use 872system.cpu.icache.tags.total_refs 656912599 # Total number of references to valid blocks. 873system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. 874system.cpu.icache.tags.avg_refs 610513.567844 # Average number of references to valid blocks. 875system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 876system.cpu.icache.tags.occ_blocks::cpu.inst 446.068543 # Average occupied blocks per requestor 877system.cpu.icache.tags.occ_percent::cpu.inst 0.871228 # Average percentage of cache occupancy 878system.cpu.icache.tags.occ_percent::total 0.871228 # Average percentage of cache occupancy 879system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id 880system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 881system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id 882system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id 883system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id 884system.cpu.icache.tags.tag_accesses 1313829498 # Number of tag accesses 885system.cpu.icache.tags.data_accesses 1313829498 # Number of data accesses 886system.cpu.icache.ReadReq_hits::cpu.inst 656912599 # number of ReadReq hits 887system.cpu.icache.ReadReq_hits::total 656912599 # number of ReadReq hits 888system.cpu.icache.demand_hits::cpu.inst 656912599 # number of demand (read+write) hits 889system.cpu.icache.demand_hits::total 656912599 # number of demand (read+write) hits 890system.cpu.icache.overall_hits::cpu.inst 656912599 # number of overall hits 891system.cpu.icache.overall_hits::total 656912599 # number of overall hits 892system.cpu.icache.ReadReq_misses::cpu.inst 1612 # number of ReadReq misses 893system.cpu.icache.ReadReq_misses::total 1612 # number of ReadReq misses 894system.cpu.icache.demand_misses::cpu.inst 1612 # number of demand (read+write) misses 895system.cpu.icache.demand_misses::total 1612 # number of demand (read+write) misses 896system.cpu.icache.overall_misses::cpu.inst 1612 # number of overall misses 897system.cpu.icache.overall_misses::total 1612 # number of overall misses 898system.cpu.icache.ReadReq_miss_latency::cpu.inst 102924516 # number of ReadReq miss cycles 899system.cpu.icache.ReadReq_miss_latency::total 102924516 # number of ReadReq miss cycles 900system.cpu.icache.demand_miss_latency::cpu.inst 102924516 # number of demand (read+write) miss cycles 901system.cpu.icache.demand_miss_latency::total 102924516 # number of demand (read+write) miss cycles 902system.cpu.icache.overall_miss_latency::cpu.inst 102924516 # number of overall miss cycles 903system.cpu.icache.overall_miss_latency::total 102924516 # number of overall miss cycles 904system.cpu.icache.ReadReq_accesses::cpu.inst 656914211 # number of ReadReq accesses(hits+misses) 905system.cpu.icache.ReadReq_accesses::total 656914211 # number of ReadReq accesses(hits+misses) 906system.cpu.icache.demand_accesses::cpu.inst 656914211 # number of demand (read+write) accesses 907system.cpu.icache.demand_accesses::total 656914211 # number of demand (read+write) accesses 908system.cpu.icache.overall_accesses::cpu.inst 656914211 # number of overall (read+write) accesses 909system.cpu.icache.overall_accesses::total 656914211 # number of overall (read+write) accesses 910system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 911system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 912system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 913system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 914system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 915system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 916system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63848.955335 # average ReadReq miss latency 917system.cpu.icache.ReadReq_avg_miss_latency::total 63848.955335 # average ReadReq miss latency 918system.cpu.icache.demand_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency 919system.cpu.icache.demand_avg_miss_latency::total 63848.955335 # average overall miss latency 920system.cpu.icache.overall_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency 921system.cpu.icache.overall_avg_miss_latency::total 63848.955335 # average overall miss latency 922system.cpu.icache.blocked_cycles::no_mshrs 17306 # number of cycles access was blocked 923system.cpu.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked 924system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked 925system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked 926system.cpu.icache.avg_blocked_cycles::no_mshrs 93.043011 # average number of cycles each access was blocked 927system.cpu.icache.avg_blocked_cycles::no_targets 38.375000 # average number of cycles each access was blocked 928system.cpu.icache.fast_writes 0 # number of fast writes performed 929system.cpu.icache.cache_copies 0 # number of cache copies performed 930system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits 931system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits 932system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits 933system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits 934system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits 935system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits 936system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses 937system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses 938system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses 939system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses 940system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses 941system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses 942system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76203217 # number of ReadReq MSHR miss cycles 943system.cpu.icache.ReadReq_mshr_miss_latency::total 76203217 # number of ReadReq MSHR miss cycles 944system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76203217 # number of demand (read+write) MSHR miss cycles 945system.cpu.icache.demand_mshr_miss_latency::total 76203217 # number of demand (read+write) MSHR miss cycles 946system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76203217 # number of overall MSHR miss cycles 947system.cpu.icache.overall_mshr_miss_latency::total 76203217 # number of overall MSHR miss cycles 948system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 949system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 950system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 951system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 952system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 953system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 954system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70820.833643 # average ReadReq mshr miss latency 955system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70820.833643 # average ReadReq mshr miss latency 956system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency 957system.cpu.icache.demand_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency 958system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency 959system.cpu.icache.overall_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency 960system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 961system.cpu.l2cache.prefetcher.num_hwpf_issued 10941726 # number of hwpf issued 962system.cpu.l2cache.prefetcher.pfIdentified 11630409 # number of prefetch candidates identified 963system.cpu.l2cache.prefetcher.pfBufferHit 431114 # number of redundant prefetches already in prefetch queue 964system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 965system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 966system.cpu.l2cache.prefetcher.pfSpanPage 4654951 # number of prefetches not generated due to page crossing 967system.cpu.l2cache.tags.replacements 4713207 # number of replacements 968system.cpu.l2cache.tags.tagsinuse 16130.406064 # Cycle average of tags in use 969system.cpu.l2cache.tags.total_refs 15325447 # Total number of references to valid blocks. 970system.cpu.l2cache.tags.sampled_refs 4729134 # Sample count of references to valid blocks. 971system.cpu.l2cache.tags.avg_refs 3.240646 # Average number of references to valid blocks. 972system.cpu.l2cache.tags.warmup_cycle 29468558500 # Cycle when the warmup percentage was hit. 973system.cpu.l2cache.tags.occ_blocks::writebacks 5233.732135 # Average occupied blocks per requestor 974system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.908605 # Average occupied blocks per requestor 975system.cpu.l2cache.tags.occ_blocks::cpu.data 7574.796716 # Average occupied blocks per requestor 976system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3302.968608 # Average occupied blocks per requestor 977system.cpu.l2cache.tags.occ_percent::writebacks 0.319442 # Average percentage of cache occupancy 978system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001154 # Average percentage of cache occupancy 979system.cpu.l2cache.tags.occ_percent::cpu.data 0.462329 # Average percentage of cache occupancy 980system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.201597 # Average percentage of cache occupancy 981system.cpu.l2cache.tags.occ_percent::total 0.984522 # Average percentage of cache occupancy 982system.cpu.l2cache.tags.occ_task_id_blocks::1022 731 # Occupied blocks per task id 983system.cpu.l2cache.tags.occ_task_id_blocks::1024 15196 # Occupied blocks per task id 984system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1022::1 525 # Occupied blocks per task id 986system.cpu.l2cache.tags.age_task_id_blocks_1022::3 201 # Occupied blocks per task id 987system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id 988system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2455 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1253 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9206 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1816 # Occupied blocks per task id 992system.cpu.l2cache.tags.occ_task_id_percent::1022 0.044617 # Percentage of cache occupancy per task id 993system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927490 # Percentage of cache occupancy per task id 994system.cpu.l2cache.tags.tag_accesses 356943997 # Number of tag accesses 995system.cpu.l2cache.tags.data_accesses 356943997 # Number of data accesses 996system.cpu.l2cache.ReadReq_hits::cpu.inst 43 # number of ReadReq hits 997system.cpu.l2cache.ReadReq_hits::cpu.data 11484174 # number of ReadReq hits 998system.cpu.l2cache.ReadReq_hits::total 11484217 # number of ReadReq hits 999system.cpu.l2cache.Writeback_hits::writebacks 4835251 # number of Writeback hits 1000system.cpu.l2cache.Writeback_hits::total 4835251 # number of Writeback hits 1001system.cpu.l2cache.ReadExReq_hits::cpu.data 1752141 # number of ReadExReq hits 1002system.cpu.l2cache.ReadExReq_hits::total 1752141 # number of ReadExReq hits 1003system.cpu.l2cache.demand_hits::cpu.inst 43 # number of demand (read+write) hits 1004system.cpu.l2cache.demand_hits::cpu.data 13236315 # number of demand (read+write) hits 1005system.cpu.l2cache.demand_hits::total 13236358 # number of demand (read+write) hits 1006system.cpu.l2cache.overall_hits::cpu.inst 43 # number of overall hits 1007system.cpu.l2cache.overall_hits::cpu.data 13236315 # number of overall hits 1008system.cpu.l2cache.overall_hits::total 13236358 # number of overall hits 1009system.cpu.l2cache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses 1010system.cpu.l2cache.ReadReq_misses::cpu.data 2784280 # number of ReadReq misses 1011system.cpu.l2cache.ReadReq_misses::total 2785313 # number of ReadReq misses 1012system.cpu.l2cache.ReadExReq_misses::cpu.data 985410 # number of ReadExReq misses 1013system.cpu.l2cache.ReadExReq_misses::total 985410 # number of ReadExReq misses 1014system.cpu.l2cache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses 1015system.cpu.l2cache.demand_misses::cpu.data 3769690 # number of demand (read+write) misses 1016system.cpu.l2cache.demand_misses::total 3770723 # number of demand (read+write) misses 1017system.cpu.l2cache.overall_misses::cpu.inst 1033 # number of overall misses 1018system.cpu.l2cache.overall_misses::cpu.data 3769690 # number of overall misses 1019system.cpu.l2cache.overall_misses::total 3770723 # number of overall misses 1020system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 75372729 # number of ReadReq miss cycles 1021system.cpu.l2cache.ReadReq_miss_latency::cpu.data 239047213138 # number of ReadReq miss cycles 1022system.cpu.l2cache.ReadReq_miss_latency::total 239122585867 # number of ReadReq miss cycles 1023system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100142345987 # number of ReadExReq miss cycles 1024system.cpu.l2cache.ReadExReq_miss_latency::total 100142345987 # number of ReadExReq miss cycles 1025system.cpu.l2cache.demand_miss_latency::cpu.inst 75372729 # number of demand (read+write) miss cycles 1026system.cpu.l2cache.demand_miss_latency::cpu.data 339189559125 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.demand_miss_latency::total 339264931854 # number of demand (read+write) miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.inst 75372729 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.data 339189559125 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::total 339264931854 # number of overall miss cycles 1031system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) 1032system.cpu.l2cache.ReadReq_accesses::cpu.data 14268454 # number of ReadReq accesses(hits+misses) 1033system.cpu.l2cache.ReadReq_accesses::total 14269530 # number of ReadReq accesses(hits+misses) 1034system.cpu.l2cache.Writeback_accesses::writebacks 4835251 # number of Writeback accesses(hits+misses) 1035system.cpu.l2cache.Writeback_accesses::total 4835251 # number of Writeback accesses(hits+misses) 1036system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737551 # number of ReadExReq accesses(hits+misses) 1037system.cpu.l2cache.ReadExReq_accesses::total 2737551 # number of ReadExReq accesses(hits+misses) 1038system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses 1039system.cpu.l2cache.demand_accesses::cpu.data 17006005 # number of demand (read+write) accesses 1040system.cpu.l2cache.demand_accesses::total 17007081 # number of demand (read+write) accesses 1041system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses 1042system.cpu.l2cache.overall_accesses::cpu.data 17006005 # number of overall (read+write) accesses 1043system.cpu.l2cache.overall_accesses::total 17007081 # number of overall (read+write) accesses 1044system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960037 # miss rate for ReadReq accesses 1045system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195135 # miss rate for ReadReq accesses 1046system.cpu.l2cache.ReadReq_miss_rate::total 0.195193 # miss rate for ReadReq accesses 1047system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359960 # miss rate for ReadExReq accesses 1048system.cpu.l2cache.ReadExReq_miss_rate::total 0.359960 # miss rate for ReadExReq accesses 1049system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960037 # miss rate for demand accesses 1050system.cpu.l2cache.demand_miss_rate::cpu.data 0.221668 # miss rate for demand accesses 1051system.cpu.l2cache.demand_miss_rate::total 0.221715 # miss rate for demand accesses 1052system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960037 # miss rate for overall accesses 1053system.cpu.l2cache.overall_miss_rate::cpu.data 0.221668 # miss rate for overall accesses 1054system.cpu.l2cache.overall_miss_rate::total 0.221715 # miss rate for overall accesses 1055system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72964.887706 # average ReadReq miss latency 1056system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.024946 # average ReadReq miss latency 1057system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.243960 # average ReadReq miss latency 1058system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101625.055547 # average ReadExReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101625.055547 # average ReadExReq miss latency 1060system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency 1062system.cpu.l2cache.demand_avg_miss_latency::total 89973.443251 # average overall miss latency 1063system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency 1064system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::total 89973.443251 # average overall miss latency 1066system.cpu.l2cache.blocked_cycles::no_mshrs 846 # number of cycles access was blocked 1067system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1068system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked 1069system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1070system.cpu.l2cache.avg_blocked_cycles::no_mshrs 211.500000 # average number of cycles each access was blocked 1071system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1072system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1073system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1074system.cpu.l2cache.writebacks::writebacks 1639072 # number of writebacks 1075system.cpu.l2cache.writebacks::total 1639072 # number of writebacks 1076system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 36084 # number of ReadReq MSHR hits 1077system.cpu.l2cache.ReadReq_mshr_hits::total 36084 # number of ReadReq MSHR hits 1078system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3647 # number of ReadExReq MSHR hits 1079system.cpu.l2cache.ReadExReq_mshr_hits::total 3647 # number of ReadExReq MSHR hits 1080system.cpu.l2cache.demand_mshr_hits::cpu.data 39731 # number of demand (read+write) MSHR hits 1081system.cpu.l2cache.demand_mshr_hits::total 39731 # number of demand (read+write) MSHR hits 1082system.cpu.l2cache.overall_mshr_hits::cpu.data 39731 # number of overall MSHR hits 1083system.cpu.l2cache.overall_mshr_hits::total 39731 # number of overall MSHR hits 1084system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1033 # number of ReadReq MSHR misses 1085system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748196 # number of ReadReq MSHR misses 1086system.cpu.l2cache.ReadReq_mshr_misses::total 2749229 # number of ReadReq MSHR misses 1087system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993723 # number of HardPFReq MSHR misses 1088system.cpu.l2cache.HardPFReq_mshr_misses::total 993723 # number of HardPFReq MSHR misses 1089system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981763 # number of ReadExReq MSHR misses 1090system.cpu.l2cache.ReadExReq_mshr_misses::total 981763 # number of ReadExReq MSHR misses 1091system.cpu.l2cache.demand_mshr_misses::cpu.inst 1033 # number of demand (read+write) MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::cpu.data 3729959 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.demand_mshr_misses::total 3730992 # number of demand (read+write) MSHR misses 1094system.cpu.l2cache.overall_mshr_misses::cpu.inst 1033 # number of overall MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.data 3729959 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993723 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::total 4724715 # number of overall MSHR misses 1098system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66585771 # number of ReadReq MSHR miss cycles 1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212846915589 # number of ReadReq MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212913501360 # number of ReadReq MSHR miss cycles 1101system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of HardPFReq MSHR miss cycles 1102system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 71046693133 # number of HardPFReq MSHR miss cycles 1103system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91372170669 # number of ReadExReq MSHR miss cycles 1104system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91372170669 # number of ReadExReq MSHR miss cycles 1105system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66585771 # number of demand (read+write) MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304219086258 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::total 304285672029 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66585771 # number of overall MSHR miss cycles 1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304219086258 # number of overall MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::total 375332365162 # number of overall MSHR miss cycles 1112system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for ReadReq accesses 1113system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192606 # mshr miss rate for ReadReq accesses 1114system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192664 # mshr miss rate for ReadReq accesses 1115system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1116system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1117system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358628 # mshr miss rate for ReadExReq accesses 1118system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358628 # mshr miss rate for ReadExReq accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for demand accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for demand accesses 1121system.cpu.l2cache.demand_mshr_miss_rate::total 0.219379 # mshr miss rate for demand accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for overall accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for overall accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1125system.cpu.l2cache.overall_mshr_miss_rate::total 0.277809 # mshr miss rate for overall accesses 1126system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64458.636012 # average ReadReq mshr miss latency 1127system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77449.685390 # average ReadReq mshr miss latency 1128system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77444.804111 # average ReadReq mshr miss latency 1129system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average HardPFReq mshr miss latency 1130system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71495.470199 # average HardPFReq mshr miss latency 1131system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93069.478753 # average ReadExReq mshr miss latency 1132system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93069.478753 # average ReadExReq mshr miss latency 1133system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency 1134system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency 1135system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81556.238134 # average overall mshr miss latency 1136system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency 1137system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79440.212830 # average overall mshr miss latency 1140system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1141system.cpu.toL2Bus.trans_dist::ReadReq 14269530 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::ReadResp 14269530 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::Writeback 4835251 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::HardPFReq 1300143 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::ReadExReq 2737551 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::ReadExResp 2737551 # Transaction distribution 1147system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2152 # Packet count per connected master and slave (bytes) 1148system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38847261 # Packet count per connected master and slave (bytes) 1149system.cpu.toL2Bus.pkt_count::total 38849413 # Packet count per connected master and slave (bytes) 1150system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68864 # Cumulative packet size per connected master and slave (bytes) 1151system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397840384 # Cumulative packet size per connected master and slave (bytes) 1152system.cpu.toL2Bus.pkt_size::total 1397909248 # Cumulative packet size per connected master and slave (bytes) 1153system.cpu.toL2Bus.snoops 1300143 # Total snoops (count) 1154system.cpu.toL2Bus.snoop_fanout::samples 23142477 # Request fanout histogram 1155system.cpu.toL2Bus.snoop_fanout::mean 3.056180 # Request fanout histogram 1156system.cpu.toL2Bus.snoop_fanout::stdev 0.230269 # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1159system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1160system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::3 21842334 94.38% 94.38% # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::4 1300143 5.62% 100.00% # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::total 23142477 # Request fanout histogram 1167system.cpu.toL2Bus.reqLayer0.occupancy 15756418748 # Layer occupancy (ticks) 1168system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) 1169system.cpu.toL2Bus.respLayer0.occupancy 1812271 # Layer occupancy (ticks) 1170system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1171system.cpu.toL2Bus.respLayer1.occupancy 26100835834 # Layer occupancy (ticks) 1172system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) 1173system.membus.trans_dist::ReadReq 3739202 # Transaction distribution 1174system.membus.trans_dist::ReadResp 3739202 # Transaction distribution 1175system.membus.trans_dist::Writeback 1639072 # Transaction distribution 1176system.membus.trans_dist::ReadExReq 982028 # Transaction distribution 1177system.membus.trans_dist::ReadExResp 982028 # Transaction distribution 1178system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11081532 # Packet count per connected master and slave (bytes) 1179system.membus.pkt_count::total 11081532 # Packet count per connected master and slave (bytes) 1180system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407059328 # Cumulative packet size per connected master and slave (bytes) 1181system.membus.pkt_size::total 407059328 # Cumulative packet size per connected master and slave (bytes) 1182system.membus.snoops 0 # Total snoops (count) 1183system.membus.snoop_fanout::samples 6360302 # Request fanout histogram 1184system.membus.snoop_fanout::mean 0 # Request fanout histogram 1185system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1186system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1187system.membus.snoop_fanout::0 6360302 100.00% 100.00% # Request fanout histogram 1188system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1189system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1190system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1191system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1192system.membus.snoop_fanout::total 6360302 # Request fanout histogram 1193system.membus.reqLayer0.occupancy 14493239223 # Layer occupancy (ticks) 1194system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) 1195system.membus.respLayer1.occupancy 25671846860 # Layer occupancy (ticks) 1196system.membus.respLayer1.utilization 3.3 # Layer utilization (%) 1197 1198---------- End Simulation Statistics ---------- 1199