stats.txt revision 10038:7eccd14e2610
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.533762 # Number of seconds simulated 4sim_ticks 533761922000 # Number of ticks simulated 5final_tick 533761922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 155948 # Simulator instruction rate (inst/s) 8host_op_rate 173972 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53891847 # Simulator tick rate (ticks/s) 10host_mem_usage 269768 # Number of bytes of host memory used 11host_seconds 9904.32 # Real time elapsed on the host 12sim_insts 1544563023 # Number of instructions simulated 13sim_ops 1723073835 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 143740736 # Number of bytes read from this memory 18system.physmem.bytes_read::total 143788352 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 70437056 # Number of bytes written to this memory 22system.physmem.bytes_written::total 70437056 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 2245949 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 2246693 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1100579 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1100579 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 89208 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 269297472 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 269386680 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 89208 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 89208 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 131963434 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 131963434 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 131963434 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 89208 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 269297472 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 401350114 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 2246694 # Number of read requests accepted 40system.physmem.writeReqs 1100579 # Number of write requests accepted 41system.physmem.readBursts 2246694 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 1100579 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 143750848 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 37568 # Total number of bytes read from write queue 45system.physmem.bytesWritten 70435904 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 143788416 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 70437056 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 587 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 139629 # Per bank write bursts 52system.physmem.perBankRdBursts::1 136292 # Per bank write bursts 53system.physmem.perBankRdBursts::2 133828 # Per bank write bursts 54system.physmem.perBankRdBursts::3 136435 # Per bank write bursts 55system.physmem.perBankRdBursts::4 134766 # Per bank write bursts 56system.physmem.perBankRdBursts::5 135151 # Per bank write bursts 57system.physmem.perBankRdBursts::6 136244 # Per bank write bursts 58system.physmem.perBankRdBursts::7 136309 # Per bank write bursts 59system.physmem.perBankRdBursts::8 143829 # Per bank write bursts 60system.physmem.perBankRdBursts::9 146501 # Per bank write bursts 61system.physmem.perBankRdBursts::10 144298 # Per bank write bursts 62system.physmem.perBankRdBursts::11 146295 # Per bank write bursts 63system.physmem.perBankRdBursts::12 145712 # Per bank write bursts 64system.physmem.perBankRdBursts::13 146106 # Per bank write bursts 65system.physmem.perBankRdBursts::14 142241 # Per bank write bursts 66system.physmem.perBankRdBursts::15 142471 # Per bank write bursts 67system.physmem.perBankWrBursts::0 69077 # Per bank write bursts 68system.physmem.perBankWrBursts::1 67426 # Per bank write bursts 69system.physmem.perBankWrBursts::2 65726 # Per bank write bursts 70system.physmem.perBankWrBursts::3 66343 # Per bank write bursts 71system.physmem.perBankWrBursts::4 66130 # Per bank write bursts 72system.physmem.perBankWrBursts::5 66357 # Per bank write bursts 73system.physmem.perBankWrBursts::6 67984 # Per bank write bursts 74system.physmem.perBankWrBursts::7 68878 # Per bank write bursts 75system.physmem.perBankWrBursts::8 70373 # Per bank write bursts 76system.physmem.perBankWrBursts::9 70997 # Per bank write bursts 77system.physmem.perBankWrBursts::10 70493 # Per bank write bursts 78system.physmem.perBankWrBursts::11 70981 # Per bank write bursts 79system.physmem.perBankWrBursts::12 70269 # Per bank write bursts 80system.physmem.perBankWrBursts::13 70812 # Per bank write bursts 81system.physmem.perBankWrBursts::14 69646 # Per bank write bursts 82system.physmem.perBankWrBursts::15 69069 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 2 # Number of times write queue was full causing retry 85system.physmem.totGap 533761847000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 2246694 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 1100579 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 1621644 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 445219 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 135704 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 43528 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 49060 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 49089 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 49071 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 49076 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 49104 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 49085 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 49081 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 49079 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 49128 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 49123 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 49158 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 49172 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 49261 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 49504 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 49899 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 50373 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 52060 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 52016 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 51492 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 52976 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 52139 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 2343 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 326 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see 164system.physmem.bytesPerActivate::samples 2078319 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::mean 103.049035 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::gmean 79.954808 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::stdev 184.695982 # Bytes accessed per row activation 168system.physmem.bytesPerActivate::64-65 1660986 79.92% 79.92% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::128-129 227336 10.94% 90.86% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::192-193 68882 3.31% 94.17% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::256-257 37662 1.81% 95.98% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::320-321 25035 1.20% 97.19% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::384-385 12093 0.58% 97.77% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::448-449 8438 0.41% 98.18% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::512-513 8141 0.39% 98.57% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::576-577 4391 0.21% 98.78% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::640-641 3442 0.17% 98.95% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::704-705 2829 0.14% 99.08% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::768-769 1974 0.09% 99.18% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::832-833 1676 0.08% 99.26% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::896-897 1442 0.07% 99.33% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::960-961 1174 0.06% 99.38% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1024-1025 1106 0.05% 99.44% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1088-1089 969 0.05% 99.48% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1152-1153 858 0.04% 99.52% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1216-1217 735 0.04% 99.56% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1280-1281 673 0.03% 99.59% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1344-1345 651 0.03% 99.62% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1408-1409 3128 0.15% 99.77% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1472-1473 421 0.02% 99.79% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1536-1537 240 0.01% 99.81% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1600-1601 179 0.01% 99.81% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1664-1665 200 0.01% 99.82% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1728-1729 207 0.01% 99.83% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1792-1793 498 0.02% 99.86% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.86% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.87% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1984-1985 136 0.01% 99.88% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2048-2049 128 0.01% 99.88% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2112-2113 89 0.00% 99.89% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2176-2177 121 0.01% 99.89% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2240-2241 102 0.00% 99.90% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2304-2305 117 0.01% 99.90% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2368-2369 77 0.00% 99.91% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2432-2433 74 0.00% 99.91% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2496-2497 59 0.00% 99.91% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2560-2561 70 0.00% 99.92% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2624-2625 60 0.00% 99.92% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2688-2689 54 0.00% 99.92% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2752-2753 55 0.00% 99.93% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2816-2817 76 0.00% 99.93% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2880-2881 49 0.00% 99.93% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2944-2945 45 0.00% 99.93% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3008-3009 33 0.00% 99.94% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3072-3073 66 0.00% 99.94% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3136-3137 39 0.00% 99.94% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3200-3201 33 0.00% 99.94% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3264-3265 36 0.00% 99.94% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3328-3329 47 0.00% 99.95% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3392-3393 27 0.00% 99.95% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.95% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3520-3521 22 0.00% 99.95% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3584-3585 27 0.00% 99.95% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3648-3649 21 0.00% 99.95% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3712-3713 25 0.00% 99.95% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.95% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3840-3841 40 0.00% 99.96% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.96% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3968-3969 18 0.00% 99.96% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4032-4033 16 0.00% 99.96% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4096-4097 30 0.00% 99.96% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4160-4161 10 0.00% 99.96% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4224-4225 21 0.00% 99.96% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4288-4289 16 0.00% 99.96% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4352-4353 36 0.00% 99.96% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4416-4417 15 0.00% 99.97% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.97% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4608-4609 17 0.00% 99.97% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4736-4737 17 0.00% 99.97% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4800-4801 17 0.00% 99.97% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4864-4865 32 0.00% 99.97% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4928-4929 10 0.00% 99.97% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5056-5057 15 0.00% 99.97% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5120-5121 31 0.00% 99.97% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.98% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5248-5249 10 0.00% 99.98% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5312-5313 9 0.00% 99.98% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5376-5377 206 0.01% 99.99% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.99% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.99% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.99% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.99% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5888-5889 22 0.00% 99.99% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5952-5953 6 0.00% 99.99% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.99% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.99% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.99% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.99% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.99% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6400-6401 20 0.00% 99.99% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.99% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.99% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6656-6657 37 0.00% 99.99% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.99% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.99% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6976-6977 3 0.00% 99.99% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.99% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.99% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7168-7169 13 0.00% 99.99% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.99% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7296-7297 1 0.00% 99.99% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.99% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7616-7617 4 0.00% 100.00% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7872-7873 1 0.00% 100.00% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7936-7937 6 0.00% 100.00% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::8064-8065 4 0.00% 100.00% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8192-8193 88 0.00% 100.00% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::total 2078319 # Bytes accessed per row activation 291system.physmem.totQLat 32815970750 # Total ticks spent queuing 292system.physmem.totMemAccLat 104054627000 # Total ticks spent from burst creation until serviced by the DRAM 293system.physmem.totBusLat 11230535000 # Total ticks spent in databus transfers 294system.physmem.totBankLat 60008121250 # Total ticks spent accessing banks 295system.physmem.avgQLat 14610.15 # Average queueing delay per DRAM burst 296system.physmem.avgBankLat 26716.50 # Average bank access latency per DRAM burst 297system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 298system.physmem.avgMemAccLat 46326.66 # Average memory access latency per DRAM burst 299system.physmem.avgRdBW 269.32 # Average DRAM read bandwidth in MiByte/s 300system.physmem.avgWrBW 131.96 # Average achieved write bandwidth in MiByte/s 301system.physmem.avgRdBWSys 269.39 # Average system read bandwidth in MiByte/s 302system.physmem.avgWrBWSys 131.96 # Average system write bandwidth in MiByte/s 303system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 304system.physmem.busUtil 3.13 # Data bus utilization in percentage 305system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads 306system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes 307system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing 308system.physmem.avgWrQLen 10.33 # Average write queue length when enqueuing 309system.physmem.readRowHits 932061 # Number of row buffer hits during reads 310system.physmem.writeRowHits 336288 # Number of row buffer hits during writes 311system.physmem.readRowHitRate 41.50 # Row buffer hit rate for reads 312system.physmem.writeRowHitRate 30.56 # Row buffer hit rate for writes 313system.physmem.avgGap 159461.70 # Average gap between requests 314system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined 315system.physmem.prechargeAllPercent 5.96 # Percentage of time for which DRAM has all the banks in precharge state 316system.membus.throughput 401350114 # Throughput (bytes/s) 317system.membus.trans_dist::ReadReq 1420099 # Transaction distribution 318system.membus.trans_dist::ReadResp 1420098 # Transaction distribution 319system.membus.trans_dist::Writeback 1100579 # Transaction distribution 320system.membus.trans_dist::ReadExReq 826595 # Transaction distribution 321system.membus.trans_dist::ReadExResp 826595 # Transaction distribution 322system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593966 # Packet count per connected master and slave (bytes) 323system.membus.pkt_count::total 5593966 # Packet count per connected master and slave (bytes) 324system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214225408 # Cumulative packet size per connected master and slave (bytes) 325system.membus.tot_pkt_size::total 214225408 # Cumulative packet size per connected master and slave (bytes) 326system.membus.data_through_bus 214225408 # Total data (bytes) 327system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 328system.membus.reqLayer0.occupancy 12926034750 # Layer occupancy (ticks) 329system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 330system.membus.respLayer1.occupancy 21084340000 # Layer occupancy (ticks) 331system.membus.respLayer1.utilization 4.0 # Layer utilization (%) 332system.cpu_clk_domain.clock 500 # Clock period in ticks 333system.cpu.branchPred.lookups 303426723 # Number of BP lookups 334system.cpu.branchPred.condPredicted 249665263 # Number of conditional branches predicted 335system.cpu.branchPred.condIncorrect 15197446 # Number of conditional branches incorrect 336system.cpu.branchPred.BTBLookups 174885075 # Number of BTB lookups 337system.cpu.branchPred.BTBHits 161766496 # Number of BTB hits 338system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 339system.cpu.branchPred.BTBHitPct 92.498743 # BTB Hit Percentage 340system.cpu.branchPred.usedRAS 17552924 # Number of times the RAS was used to get a target. 341system.cpu.branchPred.RASInCorrect 181 # Number of incorrect RAS predictions. 342system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 343system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 344system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 345system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 346system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 347system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 348system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 349system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 350system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 351system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 352system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 353system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 354system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 355system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 358system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 359system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 360system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 361system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 362system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 363system.cpu.dtb.inst_hits 0 # ITB inst hits 364system.cpu.dtb.inst_misses 0 # ITB inst misses 365system.cpu.dtb.read_hits 0 # DTB read hits 366system.cpu.dtb.read_misses 0 # DTB read misses 367system.cpu.dtb.write_hits 0 # DTB write hits 368system.cpu.dtb.write_misses 0 # DTB write misses 369system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.dtb.read_accesses 0 # DTB read accesses 379system.cpu.dtb.write_accesses 0 # DTB write accesses 380system.cpu.dtb.inst_accesses 0 # ITB inst accesses 381system.cpu.dtb.hits 0 # DTB hits 382system.cpu.dtb.misses 0 # DTB misses 383system.cpu.dtb.accesses 0 # DTB accesses 384system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 385system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 386system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 387system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 388system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 389system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 390system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 391system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 392system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 393system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 394system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 395system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 396system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 397system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 398system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 399system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 400system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 401system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 402system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 403system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 404system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 405system.cpu.itb.inst_hits 0 # ITB inst hits 406system.cpu.itb.inst_misses 0 # ITB inst misses 407system.cpu.itb.read_hits 0 # DTB read hits 408system.cpu.itb.read_misses 0 # DTB read misses 409system.cpu.itb.write_hits 0 # DTB write hits 410system.cpu.itb.write_misses 0 # DTB write misses 411system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 412system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 413system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 414system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 415system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 416system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 417system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 418system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 419system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 420system.cpu.itb.read_accesses 0 # DTB read accesses 421system.cpu.itb.write_accesses 0 # DTB write accesses 422system.cpu.itb.inst_accesses 0 # ITB inst accesses 423system.cpu.itb.hits 0 # DTB hits 424system.cpu.itb.misses 0 # DTB misses 425system.cpu.itb.accesses 0 # DTB accesses 426system.cpu.workload.num_syscalls 46 # Number of system calls 427system.cpu.numCycles 1067523845 # number of cpu cycles simulated 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 430system.cpu.fetch.icacheStallCycles 299169160 # Number of cycles fetch is stalled on an Icache miss 431system.cpu.fetch.Insts 2189552617 # Number of instructions fetch has processed 432system.cpu.fetch.Branches 303426723 # Number of branches that fetch encountered 433system.cpu.fetch.predictedBranches 179319420 # Number of branches that fetch has predicted taken 434system.cpu.fetch.Cycles 435766349 # Number of cycles fetch has run and was not squashing or blocked 435system.cpu.fetch.SquashCycles 88088140 # Number of cycles fetch has spent squashing 436system.cpu.fetch.BlockedCycles 164108706 # Number of cycles fetch has spent blocked 437system.cpu.fetch.PendingTrapStallCycles 249 # Number of stall cycles due to pending traps 438system.cpu.fetch.CacheLines 289578845 # Number of cache lines fetched 439system.cpu.fetch.IcacheSquashes 5989031 # Number of outstanding Icache misses that were squashed 440system.cpu.fetch.rateDist::samples 969003000 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::mean 2.499478 # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::stdev 3.206212 # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::0 533236766 55.03% 55.03% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::1 25461427 2.63% 57.66% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::2 39064672 4.03% 61.69% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::3 48308848 4.99% 66.67% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::4 43759414 4.52% 71.19% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::5 46393042 4.79% 75.98% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::6 38404129 3.96% 79.94% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::7 18940871 1.95% 81.90% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::8 175433831 18.10% 100.00% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.rateDist::total 969003000 # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.branchRate 0.284234 # Number of branch fetches per cycle 458system.cpu.fetch.rate 2.051057 # Number of inst fetches per cycle 459system.cpu.decode.IdleCycles 331406137 # Number of cycles decode is idle 460system.cpu.decode.BlockedCycles 141956827 # Number of cycles decode is blocked 461system.cpu.decode.RunCycles 405364012 # Number of cycles decode is running 462system.cpu.decode.UnblockCycles 20318148 # Number of cycles decode is unblocking 463system.cpu.decode.SquashCycles 69957876 # Number of cycles decode is squashing 464system.cpu.decode.BranchResolved 46020737 # Number of times decode resolved a branch 465system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction 466system.cpu.decode.DecodedInsts 2369052643 # Number of instructions handled by decode 467system.cpu.decode.SquashedInsts 2441 # Number of squashed instructions handled by decode 468system.cpu.rename.SquashCycles 69957876 # Number of cycles rename is squashing 469system.cpu.rename.IdleCycles 354906744 # Number of cycles rename is idle 470system.cpu.rename.BlockCycles 70525275 # Number of cycles rename is blocking 471system.cpu.rename.serializeStallCycles 17150 # count of cycles rename stalled for serializing inst 472system.cpu.rename.RunCycles 400533325 # Number of cycles rename is running 473system.cpu.rename.UnblockCycles 73062630 # Number of cycles rename is unblocking 474system.cpu.rename.RenamedInsts 2306235389 # Number of instructions processed by rename 475system.cpu.rename.ROBFullEvents 151230 # Number of times rename has blocked due to ROB full 476system.cpu.rename.IQFullEvents 5013278 # Number of times rename has blocked due to IQ full 477system.cpu.rename.LSQFullEvents 60135849 # Number of times rename has blocked due to LSQ full 478system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers 479system.cpu.rename.RenamedOperands 2282078057 # Number of destination operands rename has renamed 480system.cpu.rename.RenameLookups 10649208068 # Number of register rename lookups that rename has made 481system.cpu.rename.int_rename_lookups 9763247621 # Number of integer rename lookups 482system.cpu.rename.fp_rename_lookups 332 # Number of floating rename lookups 483system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed 484system.cpu.rename.UndoneMaps 575758127 # Number of HB maps that are undone due to squashing 485system.cpu.rename.serializingInsts 542 # count of serializing insts renamed 486system.cpu.rename.tempSerializingInsts 539 # count of temporary serializing insts renamed 487system.cpu.rename.skidInsts 160926093 # count of insts added to the skid buffer 488system.cpu.memDep0.insertedLoads 624728249 # Number of loads inserted to the mem dependence unit. 489system.cpu.memDep0.insertedStores 220785157 # Number of stores inserted to the mem dependence unit. 490system.cpu.memDep0.conflictingLoads 86065935 # Number of conflicting loads. 491system.cpu.memDep0.conflictingStores 71218939 # Number of conflicting stores. 492system.cpu.iq.iqInstsAdded 2202289570 # Number of instructions added to the IQ (excludes non-spec) 493system.cpu.iq.iqNonSpecInstsAdded 584 # Number of non-speculative instructions added to the IQ 494system.cpu.iq.iqInstsIssued 2018746767 # Number of instructions issued 495system.cpu.iq.iqSquashedInstsIssued 4010968 # Number of squashed instructions issued 496system.cpu.iq.iqSquashedInstsExamined 474628449 # Number of squashed instructions iterated over during squash; mainly for profiling 497system.cpu.iq.iqSquashedOperandsExamined 1127376318 # Number of squashed operands that are examined and possibly removed from graph 498system.cpu.iq.iqSquashedNonSpecRemoved 414 # Number of squashed non-spec instructions that were removed 499system.cpu.iq.issued_per_cycle::samples 969003000 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::mean 2.083324 # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::stdev 1.906240 # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::0 286111139 29.53% 29.53% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::1 153618591 15.85% 45.38% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::2 160911412 16.61% 61.99% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::3 120366979 12.42% 74.41% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::4 123454210 12.74% 87.15% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::5 73801369 7.62% 94.76% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::6 38320646 3.95% 98.72% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::7 9892378 1.02% 99.74% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::8 2526276 0.26% 100.00% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::total 969003000 # Number of insts issued each cycle 516system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 517system.cpu.iq.fu_full::IntAlu 901909 3.77% 3.77% # attempts to use FU when none available 518system.cpu.iq.fu_full::IntMult 5511 0.02% 3.79% # attempts to use FU when none available 519system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available 546system.cpu.iq.fu_full::MemRead 18267438 76.34% 80.13% # attempts to use FU when none available 547system.cpu.iq.fu_full::MemWrite 4754077 19.87% 100.00% # attempts to use FU when none available 548system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 549system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 550system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 551system.cpu.iq.FU_type_0::IntAlu 1236913920 61.27% 61.27% # Type of FU issued 552system.cpu.iq.FU_type_0::IntMult 925199 0.05% 61.32% # Type of FU issued 553system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatMult 6 0.00% 61.32% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued 580system.cpu.iq.FU_type_0::MemRead 587869811 29.12% 90.44% # Type of FU issued 581system.cpu.iq.FU_type_0::MemWrite 193037777 9.56% 100.00% # Type of FU issued 582system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 583system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 584system.cpu.iq.FU_type_0::total 2018746767 # Type of FU issued 585system.cpu.iq.rate 1.891055 # Inst issue rate 586system.cpu.iq.fu_busy_cnt 23928935 # FU busy when requested 587system.cpu.iq.fu_busy_rate 0.011853 # FU busy rate (busy events/executed inst) 588system.cpu.iq.int_inst_queue_reads 5034436167 # Number of integer instruction queue reads 589system.cpu.iq.int_inst_queue_writes 2677107941 # Number of integer instruction queue writes 590system.cpu.iq.int_inst_queue_wakeup_accesses 1957305969 # Number of integer instruction queue wakeup accesses 591system.cpu.iq.fp_inst_queue_reads 270 # Number of floating instruction queue reads 592system.cpu.iq.fp_inst_queue_writes 526 # Number of floating instruction queue writes 593system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses 594system.cpu.iq.int_alu_accesses 2042675566 # Number of integer alu accesses 595system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses 596system.cpu.iew.lsq.thread0.forwLoads 64599963 # Number of loads that had data forwarded from stores 597system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 598system.cpu.iew.lsq.thread0.squashedLoads 138801480 # Number of loads squashed 599system.cpu.iew.lsq.thread0.ignoredResponses 270727 # Number of memory responses ignored because the instruction is squashed 600system.cpu.iew.lsq.thread0.memOrderViolation 192405 # Number of memory ordering violations 601system.cpu.iew.lsq.thread0.squashedStores 45938112 # Number of stores squashed 602system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 603system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 604system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled 605system.cpu.iew.lsq.thread0.cacheBlocked 4771665 # Number of times an access to memory failed due to the cache being blocked 606system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 607system.cpu.iew.iewSquashCycles 69957876 # Number of cycles IEW is squashing 608system.cpu.iew.iewBlockCycles 33460674 # Number of cycles IEW is blocking 609system.cpu.iew.iewUnblockCycles 1602950 # Number of cycles IEW is unblocking 610system.cpu.iew.iewDispatchedInsts 2202290297 # Number of instructions dispatched to IQ 611system.cpu.iew.iewDispSquashedInsts 7880065 # Number of squashed instructions skipped by dispatch 612system.cpu.iew.iewDispLoadInsts 624728249 # Number of dispatched load instructions 613system.cpu.iew.iewDispStoreInsts 220785157 # Number of dispatched store instructions 614system.cpu.iew.iewDispNonSpecInsts 522 # Number of dispatched non-speculative instructions 615system.cpu.iew.iewIQFullEvents 477902 # Number of times the IQ has become full, causing a stall 616system.cpu.iew.iewLSQFullEvents 97314 # Number of times the LSQ has become full, causing a stall 617system.cpu.iew.memOrderViolationEvents 192405 # Number of memory order violations 618system.cpu.iew.predictedTakenIncorrect 8143338 # Number of branches that were predicted taken incorrectly 619system.cpu.iew.predictedNotTakenIncorrect 9598007 # Number of branches that were predicted not taken incorrectly 620system.cpu.iew.branchMispredicts 17741345 # Number of branch mispredicts detected at execute 621system.cpu.iew.iewExecutedInsts 1988017569 # Number of executed instructions 622system.cpu.iew.iewExecLoadInsts 574014855 # Number of load instructions executed 623system.cpu.iew.iewExecSquashedInsts 30729198 # Number of squashed instructions skipped in execute 624system.cpu.iew.exec_swp 0 # number of swp insts executed 625system.cpu.iew.exec_nop 143 # number of nop insts executed 626system.cpu.iew.exec_refs 764181270 # number of memory reference insts executed 627system.cpu.iew.exec_branches 238318975 # Number of branches executed 628system.cpu.iew.exec_stores 190166415 # Number of stores executed 629system.cpu.iew.exec_rate 1.862270 # Inst execution rate 630system.cpu.iew.wb_sent 1965726867 # cumulative count of insts sent to commit 631system.cpu.iew.wb_count 1957306072 # cumulative count of insts written-back 632system.cpu.iew.wb_producers 1295394361 # num instructions producing a value 633system.cpu.iew.wb_consumers 2059160488 # num instructions consuming a value 634system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 635system.cpu.iew.wb_rate 1.833501 # insts written-back per cycle 636system.cpu.iew.wb_fanout 0.629089 # average fanout of values written-back 637system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 638system.cpu.commit.commitSquashedInsts 479315418 # The number of squashed insts skipped by commit 639system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 640system.cpu.commit.branchMispredicts 15196786 # The number of times a branch was mispredicted 641system.cpu.commit.committed_per_cycle::samples 899045124 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::mean 1.916560 # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::stdev 2.718243 # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::0 410462230 45.66% 45.66% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::1 193303811 21.50% 67.16% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::2 72810970 8.10% 75.26% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::3 35275316 3.92% 79.18% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::4 18883906 2.10% 81.28% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::5 30780783 3.42% 84.70% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::6 19963318 2.22% 86.92% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::7 11415613 1.27% 88.19% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::8 106149177 11.81% 100.00% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::total 899045124 # Number of insts commited each cycle 658system.cpu.commit.committedInsts 1544563041 # Number of instructions committed 659system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed 660system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 661system.cpu.commit.refs 660773814 # Number of memory references committed 662system.cpu.commit.loads 485926769 # Number of loads committed 663system.cpu.commit.membars 62 # Number of memory barriers committed 664system.cpu.commit.branches 213462426 # Number of branches committed 665system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 666system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. 667system.cpu.commit.function_calls 13665177 # Number of function calls committed. 668system.cpu.commit.bw_lim_events 106149177 # number cycles where commit BW limit reached 669system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 670system.cpu.rob.rob_reads 2995284619 # The number of ROB reads 671system.cpu.rob.rob_writes 4474886700 # The number of ROB writes 672system.cpu.timesIdled 1153694 # Number of times that the entire CPU went into an idle state and unscheduled itself 673system.cpu.idleCycles 98520845 # Total number of cycles that the CPU has spent unscheduled due to idling 674system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 675system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated 676system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated 677system.cpu.cpi 0.691149 # CPI: Cycles Per Instruction 678system.cpu.cpi_total 0.691149 # CPI: Total CPI of All Threads 679system.cpu.ipc 1.446865 # IPC: Instructions Per Cycle 680system.cpu.ipc_total 1.446865 # IPC: Total IPC of All Threads 681system.cpu.int_regfile_reads 9956057659 # number of integer regfile reads 682system.cpu.int_regfile_writes 1937206435 # number of integer regfile writes 683system.cpu.fp_regfile_reads 98 # number of floating regfile reads 684system.cpu.fp_regfile_writes 94 # number of floating regfile writes 685system.cpu.misc_regfile_reads 737611057 # number of misc regfile reads 686system.cpu.misc_regfile_writes 124 # number of misc regfile writes 687system.cpu.toL2Bus.throughput 1604912326 # Throughput (bytes/s) 688system.cpu.toL2Bus.trans_dist::ReadReq 7709455 # Transaction distribution 689system.cpu.toL2Bus.trans_dist::ReadResp 7709454 # Transaction distribution 690system.cpu.toL2Bus.trans_dist::Writeback 3782070 # Transaction distribution 691system.cpu.toL2Bus.trans_dist::ReadExReq 1893493 # Transaction distribution 692system.cpu.toL2Bus.trans_dist::ReadExResp 1893493 # Transaction distribution 693system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1550 # Packet count per connected master and slave (bytes) 694system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986415 # Packet count per connected master and slave (bytes) 695system.cpu.toL2Bus.pkt_count::total 22987965 # Packet count per connected master and slave (bytes) 696system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49600 # Cumulative packet size per connected master and slave (bytes) 697system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856591488 # Cumulative packet size per connected master and slave (bytes) 698system.cpu.toL2Bus.tot_pkt_size::total 856641088 # Cumulative packet size per connected master and slave (bytes) 699system.cpu.toL2Bus.data_through_bus 856641088 # Total data (bytes) 700system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 701system.cpu.toL2Bus.reqLayer0.occupancy 10474747083 # Layer occupancy (ticks) 702system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) 703system.cpu.toL2Bus.respLayer0.occupancy 1295998 # Layer occupancy (ticks) 704system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 705system.cpu.toL2Bus.respLayer1.occupancy 14769977492 # Layer occupancy (ticks) 706system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) 707system.cpu.icache.tags.replacements 19 # number of replacements 708system.cpu.icache.tags.tagsinuse 628.273269 # Cycle average of tags in use 709system.cpu.icache.tags.total_refs 289577640 # Total number of references to valid blocks. 710system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks. 711system.cpu.icache.tags.avg_refs 373648.567742 # Average number of references to valid blocks. 712system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 713system.cpu.icache.tags.occ_blocks::cpu.inst 628.273269 # Average occupied blocks per requestor 714system.cpu.icache.tags.occ_percent::cpu.inst 0.306774 # Average percentage of cache occupancy 715system.cpu.icache.tags.occ_percent::total 0.306774 # Average percentage of cache occupancy 716system.cpu.icache.tags.occ_task_id_blocks::1024 756 # Occupied blocks per task id 717system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 718system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 719system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 720system.cpu.icache.tags.age_task_id_blocks_1024::4 727 # Occupied blocks per task id 721system.cpu.icache.tags.occ_task_id_percent::1024 0.369141 # Percentage of cache occupancy per task id 722system.cpu.icache.tags.tag_accesses 579158465 # Number of tag accesses 723system.cpu.icache.tags.data_accesses 579158465 # Number of data accesses 724system.cpu.icache.ReadReq_hits::cpu.inst 289577640 # number of ReadReq hits 725system.cpu.icache.ReadReq_hits::total 289577640 # number of ReadReq hits 726system.cpu.icache.demand_hits::cpu.inst 289577640 # number of demand (read+write) hits 727system.cpu.icache.demand_hits::total 289577640 # number of demand (read+write) hits 728system.cpu.icache.overall_hits::cpu.inst 289577640 # number of overall hits 729system.cpu.icache.overall_hits::total 289577640 # number of overall hits 730system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses 731system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses 732system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses 733system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses 734system.cpu.icache.overall_misses::cpu.inst 1205 # number of overall misses 735system.cpu.icache.overall_misses::total 1205 # number of overall misses 736system.cpu.icache.ReadReq_miss_latency::cpu.inst 81284498 # number of ReadReq miss cycles 737system.cpu.icache.ReadReq_miss_latency::total 81284498 # number of ReadReq miss cycles 738system.cpu.icache.demand_miss_latency::cpu.inst 81284498 # number of demand (read+write) miss cycles 739system.cpu.icache.demand_miss_latency::total 81284498 # number of demand (read+write) miss cycles 740system.cpu.icache.overall_miss_latency::cpu.inst 81284498 # number of overall miss cycles 741system.cpu.icache.overall_miss_latency::total 81284498 # number of overall miss cycles 742system.cpu.icache.ReadReq_accesses::cpu.inst 289578845 # number of ReadReq accesses(hits+misses) 743system.cpu.icache.ReadReq_accesses::total 289578845 # number of ReadReq accesses(hits+misses) 744system.cpu.icache.demand_accesses::cpu.inst 289578845 # number of demand (read+write) accesses 745system.cpu.icache.demand_accesses::total 289578845 # number of demand (read+write) accesses 746system.cpu.icache.overall_accesses::cpu.inst 289578845 # number of overall (read+write) accesses 747system.cpu.icache.overall_accesses::total 289578845 # number of overall (read+write) accesses 748system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 749system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 750system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 751system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 752system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 753system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses 754system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67456.014938 # average ReadReq miss latency 755system.cpu.icache.ReadReq_avg_miss_latency::total 67456.014938 # average ReadReq miss latency 756system.cpu.icache.demand_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency 757system.cpu.icache.demand_avg_miss_latency::total 67456.014938 # average overall miss latency 758system.cpu.icache.overall_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency 759system.cpu.icache.overall_avg_miss_latency::total 67456.014938 # average overall miss latency 760system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked 761system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked 763system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 764system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked 765system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.cpu.icache.fast_writes 0 # number of fast writes performed 767system.cpu.icache.cache_copies 0 # number of cache copies performed 768system.cpu.icache.ReadReq_mshr_hits::cpu.inst 430 # number of ReadReq MSHR hits 769system.cpu.icache.ReadReq_mshr_hits::total 430 # number of ReadReq MSHR hits 770system.cpu.icache.demand_mshr_hits::cpu.inst 430 # number of demand (read+write) MSHR hits 771system.cpu.icache.demand_mshr_hits::total 430 # number of demand (read+write) MSHR hits 772system.cpu.icache.overall_mshr_hits::cpu.inst 430 # number of overall MSHR hits 773system.cpu.icache.overall_mshr_hits::total 430 # number of overall MSHR hits 774system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses 775system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses 776system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses 777system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses 778system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses 779system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses 780system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55854002 # number of ReadReq MSHR miss cycles 781system.cpu.icache.ReadReq_mshr_miss_latency::total 55854002 # number of ReadReq MSHR miss cycles 782system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55854002 # number of demand (read+write) MSHR miss cycles 783system.cpu.icache.demand_mshr_miss_latency::total 55854002 # number of demand (read+write) MSHR miss cycles 784system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55854002 # number of overall MSHR miss cycles 785system.cpu.icache.overall_mshr_miss_latency::total 55854002 # number of overall MSHR miss cycles 786system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 787system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 788system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 789system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 790system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 791system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 792system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72069.680000 # average ReadReq mshr miss latency 793system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72069.680000 # average ReadReq mshr miss latency 794system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72069.680000 # average overall mshr miss latency 795system.cpu.icache.demand_avg_mshr_miss_latency::total 72069.680000 # average overall mshr miss latency 796system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72069.680000 # average overall mshr miss latency 797system.cpu.icache.overall_avg_mshr_miss_latency::total 72069.680000 # average overall mshr miss latency 798system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 799system.cpu.l2cache.tags.replacements 2214011 # number of replacements 800system.cpu.l2cache.tags.tagsinuse 31532.870200 # Cycle average of tags in use 801system.cpu.l2cache.tags.total_refs 9247003 # Total number of references to valid blocks. 802system.cpu.l2cache.tags.sampled_refs 2243785 # Sample count of references to valid blocks. 803system.cpu.l2cache.tags.avg_refs 4.121163 # Average number of references to valid blocks. 804system.cpu.l2cache.tags.warmup_cycle 21623958250 # Cycle when the warmup percentage was hit. 805system.cpu.l2cache.tags.occ_blocks::writebacks 14303.376165 # Average occupied blocks per requestor 806system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.256077 # Average occupied blocks per requestor 807system.cpu.l2cache.tags.occ_blocks::cpu.data 17209.237958 # Average occupied blocks per requestor 808system.cpu.l2cache.tags.occ_percent::writebacks 0.436504 # Average percentage of cache occupancy 809system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000618 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_percent::cpu.data 0.525184 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_percent::total 0.962307 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_task_id_blocks::1024 29774 # Occupied blocks per task id 813system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1894 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23751 # Occupied blocks per task id 817system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3958 # Occupied blocks per task id 818system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908630 # Percentage of cache occupancy per task id 819system.cpu.l2cache.tags.tag_accesses 111217422 # Number of tag accesses 820system.cpu.l2cache.tags.data_accesses 111217422 # Number of data accesses 821system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits 822system.cpu.l2cache.ReadReq_hits::cpu.data 6289318 # number of ReadReq hits 823system.cpu.l2cache.ReadReq_hits::total 6289347 # number of ReadReq hits 824system.cpu.l2cache.Writeback_hits::writebacks 3782070 # number of Writeback hits 825system.cpu.l2cache.Writeback_hits::total 3782070 # number of Writeback hits 826system.cpu.l2cache.ReadExReq_hits::cpu.data 1066898 # number of ReadExReq hits 827system.cpu.l2cache.ReadExReq_hits::total 1066898 # number of ReadExReq hits 828system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits 829system.cpu.l2cache.demand_hits::cpu.data 7356216 # number of demand (read+write) hits 830system.cpu.l2cache.demand_hits::total 7356245 # number of demand (read+write) hits 831system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits 832system.cpu.l2cache.overall_hits::cpu.data 7356216 # number of overall hits 833system.cpu.l2cache.overall_hits::total 7356245 # number of overall hits 834system.cpu.l2cache.ReadReq_misses::cpu.inst 746 # number of ReadReq misses 835system.cpu.l2cache.ReadReq_misses::cpu.data 1419362 # number of ReadReq misses 836system.cpu.l2cache.ReadReq_misses::total 1420108 # number of ReadReq misses 837system.cpu.l2cache.ReadExReq_misses::cpu.data 826595 # number of ReadExReq misses 838system.cpu.l2cache.ReadExReq_misses::total 826595 # number of ReadExReq misses 839system.cpu.l2cache.demand_misses::cpu.inst 746 # number of demand (read+write) misses 840system.cpu.l2cache.demand_misses::cpu.data 2245957 # number of demand (read+write) misses 841system.cpu.l2cache.demand_misses::total 2246703 # number of demand (read+write) misses 842system.cpu.l2cache.overall_misses::cpu.inst 746 # number of overall misses 843system.cpu.l2cache.overall_misses::cpu.data 2245957 # number of overall misses 844system.cpu.l2cache.overall_misses::total 2246703 # number of overall misses 845system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 54783500 # number of ReadReq miss cycles 846system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125692113250 # number of ReadReq miss cycles 847system.cpu.l2cache.ReadReq_miss_latency::total 125746896750 # number of ReadReq miss cycles 848system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76318094500 # number of ReadExReq miss cycles 849system.cpu.l2cache.ReadExReq_miss_latency::total 76318094500 # number of ReadExReq miss cycles 850system.cpu.l2cache.demand_miss_latency::cpu.inst 54783500 # number of demand (read+write) miss cycles 851system.cpu.l2cache.demand_miss_latency::cpu.data 202010207750 # number of demand (read+write) miss cycles 852system.cpu.l2cache.demand_miss_latency::total 202064991250 # number of demand (read+write) miss cycles 853system.cpu.l2cache.overall_miss_latency::cpu.inst 54783500 # number of overall miss cycles 854system.cpu.l2cache.overall_miss_latency::cpu.data 202010207750 # number of overall miss cycles 855system.cpu.l2cache.overall_miss_latency::total 202064991250 # number of overall miss cycles 856system.cpu.l2cache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses) 857system.cpu.l2cache.ReadReq_accesses::cpu.data 7708680 # number of ReadReq accesses(hits+misses) 858system.cpu.l2cache.ReadReq_accesses::total 7709455 # number of ReadReq accesses(hits+misses) 859system.cpu.l2cache.Writeback_accesses::writebacks 3782070 # number of Writeback accesses(hits+misses) 860system.cpu.l2cache.Writeback_accesses::total 3782070 # number of Writeback accesses(hits+misses) 861system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893493 # number of ReadExReq accesses(hits+misses) 862system.cpu.l2cache.ReadExReq_accesses::total 1893493 # number of ReadExReq accesses(hits+misses) 863system.cpu.l2cache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses 864system.cpu.l2cache.demand_accesses::cpu.data 9602173 # number of demand (read+write) accesses 865system.cpu.l2cache.demand_accesses::total 9602948 # number of demand (read+write) accesses 866system.cpu.l2cache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses 867system.cpu.l2cache.overall_accesses::cpu.data 9602173 # number of overall (read+write) accesses 868system.cpu.l2cache.overall_accesses::total 9602948 # number of overall (read+write) accesses 869system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962581 # miss rate for ReadReq accesses 870system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184125 # miss rate for ReadReq accesses 871system.cpu.l2cache.ReadReq_miss_rate::total 0.184203 # miss rate for ReadReq accesses 872system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436545 # miss rate for ReadExReq accesses 873system.cpu.l2cache.ReadExReq_miss_rate::total 0.436545 # miss rate for ReadExReq accesses 874system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962581 # miss rate for demand accesses 875system.cpu.l2cache.demand_miss_rate::cpu.data 0.233901 # miss rate for demand accesses 876system.cpu.l2cache.demand_miss_rate::total 0.233960 # miss rate for demand accesses 877system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962581 # miss rate for overall accesses 878system.cpu.l2cache.overall_miss_rate::cpu.data 0.233901 # miss rate for overall accesses 879system.cpu.l2cache.overall_miss_rate::total 0.233960 # miss rate for overall accesses 880system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73436.327078 # average ReadReq miss latency 881system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88555.360260 # average ReadReq miss latency 882system.cpu.l2cache.ReadReq_avg_miss_latency::total 88547.418048 # average ReadReq miss latency 883system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92328.279871 # average ReadExReq miss latency 884system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92328.279871 # average ReadExReq miss latency 885system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.327078 # average overall miss latency 886system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89943.933811 # average overall miss latency 887system.cpu.l2cache.demand_avg_miss_latency::total 89938.452590 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.327078 # average overall miss latency 889system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89943.933811 # average overall miss latency 890system.cpu.l2cache.overall_avg_miss_latency::total 89938.452590 # average overall miss latency 891system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 894system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 895system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 896system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 897system.cpu.l2cache.fast_writes 0 # number of fast writes performed 898system.cpu.l2cache.cache_copies 0 # number of cache copies performed 899system.cpu.l2cache.writebacks::writebacks 1100579 # number of writebacks 900system.cpu.l2cache.writebacks::total 1100579 # number of writebacks 901system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 902system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits 903system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 904system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 905system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits 906system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits 907system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 908system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits 909system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits 910system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses 911system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419355 # number of ReadReq MSHR misses 912system.cpu.l2cache.ReadReq_mshr_misses::total 1420099 # number of ReadReq MSHR misses 913system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826595 # number of ReadExReq MSHR misses 914system.cpu.l2cache.ReadExReq_mshr_misses::total 826595 # number of ReadExReq MSHR misses 915system.cpu.l2cache.demand_mshr_misses::cpu.inst 744 # number of demand (read+write) MSHR misses 916system.cpu.l2cache.demand_mshr_misses::cpu.data 2245950 # number of demand (read+write) MSHR misses 917system.cpu.l2cache.demand_mshr_misses::total 2246694 # number of demand (read+write) MSHR misses 918system.cpu.l2cache.overall_mshr_misses::cpu.inst 744 # number of overall MSHR misses 919system.cpu.l2cache.overall_mshr_misses::cpu.data 2245950 # number of overall MSHR misses 920system.cpu.l2cache.overall_mshr_misses::total 2246694 # number of overall MSHR misses 921system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45263000 # number of ReadReq MSHR miss cycles 922system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107889512500 # number of ReadReq MSHR miss cycles 923system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107934775500 # number of ReadReq MSHR miss cycles 924system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65933341000 # number of ReadExReq MSHR miss cycles 925system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65933341000 # number of ReadExReq MSHR miss cycles 926system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45263000 # number of demand (read+write) MSHR miss cycles 927system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173822853500 # number of demand (read+write) MSHR miss cycles 928system.cpu.l2cache.demand_mshr_miss_latency::total 173868116500 # number of demand (read+write) MSHR miss cycles 929system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45263000 # number of overall MSHR miss cycles 930system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173822853500 # number of overall MSHR miss cycles 931system.cpu.l2cache.overall_mshr_miss_latency::total 173868116500 # number of overall MSHR miss cycles 932system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for ReadReq accesses 933system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184124 # mshr miss rate for ReadReq accesses 934system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184202 # mshr miss rate for ReadReq accesses 935system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436545 # mshr miss rate for ReadExReq accesses 936system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436545 # mshr miss rate for ReadExReq accesses 937system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for demand accesses 938system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233900 # mshr miss rate for demand accesses 939system.cpu.l2cache.demand_mshr_miss_rate::total 0.233959 # mshr miss rate for demand accesses 940system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for overall accesses 941system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233900 # mshr miss rate for overall accesses 942system.cpu.l2cache.overall_mshr_miss_rate::total 0.233959 # mshr miss rate for overall accesses 943system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60837.365591 # average ReadReq mshr miss latency 944system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76013.056987 # average ReadReq mshr miss latency 945system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76005.106334 # average ReadReq mshr miss latency 946system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79764.988900 # average ReadExReq mshr miss latency 947system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79764.988900 # average ReadExReq mshr miss latency 948system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60837.365591 # average overall mshr miss latency 949system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77393.910595 # average overall mshr miss latency 950system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77388.427841 # average overall mshr miss latency 951system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60837.365591 # average overall mshr miss latency 952system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77393.910595 # average overall mshr miss latency 953system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77388.427841 # average overall mshr miss latency 954system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 955system.cpu.dcache.tags.replacements 9598076 # number of replacements 956system.cpu.dcache.tags.tagsinuse 4088.041397 # Cycle average of tags in use 957system.cpu.dcache.tags.total_refs 656012597 # Total number of references to valid blocks. 958system.cpu.dcache.tags.sampled_refs 9602172 # Sample count of references to valid blocks. 959system.cpu.dcache.tags.avg_refs 68.319188 # Average number of references to valid blocks. 960system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit. 961system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041397 # Average occupied blocks per requestor 962system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy 963system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy 964system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 965system.cpu.dcache.tags.age_task_id_blocks_1024::0 635 # Occupied blocks per task id 966system.cpu.dcache.tags.age_task_id_blocks_1024::1 2403 # Occupied blocks per task id 967system.cpu.dcache.tags.age_task_id_blocks_1024::2 1057 # Occupied blocks per task id 968system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 969system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 970system.cpu.dcache.tags.tag_accesses 1355899932 # Number of tag accesses 971system.cpu.dcache.tags.data_accesses 1355899932 # Number of data accesses 972system.cpu.dcache.ReadReq_hits::cpu.data 489056209 # number of ReadReq hits 973system.cpu.dcache.ReadReq_hits::total 489056209 # number of ReadReq hits 974system.cpu.dcache.WriteReq_hits::cpu.data 166956265 # number of WriteReq hits 975system.cpu.dcache.WriteReq_hits::total 166956265 # number of WriteReq hits 976system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits 977system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits 978system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 979system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 980system.cpu.dcache.demand_hits::cpu.data 656012474 # number of demand (read+write) hits 981system.cpu.dcache.demand_hits::total 656012474 # number of demand (read+write) hits 982system.cpu.dcache.overall_hits::cpu.data 656012474 # number of overall hits 983system.cpu.dcache.overall_hits::total 656012474 # number of overall hits 984system.cpu.dcache.ReadReq_misses::cpu.data 11506498 # number of ReadReq misses 985system.cpu.dcache.ReadReq_misses::total 11506498 # number of ReadReq misses 986system.cpu.dcache.WriteReq_misses::cpu.data 5629782 # number of WriteReq misses 987system.cpu.dcache.WriteReq_misses::total 5629782 # number of WriteReq misses 988system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 989system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 990system.cpu.dcache.demand_misses::cpu.data 17136280 # number of demand (read+write) misses 991system.cpu.dcache.demand_misses::total 17136280 # number of demand (read+write) misses 992system.cpu.dcache.overall_misses::cpu.data 17136280 # number of overall misses 993system.cpu.dcache.overall_misses::total 17136280 # number of overall misses 994system.cpu.dcache.ReadReq_miss_latency::cpu.data 363307841237 # number of ReadReq miss cycles 995system.cpu.dcache.ReadReq_miss_latency::total 363307841237 # number of ReadReq miss cycles 996system.cpu.dcache.WriteReq_miss_latency::cpu.data 307618244019 # number of WriteReq miss cycles 997system.cpu.dcache.WriteReq_miss_latency::total 307618244019 # number of WriteReq miss cycles 998system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles 999system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles 1000system.cpu.dcache.demand_miss_latency::cpu.data 670926085256 # number of demand (read+write) miss cycles 1001system.cpu.dcache.demand_miss_latency::total 670926085256 # number of demand (read+write) miss cycles 1002system.cpu.dcache.overall_miss_latency::cpu.data 670926085256 # number of overall miss cycles 1003system.cpu.dcache.overall_miss_latency::total 670926085256 # number of overall miss cycles 1004system.cpu.dcache.ReadReq_accesses::cpu.data 500562707 # number of ReadReq accesses(hits+misses) 1005system.cpu.dcache.ReadReq_accesses::total 500562707 # number of ReadReq accesses(hits+misses) 1006system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 1007system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 1008system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) 1009system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) 1010system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 1011system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 1012system.cpu.dcache.demand_accesses::cpu.data 673148754 # number of demand (read+write) accesses 1013system.cpu.dcache.demand_accesses::total 673148754 # number of demand (read+write) accesses 1014system.cpu.dcache.overall_accesses::cpu.data 673148754 # number of overall (read+write) accesses 1015system.cpu.dcache.overall_accesses::total 673148754 # number of overall (read+write) accesses 1016system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022987 # miss rate for ReadReq accesses 1017system.cpu.dcache.ReadReq_miss_rate::total 0.022987 # miss rate for ReadReq accesses 1018system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032620 # miss rate for WriteReq accesses 1019system.cpu.dcache.WriteReq_miss_rate::total 0.032620 # miss rate for WriteReq accesses 1020system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses 1021system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses 1022system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses 1023system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses 1024system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses 1025system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses 1026system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31574.145430 # average ReadReq miss latency 1027system.cpu.dcache.ReadReq_avg_miss_latency::total 31574.145430 # average ReadReq miss latency 1028system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54641.235490 # average WriteReq miss latency 1029system.cpu.dcache.WriteReq_avg_miss_latency::total 54641.235490 # average WriteReq miss latency 1030system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency 1031system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency 1032system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency 1033system.cpu.dcache.demand_avg_miss_latency::total 39152.376435 # average overall miss latency 1034system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency 1035system.cpu.dcache.overall_avg_miss_latency::total 39152.376435 # average overall miss latency 1036system.cpu.dcache.blocked_cycles::no_mshrs 24574937 # number of cycles access was blocked 1037system.cpu.dcache.blocked_cycles::no_targets 3988182 # number of cycles access was blocked 1038system.cpu.dcache.blocked::no_mshrs 1212192 # number of cycles access was blocked 1039system.cpu.dcache.blocked::no_targets 65130 # number of cycles access was blocked 1040system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.273139 # average number of cycles each access was blocked 1041system.cpu.dcache.avg_blocked_cycles::no_targets 61.234178 # average number of cycles each access was blocked 1042system.cpu.dcache.fast_writes 0 # number of fast writes performed 1043system.cpu.dcache.cache_copies 0 # number of cache copies performed 1044system.cpu.dcache.writebacks::writebacks 3782070 # number of writebacks 1045system.cpu.dcache.writebacks::total 3782070 # number of writebacks 1046system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3797817 # number of ReadReq MSHR hits 1047system.cpu.dcache.ReadReq_mshr_hits::total 3797817 # number of ReadReq MSHR hits 1048system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736290 # number of WriteReq MSHR hits 1049system.cpu.dcache.WriteReq_mshr_hits::total 3736290 # number of WriteReq MSHR hits 1050system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 1051system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 1052system.cpu.dcache.demand_mshr_hits::cpu.data 7534107 # number of demand (read+write) MSHR hits 1053system.cpu.dcache.demand_mshr_hits::total 7534107 # number of demand (read+write) MSHR hits 1054system.cpu.dcache.overall_mshr_hits::cpu.data 7534107 # number of overall MSHR hits 1055system.cpu.dcache.overall_mshr_hits::total 7534107 # number of overall MSHR hits 1056system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708681 # number of ReadReq MSHR misses 1057system.cpu.dcache.ReadReq_mshr_misses::total 7708681 # number of ReadReq MSHR misses 1058system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893492 # number of WriteReq MSHR misses 1059system.cpu.dcache.WriteReq_mshr_misses::total 1893492 # number of WriteReq MSHR misses 1060system.cpu.dcache.demand_mshr_misses::cpu.data 9602173 # number of demand (read+write) MSHR misses 1061system.cpu.dcache.demand_mshr_misses::total 9602173 # number of demand (read+write) MSHR misses 1062system.cpu.dcache.overall_mshr_misses::cpu.data 9602173 # number of overall MSHR misses 1063system.cpu.dcache.overall_mshr_misses::total 9602173 # number of overall MSHR misses 1064system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198180916008 # number of ReadReq MSHR miss cycles 1065system.cpu.dcache.ReadReq_mshr_miss_latency::total 198180916008 # number of ReadReq MSHR miss cycles 1066system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89373429339 # number of WriteReq MSHR miss cycles 1067system.cpu.dcache.WriteReq_mshr_miss_latency::total 89373429339 # number of WriteReq MSHR miss cycles 1068system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287554345347 # number of demand (read+write) MSHR miss cycles 1069system.cpu.dcache.demand_mshr_miss_latency::total 287554345347 # number of demand (read+write) MSHR miss cycles 1070system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287554345347 # number of overall MSHR miss cycles 1071system.cpu.dcache.overall_mshr_miss_latency::total 287554345347 # number of overall MSHR miss cycles 1072system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015400 # mshr miss rate for ReadReq accesses 1073system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015400 # mshr miss rate for ReadReq accesses 1074system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses 1075system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses 1076system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses 1077system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses 1078system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses 1079system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses 1080system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25708.797135 # average ReadReq mshr miss latency 1081system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25708.797135 # average ReadReq mshr miss latency 1082system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47200.320540 # average WriteReq mshr miss latency 1083system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47200.320540 # average WriteReq mshr miss latency 1084system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency 1085system.cpu.dcache.demand_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency 1086system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency 1087system.cpu.dcache.overall_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency 1088system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1089 1090---------- End Simulation Statistics ---------- 1091