stats.txt revision 11507
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.116866 # Number of seconds simulated 4sim_ticks 1116865668500 # Number of ticks simulated 5final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 243832 # Simulator instruction rate (inst/s) 8host_op_rate 262692 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 176313668 # Simulator tick rate (ticks/s) 10host_mem_usage 266900 # Number of bytes of host memory used 11host_seconds 6334.54 # Real time elapsed on the host 12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory 18system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory 22system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 2045808 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 44868 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 117231388 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 44868 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 44868 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 44868 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 117231388 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 2046591 # Number of read requests accepted 40system.physmem.writeReqs 1050123 # Number of write requests accepted 41system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 130898176 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 83648 # Total number of bytes read from write queue 45system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 1307 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 127279 # Per bank write bursts 52system.physmem.perBankRdBursts::1 124661 # Per bank write bursts 53system.physmem.perBankRdBursts::2 121601 # Per bank write bursts 54system.physmem.perBankRdBursts::3 123656 # Per bank write bursts 55system.physmem.perBankRdBursts::4 122620 # Per bank write bursts 56system.physmem.perBankRdBursts::5 122679 # Per bank write bursts 57system.physmem.perBankRdBursts::6 123247 # Per bank write bursts 58system.physmem.perBankRdBursts::7 123770 # Per bank write bursts 59system.physmem.perBankRdBursts::8 131396 # Per bank write bursts 60system.physmem.perBankRdBursts::9 133511 # Per bank write bursts 61system.physmem.perBankRdBursts::10 132081 # Per bank write bursts 62system.physmem.perBankRdBursts::11 133308 # Per bank write bursts 63system.physmem.perBankRdBursts::12 133249 # Per bank write bursts 64system.physmem.perBankRdBursts::13 133362 # Per bank write bursts 65system.physmem.perBankRdBursts::14 129309 # Per bank write bursts 66system.physmem.perBankRdBursts::15 129555 # Per bank write bursts 67system.physmem.perBankWrBursts::0 66136 # Per bank write bursts 68system.physmem.perBankWrBursts::1 64410 # Per bank write bursts 69system.physmem.perBankWrBursts::2 62576 # Per bank write bursts 70system.physmem.perBankWrBursts::3 63006 # Per bank write bursts 71system.physmem.perBankWrBursts::4 63000 # Per bank write bursts 72system.physmem.perBankWrBursts::5 63100 # Per bank write bursts 73system.physmem.perBankWrBursts::6 64443 # Per bank write bursts 74system.physmem.perBankWrBursts::7 65436 # Per bank write bursts 75system.physmem.perBankWrBursts::8 67310 # Per bank write bursts 76system.physmem.perBankWrBursts::9 67797 # Per bank write bursts 77system.physmem.perBankWrBursts::10 67549 # Per bank write bursts 78system.physmem.perBankWrBursts::11 67882 # Per bank write bursts 79system.physmem.perBankWrBursts::12 67326 # Per bank write bursts 80system.physmem.perBankWrBursts::13 67793 # Per bank write bursts 81system.physmem.perBankWrBursts::14 66482 # Per bank write bursts 82system.physmem.perBankWrBursts::15 65854 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 1116865574000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 2046591 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 1050123 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 1916619 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 128648 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 32746 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 33984 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 56911 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 61204 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 61629 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 61690 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 61591 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 61663 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 61651 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 61697 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 61747 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 61696 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 62170 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 62557 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 62067 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 62573 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 61138 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 84 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 5 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 1910138 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 103.711175 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 81.836423 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 125.540224 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 1485349 77.76% 77.76% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 305158 15.98% 93.74% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 52532 2.75% 96.49% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 21047 1.10% 97.59% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 13374 0.70% 98.29% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 7565 0.40% 98.69% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 5491 0.29% 98.97% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 5162 0.27% 99.24% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 14460 0.76% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 1910138 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 61136 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 33.411672 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 159.590236 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 61090 99.92% 99.92% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 21 0.03% 99.96% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::total 61136 # Reads before turning the bus around for writes 223system.physmem.wrPerTurnAround::samples 61136 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::mean 17.176459 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::gmean 17.141461 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::stdev 1.097536 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::16 27008 44.18% 44.18% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::17 1128 1.85% 46.02% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::18 28688 46.92% 92.95% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::19 3895 6.37% 99.32% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::20 363 0.59% 99.91% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::21 46 0.08% 99.99% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::22 6 0.01% 100.00% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::total 61136 # Writes before turning the bus around for reads 237system.physmem.totQLat 38124700750 # Total ticks spent queuing 238system.physmem.totMemAccLat 76473775750 # Total ticks spent from burst creation until serviced by the DRAM 239system.physmem.totBusLat 10226420000 # Total ticks spent in databus transfers 240system.physmem.avgQLat 18640.30 # Average queueing delay per DRAM burst 241system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 242system.physmem.avgMemAccLat 37390.30 # Average memory access latency per DRAM burst 243system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s 244system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s 245system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s 246system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s 247system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 248system.physmem.busUtil 1.39 # Data bus utilization in percentage 249system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads 250system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 251system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 252system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing 253system.physmem.readRowHits 773341 # Number of row buffer hits during reads 254system.physmem.writeRowHits 411895 # Number of row buffer hits during writes 255system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads 256system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes 257system.physmem.avgGap 360661.52 # Average gap between requests 258system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined 259system.physmem_0.actEnergy 7039078200 # Energy for activate commands per rank (pJ) 260system.physmem_0.preEnergy 3840766875 # Energy for precharge commands per rank (pJ) 261system.physmem_0.readEnergy 7717881600 # Energy for read commands per rank (pJ) 262system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) 263system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) 264system.physmem_0.actBackEnergy 420697412235 # Energy for active background per rank (pJ) 265system.physmem_0.preBackEnergy 301083150000 # Energy for precharge background per rank (pJ) 266system.physmem_0.totalEnergy 816644588670 # Total energy per rank (pJ) 267system.physmem_0.averagePower 731.196952 # Core power per rank (mW) 268system.physmem_0.memoryStateTime::IDLE 498171344000 # Time in different power states 269system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states 270system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.physmem_0.memoryStateTime::ACT 581396539000 # Time in different power states 272system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 273system.physmem_1.actEnergy 7401549960 # Energy for activate commands per rank (pJ) 274system.physmem_1.preEnergy 4038544125 # Energy for precharge commands per rank (pJ) 275system.physmem_1.readEnergy 8234959200 # Energy for read commands per rank (pJ) 276system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) 277system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) 278system.physmem_1.actBackEnergy 429293377035 # Energy for active background per rank (pJ) 279system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ) 280system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ) 281system.physmem_1.averagePower 733.256935 # Core power per rank (mW) 282system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states 283system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states 284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states 286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.cpu.branchPred.lookups 239639355 # Number of BP lookups 288system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 296system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups. 297system.cpu.branchPred.indirectHits 230 # Number of indirect target hits. 298system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. 299system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. 300system.cpu_clk_domain.clock 500 # Clock period in ticks 301system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 310system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 311system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 312system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 313system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 314system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 315system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 316system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 317system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 319system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 320system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 321system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 322system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 323system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 324system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 325system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 326system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 327system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 328system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 329system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 330system.cpu.dtb.walker.walks 0 # Table walker walks requested 331system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.inst_hits 0 # ITB inst hits 339system.cpu.dtb.inst_misses 0 # ITB inst misses 340system.cpu.dtb.read_hits 0 # DTB read hits 341system.cpu.dtb.read_misses 0 # DTB read misses 342system.cpu.dtb.write_hits 0 # DTB write hits 343system.cpu.dtb.write_misses 0 # DTB write misses 344system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 345system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 346system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 347system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 348system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 349system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 350system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 351system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.dtb.read_accesses 0 # DTB read accesses 354system.cpu.dtb.write_accesses 0 # DTB write accesses 355system.cpu.dtb.inst_accesses 0 # ITB inst accesses 356system.cpu.dtb.hits 0 # DTB hits 357system.cpu.dtb.misses 0 # DTB misses 358system.cpu.dtb.accesses 0 # DTB accesses 359system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 368system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 369system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 370system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 371system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 372system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 373system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 374system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 375system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 376system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 377system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 378system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 379system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 380system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 381system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 382system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 383system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 384system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 385system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 386system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 387system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 388system.cpu.itb.walker.walks 0 # Table walker walks requested 389system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.inst_hits 0 # ITB inst hits 397system.cpu.itb.inst_misses 0 # ITB inst misses 398system.cpu.itb.read_hits 0 # DTB read hits 399system.cpu.itb.read_misses 0 # DTB read misses 400system.cpu.itb.write_hits 0 # DTB write hits 401system.cpu.itb.write_misses 0 # DTB write misses 402system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 403system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 404system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 405system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 406system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 407system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 408system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 409system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 410system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu.itb.read_accesses 0 # DTB read accesses 412system.cpu.itb.write_accesses 0 # DTB write accesses 413system.cpu.itb.inst_accesses 0 # ITB inst accesses 414system.cpu.itb.hits 0 # DTB hits 415system.cpu.itb.misses 0 # DTB misses 416system.cpu.itb.accesses 0 # DTB accesses 417system.cpu.workload.num_syscalls 46 # Number of system calls 418system.cpu.numCycles 2233731337 # number of cpu cycles simulated 419system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 420system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 421system.cpu.committedInsts 1544563088 # Number of instructions committed 422system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed 423system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit 424system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 425system.cpu.cpi 1.446190 # CPI: cycles per instruction 426system.cpu.ipc 0.691472 # IPC: instructions per cycle 427system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 428system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction 429system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 430system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 431system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 432system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 433system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 434system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 435system.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 436system.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 437system.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 438system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 439system.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 440system.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 441system.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 442system.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 443system.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 444system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 445system.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 446system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 447system.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 448system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 449system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 450system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 451system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 452system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 453system.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction 454system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 455system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 456system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 457system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 458system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction 459system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 460system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 461system.cpu.op_class_0::total 1664032481 # Class of committed instruction 462system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked 463system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped 464system.cpu.dcache.tags.replacements 9221041 # number of replacements 465system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use 466system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. 467system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks. 468system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks. 469system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. 470system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor 471system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy 472system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy 473system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 474system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id 475system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id 476system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id 477system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 478system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 479system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses 480system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses 481system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits 482system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits 483system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits 484system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits 485system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 486system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 487system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 488system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 489system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 490system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 491system.cpu.dcache.demand_hits::cpu.data 624218805 # number of demand (read+write) hits 492system.cpu.dcache.demand_hits::total 624218805 # number of demand (read+write) hits 493system.cpu.dcache.overall_hits::cpu.data 624218806 # number of overall hits 494system.cpu.dcache.overall_hits::total 624218806 # number of overall hits 495system.cpu.dcache.ReadReq_misses::cpu.data 7334498 # number of ReadReq misses 496system.cpu.dcache.ReadReq_misses::total 7334498 # number of ReadReq misses 497system.cpu.dcache.WriteReq_misses::cpu.data 2254974 # number of WriteReq misses 498system.cpu.dcache.WriteReq_misses::total 2254974 # number of WriteReq misses 499system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 500system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 501system.cpu.dcache.demand_misses::cpu.data 9589472 # number of demand (read+write) misses 502system.cpu.dcache.demand_misses::total 9589472 # number of demand (read+write) misses 503system.cpu.dcache.overall_misses::cpu.data 9589474 # number of overall misses 504system.cpu.dcache.overall_misses::total 9589474 # number of overall misses 505system.cpu.dcache.ReadReq_miss_latency::cpu.data 190926660000 # number of ReadReq miss cycles 506system.cpu.dcache.ReadReq_miss_latency::total 190926660000 # number of ReadReq miss cycles 507system.cpu.dcache.WriteReq_miss_latency::cpu.data 109083916000 # number of WriteReq miss cycles 508system.cpu.dcache.WriteReq_miss_latency::total 109083916000 # number of WriteReq miss cycles 509system.cpu.dcache.demand_miss_latency::cpu.data 300010576000 # number of demand (read+write) miss cycles 510system.cpu.dcache.demand_miss_latency::total 300010576000 # number of demand (read+write) miss cycles 511system.cpu.dcache.overall_miss_latency::cpu.data 300010576000 # number of overall miss cycles 512system.cpu.dcache.overall_miss_latency::total 300010576000 # number of overall miss cycles 513system.cpu.dcache.ReadReq_accesses::cpu.data 461222230 # number of ReadReq accesses(hits+misses) 514system.cpu.dcache.ReadReq_accesses::total 461222230 # number of ReadReq accesses(hits+misses) 515system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 516system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 517system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) 518system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) 519system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 520system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 521system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 522system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 523system.cpu.dcache.demand_accesses::cpu.data 633808277 # number of demand (read+write) accesses 524system.cpu.dcache.demand_accesses::total 633808277 # number of demand (read+write) accesses 525system.cpu.dcache.overall_accesses::cpu.data 633808280 # number of overall (read+write) accesses 526system.cpu.dcache.overall_accesses::total 633808280 # number of overall (read+write) accesses 527system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses 528system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses 529system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses 530system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses 531system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses 532system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses 533system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses 534system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses 535system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses 536system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses 537system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.319390 # average ReadReq miss latency 538system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.319390 # average ReadReq miss latency 539system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48374.799887 # average WriteReq miss latency 540system.cpu.dcache.WriteReq_avg_miss_latency::total 48374.799887 # average WriteReq miss latency 541system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.411334 # average overall miss latency 542system.cpu.dcache.demand_avg_miss_latency::total 31285.411334 # average overall miss latency 543system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809 # average overall miss latency 544system.cpu.dcache.overall_avg_miss_latency::total 31285.404809 # average overall miss latency 545system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 546system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 549system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 550system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks 552system.cpu.dcache.writebacks::total 3684567 # number of writebacks 553system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits 554system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits 555system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364121 # number of WriteReq MSHR hits 556system.cpu.dcache.WriteReq_mshr_hits::total 364121 # number of WriteReq MSHR hits 557system.cpu.dcache.demand_mshr_hits::cpu.data 364336 # number of demand (read+write) MSHR hits 558system.cpu.dcache.demand_mshr_hits::total 364336 # number of demand (read+write) MSHR hits 559system.cpu.dcache.overall_mshr_hits::cpu.data 364336 # number of overall MSHR hits 560system.cpu.dcache.overall_mshr_hits::total 364336 # number of overall MSHR hits 561system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334283 # number of ReadReq MSHR misses 562system.cpu.dcache.ReadReq_mshr_misses::total 7334283 # number of ReadReq MSHR misses 563system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890853 # number of WriteReq MSHR misses 564system.cpu.dcache.WriteReq_mshr_misses::total 1890853 # number of WriteReq MSHR misses 565system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 566system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 567system.cpu.dcache.demand_mshr_misses::cpu.data 9225136 # number of demand (read+write) MSHR misses 568system.cpu.dcache.demand_mshr_misses::total 9225136 # number of demand (read+write) MSHR misses 569system.cpu.dcache.overall_mshr_misses::cpu.data 9225137 # number of overall MSHR misses 570system.cpu.dcache.overall_mshr_misses::total 9225137 # number of overall MSHR misses 571system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183586477500 # number of ReadReq MSHR miss cycles 572system.cpu.dcache.ReadReq_mshr_miss_latency::total 183586477500 # number of ReadReq MSHR miss cycles 573system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84779361000 # number of WriteReq MSHR miss cycles 574system.cpu.dcache.WriteReq_mshr_miss_latency::total 84779361000 # number of WriteReq MSHR miss cycles 575system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles 576system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles 577system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268365838500 # number of demand (read+write) MSHR miss cycles 578system.cpu.dcache.demand_mshr_miss_latency::total 268365838500 # number of demand (read+write) MSHR miss cycles 579system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268365912500 # number of overall MSHR miss cycles 580system.cpu.dcache.overall_mshr_miss_latency::total 268365912500 # number of overall MSHR miss cycles 581system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses 582system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses 583system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 584system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 585system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses 586system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses 587system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for demand accesses 588system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses 589system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses 590system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses 591system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.278109 # average ReadReq mshr miss latency 592system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.278109 # average ReadReq mshr miss latency 593system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency 594system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency 595system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency 596system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency 597system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency 598system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency 599system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency 600system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency 601system.cpu.icache.tags.replacements 29 # number of replacements 602system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use 603system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. 604system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. 605system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks. 606system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 607system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor 608system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy 610system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id 614system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id 615system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses 616system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses 617system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits 618system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits 619system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits 620system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits 621system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits 622system.cpu.icache.overall_hits::total 465281510 # number of overall hits 623system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses 624system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses 625system.cpu.icache.demand_misses::cpu.inst 819 # number of demand (read+write) misses 626system.cpu.icache.demand_misses::total 819 # number of demand (read+write) misses 627system.cpu.icache.overall_misses::cpu.inst 819 # number of overall misses 628system.cpu.icache.overall_misses::total 819 # number of overall misses 629system.cpu.icache.ReadReq_miss_latency::cpu.inst 62402500 # number of ReadReq miss cycles 630system.cpu.icache.ReadReq_miss_latency::total 62402500 # number of ReadReq miss cycles 631system.cpu.icache.demand_miss_latency::cpu.inst 62402500 # number of demand (read+write) miss cycles 632system.cpu.icache.demand_miss_latency::total 62402500 # number of demand (read+write) miss cycles 633system.cpu.icache.overall_miss_latency::cpu.inst 62402500 # number of overall miss cycles 634system.cpu.icache.overall_miss_latency::total 62402500 # number of overall miss cycles 635system.cpu.icache.ReadReq_accesses::cpu.inst 465282329 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.ReadReq_accesses::total 465282329 # number of ReadReq accesses(hits+misses) 637system.cpu.icache.demand_accesses::cpu.inst 465282329 # number of demand (read+write) accesses 638system.cpu.icache.demand_accesses::total 465282329 # number of demand (read+write) accesses 639system.cpu.icache.overall_accesses::cpu.inst 465282329 # number of overall (read+write) accesses 640system.cpu.icache.overall_accesses::total 465282329 # number of overall (read+write) accesses 641system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 642system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 643system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 644system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 645system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 646system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 647system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76193.528694 # average ReadReq miss latency 648system.cpu.icache.ReadReq_avg_miss_latency::total 76193.528694 # average ReadReq miss latency 649system.cpu.icache.demand_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency 650system.cpu.icache.demand_avg_miss_latency::total 76193.528694 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::total 76193.528694 # average overall miss latency 653system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 658system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.icache.writebacks::writebacks 29 # number of writebacks 660system.cpu.icache.writebacks::total 29 # number of writebacks 661system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses 662system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses 663system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses 664system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses 665system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses 666system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses 667system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61583500 # number of ReadReq MSHR miss cycles 668system.cpu.icache.ReadReq_mshr_miss_latency::total 61583500 # number of ReadReq MSHR miss cycles 669system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61583500 # number of demand (read+write) MSHR miss cycles 670system.cpu.icache.demand_mshr_miss_latency::total 61583500 # number of demand (read+write) MSHR miss cycles 671system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61583500 # number of overall MSHR miss cycles 672system.cpu.icache.overall_mshr_miss_latency::total 61583500 # number of overall MSHR miss cycles 673system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 674system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 675system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 676system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 678system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency 680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 682system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 684system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency 685system.cpu.l2cache.tags.replacements 2013919 # number of replacements 686system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use 687system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. 688system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. 689system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks. 690system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. 691system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor 692system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.data 16398.892088 # Average occupied blocks per requestor 694system.cpu.l2cache.tags.occ_percent::writebacks 0.452664 # Average percentage of cache occupancy 695system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000807 # Average percentage of cache occupancy 696system.cpu.l2cache.tags.occ_percent::cpu.data 0.500454 # Average percentage of cache occupancy 697system.cpu.l2cache.tags.occ_percent::total 0.953926 # Average percentage of cache occupancy 698system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id 699system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 700system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 701system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id 702system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id 704system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id 705system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses 706system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses 707system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits 708system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits 709system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits 710system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits 711system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits 712system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits 713system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits 714system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits 715system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits 716system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits 717system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits 718system.cpu.l2cache.demand_hits::cpu.data 7179324 # number of demand (read+write) hits 719system.cpu.l2cache.demand_hits::total 7179360 # number of demand (read+write) hits 720system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits 721system.cpu.l2cache.overall_hits::cpu.data 7179324 # number of overall hits 722system.cpu.l2cache.overall_hits::total 7179360 # number of overall hits 723system.cpu.l2cache.ReadExReq_misses::cpu.data 801159 # number of ReadExReq misses 724system.cpu.l2cache.ReadExReq_misses::total 801159 # number of ReadExReq misses 725system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 783 # number of ReadCleanReq misses 726system.cpu.l2cache.ReadCleanReq_misses::total 783 # number of ReadCleanReq misses 727system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244654 # number of ReadSharedReq misses 728system.cpu.l2cache.ReadSharedReq_misses::total 1244654 # number of ReadSharedReq misses 729system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses 730system.cpu.l2cache.demand_misses::cpu.data 2045813 # number of demand (read+write) misses 731system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses 732system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses 733system.cpu.l2cache.overall_misses::cpu.data 2045813 # number of overall misses 734system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses 735system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70441435500 # number of ReadExReq miss cycles 736system.cpu.l2cache.ReadExReq_miss_latency::total 70441435500 # number of ReadExReq miss cycles 737system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59945000 # number of ReadCleanReq miss cycles 738system.cpu.l2cache.ReadCleanReq_miss_latency::total 59945000 # number of ReadCleanReq miss cycles 739system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108637226500 # number of ReadSharedReq miss cycles 740system.cpu.l2cache.ReadSharedReq_miss_latency::total 108637226500 # number of ReadSharedReq miss cycles 741system.cpu.l2cache.demand_miss_latency::cpu.inst 59945000 # number of demand (read+write) miss cycles 742system.cpu.l2cache.demand_miss_latency::cpu.data 179078662000 # number of demand (read+write) miss cycles 743system.cpu.l2cache.demand_miss_latency::total 179138607000 # number of demand (read+write) miss cycles 744system.cpu.l2cache.overall_miss_latency::cpu.inst 59945000 # number of overall miss cycles 745system.cpu.l2cache.overall_miss_latency::cpu.data 179078662000 # number of overall miss cycles 746system.cpu.l2cache.overall_miss_latency::total 179138607000 # number of overall miss cycles 747system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684567 # number of WritebackDirty accesses(hits+misses) 748system.cpu.l2cache.WritebackDirty_accesses::total 3684567 # number of WritebackDirty accesses(hits+misses) 749system.cpu.l2cache.WritebackClean_accesses::writebacks 29 # number of WritebackClean accesses(hits+misses) 750system.cpu.l2cache.WritebackClean_accesses::total 29 # number of WritebackClean accesses(hits+misses) 751system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890853 # number of ReadExReq accesses(hits+misses) 752system.cpu.l2cache.ReadExReq_accesses::total 1890853 # number of ReadExReq accesses(hits+misses) 753system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 819 # number of ReadCleanReq accesses(hits+misses) 754system.cpu.l2cache.ReadCleanReq_accesses::total 819 # number of ReadCleanReq accesses(hits+misses) 755system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7334284 # number of ReadSharedReq accesses(hits+misses) 756system.cpu.l2cache.ReadSharedReq_accesses::total 7334284 # number of ReadSharedReq accesses(hits+misses) 757system.cpu.l2cache.demand_accesses::cpu.inst 819 # number of demand (read+write) accesses 758system.cpu.l2cache.demand_accesses::cpu.data 9225137 # number of demand (read+write) accesses 759system.cpu.l2cache.demand_accesses::total 9225956 # number of demand (read+write) accesses 760system.cpu.l2cache.overall_accesses::cpu.inst 819 # number of overall (read+write) accesses 761system.cpu.l2cache.overall_accesses::cpu.data 9225137 # number of overall (read+write) accesses 762system.cpu.l2cache.overall_accesses::total 9225956 # number of overall (read+write) accesses 763system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423702 # miss rate for ReadExReq accesses 764system.cpu.l2cache.ReadExReq_miss_rate::total 0.423702 # miss rate for ReadExReq accesses 765system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.956044 # miss rate for ReadCleanReq accesses 766system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.956044 # miss rate for ReadCleanReq accesses 767system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169704 # miss rate for ReadSharedReq accesses 768system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169704 # miss rate for ReadSharedReq accesses 769system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956044 # miss rate for demand accesses 770system.cpu.l2cache.demand_miss_rate::cpu.data 0.221765 # miss rate for demand accesses 771system.cpu.l2cache.demand_miss_rate::total 0.221830 # miss rate for demand accesses 772system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956044 # miss rate for overall accesses 773system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses 774system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses 775system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87924.413880 # average ReadExReq miss latency 776system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87924.413880 # average ReadExReq miss latency 777system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76558.109834 # average ReadCleanReq miss latency 778system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76558.109834 # average ReadCleanReq miss latency 779system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87283.073449 # average ReadSharedReq miss latency 780system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87283.073449 # average ReadSharedReq miss latency 781system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency 782system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency 783system.cpu.l2cache.demand_avg_miss_latency::total 87530.028887 # average overall miss latency 784system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76558.109834 # average overall miss latency 785system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency 786system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887 # average overall miss latency 787system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 789system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 790system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 791system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 792system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 793system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks 794system.cpu.l2cache.writebacks::total 1050123 # number of writebacks 795system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 796system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 797system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 798system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 799system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 800system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 801system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 214 # number of CleanEvict MSHR misses 802system.cpu.l2cache.CleanEvict_mshr_misses::total 214 # number of CleanEvict MSHR misses 803system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801159 # number of ReadExReq MSHR misses 804system.cpu.l2cache.ReadExReq_mshr_misses::total 801159 # number of ReadExReq MSHR misses 805system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 783 # number of ReadCleanReq MSHR misses 806system.cpu.l2cache.ReadCleanReq_mshr_misses::total 783 # number of ReadCleanReq MSHR misses 807system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses 808system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses 809system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses 810system.cpu.l2cache.demand_mshr_misses::cpu.data 2045808 # number of demand (read+write) MSHR misses 811system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses 812system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses 813system.cpu.l2cache.overall_mshr_misses::cpu.data 2045808 # number of overall MSHR misses 814system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses 815system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62429845500 # number of ReadExReq MSHR miss cycles 816system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62429845500 # number of ReadExReq MSHR miss cycles 817system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52115000 # number of ReadCleanReq MSHR miss cycles 818system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52115000 # number of ReadCleanReq MSHR miss cycles 819system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96190393500 # number of ReadSharedReq MSHR miss cycles 820system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96190393500 # number of ReadSharedReq MSHR miss cycles 821system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52115000 # number of demand (read+write) MSHR miss cycles 822system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158620239000 # number of demand (read+write) MSHR miss cycles 823system.cpu.l2cache.demand_mshr_miss_latency::total 158672354000 # number of demand (read+write) MSHR miss cycles 824system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52115000 # number of overall MSHR miss cycles 825system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158620239000 # number of overall MSHR miss cycles 826system.cpu.l2cache.overall_mshr_miss_latency::total 158672354000 # number of overall MSHR miss cycles 827system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 828system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 829system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423702 # mshr miss rate for ReadExReq accesses 830system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423702 # mshr miss rate for ReadExReq accesses 831system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses 832system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses 833system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses 834system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses 835system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses 836system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for demand accesses 837system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses 838system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses 839system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for overall accesses 840system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses 841system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77924.413880 # average ReadExReq mshr miss latency 842system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77924.413880 # average ReadExReq mshr miss latency 843system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66558.109834 # average ReadCleanReq mshr miss latency 844system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66558.109834 # average ReadCleanReq mshr miss latency 845system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77283.148502 # average ReadSharedReq mshr miss latency 846system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77283.148502 # average ReadSharedReq mshr miss latency 847system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency 848system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency 849system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency 850system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency 851system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency 852system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency 853system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter. 854system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. 855system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 856system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. 857system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 858system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 859system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution 860system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution 861system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution 862system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution 867system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1667 # Packet count per connected master and slave (bytes) 868system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes) 869system.cpu.toL2Bus.pkt_count::total 27672982 # Packet count per connected master and slave (bytes) 870system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54272 # Cumulative packet size per connected master and slave (bytes) 871system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826221056 # Cumulative packet size per connected master and slave (bytes) 872system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) 873system.cpu.toL2Bus.snoops 2013919 # Total snoops (count) 874system.cpu.toL2Bus.snoop_fanout::samples 11239875 # Request fanout histogram 875system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram 876system.cpu.toL2Bus.snoop_fanout::stdev 0.016088 # Request fanout histogram 877system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 878system.cpu.toL2Bus.snoop_fanout::0 11236983 99.97% 99.97% # Request fanout histogram 879system.cpu.toL2Bus.snoop_fanout::1 2886 0.03% 100.00% # Request fanout histogram 880system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 881system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 882system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 883system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram 885system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks) 886system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 887system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) 888system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 889system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) 890system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 891system.membus.trans_dist::ReadResp 1245432 # Transaction distribution 892system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution 893system.membus.trans_dist::CleanEvict 962724 # Transaction distribution 894system.membus.trans_dist::ReadExReq 801159 # Transaction distribution 895system.membus.trans_dist::ReadExResp 801159 # Transaction distribution 896system.membus.trans_dist::ReadSharedReq 1245432 # Transaction distribution 897system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106029 # Packet count per connected master and slave (bytes) 898system.membus.pkt_count::total 6106029 # Packet count per connected master and slave (bytes) 899system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) 900system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) 901system.membus.snoops 0 # Total snoops (count) 902system.membus.snoop_fanout::samples 4059438 # Request fanout histogram 903system.membus.snoop_fanout::mean 0 # Request fanout histogram 904system.membus.snoop_fanout::stdev 0 # Request fanout histogram 905system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 906system.membus.snoop_fanout::0 4059438 100.00% 100.00% # Request fanout histogram 907system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 908system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 909system.membus.snoop_fanout::min_value 0 # Request fanout histogram 910system.membus.snoop_fanout::max_value 0 # Request fanout histogram 911system.membus.snoop_fanout::total 4059438 # Request fanout histogram 912system.membus.reqLayer0.occupancy 8663216000 # Layer occupancy (ticks) 913system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 914system.membus.respLayer1.occupancy 11191487250 # Layer occupancy (ticks) 915system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 916 917---------- End Simulation Statistics ---------- 918