stats.txt revision 11606
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311606Sandreas.sandberg@arm.comsim_seconds 1.130744 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 1130744162500 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 1130744162500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 210155 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 226410 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 153850224 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 274312 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 7349.64 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 1544563088 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 1664032481 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 1711606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.data 132094976 # Number of bytes read from this memory 1911606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 132145216 # Number of bytes read from this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory 2111606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 67850112 # Number of bytes written to this memory 2311606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 67850112 # Number of bytes written to this memory 2411606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.data 2063984 # Number of read requests responded to by this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 2064769 # Number of read requests responded to by this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 1060158 # Number of write requests responded to by this memory 2811606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 1060158 # Number of write requests responded to by this memory 2911606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.inst 44431 # Total read bandwidth from this memory (bytes/s) 3011606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 116821276 # Total read bandwidth from this memory (bytes/s) 3111606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 116865707 # Total read bandwidth from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu.inst 44431 # Instruction read bandwidth from this memory (bytes/s) 3311606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 44431 # Instruction read bandwidth from this memory (bytes/s) 3411606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 60004831 # Write bandwidth from this memory (bytes/s) 3511606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 60004831 # Write bandwidth from this memory (bytes/s) 3611606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 60004831 # Total bandwidth to/from this memory (bytes/s) 3711606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.inst 44431 # Total bandwidth to/from this memory (bytes/s) 3811606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 116821276 # Total bandwidth to/from this memory (bytes/s) 3911606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 176870538 # Total bandwidth to/from this memory (bytes/s) 4011606Sandreas.sandberg@arm.comsystem.physmem.readReqs 2064769 # Number of read requests accepted 4111606Sandreas.sandberg@arm.comsystem.physmem.writeReqs 1060158 # Number of write requests accepted 4211606Sandreas.sandberg@arm.comsystem.physmem.readBursts 2064769 # Number of DRAM read bursts, including those serviced by the write queue 4311606Sandreas.sandberg@arm.comsystem.physmem.writeBursts 1060158 # Number of DRAM write bursts, including those merged in the write queue 4411606Sandreas.sandberg@arm.comsystem.physmem.bytesReadDRAM 132060352 # Total number of bytes read from DRAM 4511606Sandreas.sandberg@arm.comsystem.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue 4611606Sandreas.sandberg@arm.comsystem.physmem.bytesWritten 67848640 # Total number of bytes written to DRAM 4711606Sandreas.sandberg@arm.comsystem.physmem.bytesReadSys 132145216 # Total read bytes from the system interface side 4811606Sandreas.sandberg@arm.comsystem.physmem.bytesWrittenSys 67850112 # Total written bytes from the system interface side 4911606Sandreas.sandberg@arm.comsystem.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue 5011507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5111507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5211606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::0 128520 # Per bank write bursts 5311606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::1 125806 # Per bank write bursts 5411606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::2 122672 # Per bank write bursts 5511606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::3 124571 # Per bank write bursts 5611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::4 123572 # Per bank write bursts 5711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::5 123679 # Per bank write bursts 5811606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::6 124365 # Per bank write bursts 5911606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::7 124958 # Per bank write bursts 6011606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::8 132489 # Per bank write bursts 6111606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::9 134780 # Per bank write bursts 6211606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::10 133233 # Per bank write bursts 6311606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::11 134506 # Per bank write bursts 6411606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::12 134518 # Per bank write bursts 6511606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::13 134594 # Per bank write bursts 6611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::14 130540 # Per bank write bursts 6711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::15 130640 # Per bank write bursts 6811606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::0 66781 # Per bank write bursts 6911606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::1 64941 # Per bank write bursts 7011606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::2 63173 # Per bank write bursts 7111606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::3 63584 # Per bank write bursts 7211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::4 63558 # Per bank write bursts 7311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::5 63644 # Per bank write bursts 7411606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::6 65047 # Per bank write bursts 7511606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::7 66055 # Per bank write bursts 7611606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::8 67972 # Per bank write bursts 7711606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::9 68438 # Per bank write bursts 7811606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::10 68161 # Per bank write bursts 7911606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::11 68586 # Per bank write bursts 8011606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::12 68040 # Per bank write bursts 8111606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::13 68530 # Per bank write bursts 8211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::14 67159 # Per bank write bursts 8311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::15 66466 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8511507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8611606Sandreas.sandberg@arm.comsystem.physmem.totGap 1130744067500 # Total gap between requests 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9311606Sandreas.sandberg@arm.comsystem.physmem.readPktSize::6 2064769 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10011606Sandreas.sandberg@arm.comsystem.physmem.writePktSize::6 1060158 # Write request sizes (log2) 10111606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::0 1931837 # What read queue length does an incoming req see 10211606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 131592 # What read queue length does an incoming req see 10311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::15 32506 # What write queue length does an incoming req see 14911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::16 33515 # What write queue length does an incoming req see 15011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::17 57459 # What write queue length does an incoming req see 15111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::18 62386 # What write queue length does an incoming req see 15211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::19 62542 # What write queue length does an incoming req see 15311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::20 62618 # What write queue length does an incoming req see 15411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::21 62533 # What write queue length does an incoming req see 15511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::22 62474 # What write queue length does an incoming req see 15611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::23 62468 # What write queue length does an incoming req see 15711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::24 62484 # What write queue length does an incoming req see 15811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::25 62514 # What write queue length does an incoming req see 15911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::26 62444 # What write queue length does an incoming req see 16011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::27 62521 # What write queue length does an incoming req see 16111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::28 62600 # What write queue length does an incoming req see 16211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::29 62677 # What write queue length does an incoming req see 16311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::30 62255 # What write queue length does an incoming req see 16411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::31 62124 # What write queue length does an incoming req see 16511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::32 61991 # What write queue length does an incoming req see 16611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see 16711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 17011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 17111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 1925169 # Bytes accessed per row activation 19811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 103.839212 # Bytes accessed per row activation 19911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 81.850367 # Bytes accessed per row activation 20011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 126.421931 # Bytes accessed per row activation 20111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::0-127 1496084 77.71% 77.71% # Bytes accessed per row activation 20211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::128-255 309482 16.08% 93.79% # Bytes accessed per row activation 20311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 52255 2.71% 96.50% # Bytes accessed per row activation 20411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 20716 1.08% 97.58% # Bytes accessed per row activation 20511606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 12793 0.66% 98.24% # Bytes accessed per row activation 20611606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 7748 0.40% 98.64% # Bytes accessed per row activation 20711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::768-895 5753 0.30% 98.94% # Bytes accessed per row activation 20811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::896-1023 5054 0.26% 99.21% # Bytes accessed per row activation 20911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::1024-1151 15284 0.79% 100.00% # Bytes accessed per row activation 21011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 1925169 # Bytes accessed per row activation 21111606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::samples 61990 # Reads before turning the bus around for writes 21211606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::mean 33.244314 # Reads before turning the bus around for writes 21311606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::gmean 23.928422 # Reads before turning the bus around for writes 21411606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::stdev 148.698604 # Reads before turning the bus around for writes 21511606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::0-1023 61952 99.94% 99.94% # Reads before turning the bus around for writes 21611606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes 21711606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes 21811606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes 21911606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes 22011507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes 22111606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes 22211507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes 22311606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes 22411606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::total 61990 # Reads before turning the bus around for writes 22511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::samples 61990 # Writes before turning the bus around for reads 22611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::mean 17.101710 # Writes before turning the bus around for reads 22711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::gmean 17.070337 # Writes before turning the bus around for reads 22811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::stdev 1.034747 # Writes before turning the bus around for reads 22911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::16 28322 45.69% 45.69% # Writes before turning the bus around for reads 23011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::17 1015 1.64% 47.33% # Writes before turning the bus around for reads 23111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::18 30732 49.58% 96.90% # Writes before turning the bus around for reads 23211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::19 1873 3.02% 99.92% # Writes before turning the bus around for reads 23311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::20 43 0.07% 99.99% # Writes before turning the bus around for reads 23411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads 23511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::total 61990 # Writes before turning the bus around for reads 23611606Sandreas.sandberg@arm.comsystem.physmem.totQLat 38536102500 # Total ticks spent queuing 23711606Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 77225658750 # Total ticks spent from burst creation until serviced by the DRAM 23811606Sandreas.sandberg@arm.comsystem.physmem.totBusLat 10317215000 # Total ticks spent in databus transfers 23911606Sandreas.sandberg@arm.comsystem.physmem.avgQLat 18675.63 # Average queueing delay per DRAM burst 24011507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 24111606Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 37425.63 # Average memory access latency per DRAM burst 24211606Sandreas.sandberg@arm.comsystem.physmem.avgRdBW 116.79 # Average DRAM read bandwidth in MiByte/s 24311606Sandreas.sandberg@arm.comsystem.physmem.avgWrBW 60.00 # Average achieved write bandwidth in MiByte/s 24411606Sandreas.sandberg@arm.comsystem.physmem.avgRdBWSys 116.87 # Average system read bandwidth in MiByte/s 24511606Sandreas.sandberg@arm.comsystem.physmem.avgWrBWSys 60.00 # Average system write bandwidth in MiByte/s 24611507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 24711606Sandreas.sandberg@arm.comsystem.physmem.busUtil 1.38 # Data bus utilization in percentage 24811570SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads 24911507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 25011507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 25111606Sandreas.sandberg@arm.comsystem.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing 25211606Sandreas.sandberg@arm.comsystem.physmem.readRowHits 775929 # Number of row buffer hits during reads 25311606Sandreas.sandberg@arm.comsystem.physmem.writeRowHits 422476 # Number of row buffer hits during writes 25411606Sandreas.sandberg@arm.comsystem.physmem.readRowHitRate 37.60 # Row buffer hit rate for reads 25511606Sandreas.sandberg@arm.comsystem.physmem.writeRowHitRate 39.85 # Row buffer hit rate for writes 25611606Sandreas.sandberg@arm.comsystem.physmem.avgGap 361846.55 # Average gap between requests 25711606Sandreas.sandberg@arm.comsystem.physmem.pageHitRate 38.37 # Row buffer hit rate, read and write combined 25811606Sandreas.sandberg@arm.comsystem.physmem_0.actEnergy 7091695800 # Energy for activate commands per rank (pJ) 25911606Sandreas.sandberg@arm.comsystem.physmem_0.preEnergy 3869476875 # Energy for precharge commands per rank (pJ) 26011606Sandreas.sandberg@arm.comsystem.physmem_0.readEnergy 7785421800 # Energy for read commands per rank (pJ) 26111606Sandreas.sandberg@arm.comsystem.physmem_0.writeEnergy 3348753840 # Energy for write commands per rank (pJ) 26211606Sandreas.sandberg@arm.comsystem.physmem_0.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) 26311606Sandreas.sandberg@arm.comsystem.physmem_0.actBackEnergy 423921506085 # Energy for active background per rank (pJ) 26411606Sandreas.sandberg@arm.comsystem.physmem_0.preBackEnergy 306584736000 # Energy for precharge background per rank (pJ) 26511606Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 826456199280 # Total energy per rank (pJ) 26611606Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 730.896688 # Core power per rank (mW) 26711606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 507283799000 # Time in different power states 26811606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::REF 37757980000 # Time in different power states 26911507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 27011606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::ACT 585701078500 # Time in different power states 27111507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 27211606Sandreas.sandberg@arm.comsystem.physmem_1.actEnergy 7462581840 # Energy for activate commands per rank (pJ) 27311606Sandreas.sandberg@arm.comsystem.physmem_1.preEnergy 4071845250 # Energy for precharge commands per rank (pJ) 27411606Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 8309316600 # Energy for read commands per rank (pJ) 27511606Sandreas.sandberg@arm.comsystem.physmem_1.writeEnergy 3520920960 # Energy for write commands per rank (pJ) 27611606Sandreas.sandberg@arm.comsystem.physmem_1.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) 27711606Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 432965070225 # Energy for active background per rank (pJ) 27811606Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 298651785000 # Energy for precharge background per rank (pJ) 27911606Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 828836128755 # Total energy per rank (pJ) 28011606Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 733.001436 # Core power per rank (mW) 28111606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 494051909000 # Time in different power states 28211606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::REF 37757980000 # Time in different power states 28311507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 28411606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 598934101500 # Time in different power states 28511507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 28611606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 28711606Sandreas.sandberg@arm.comsystem.cpu.branchPred.lookups 240019432 # Number of BP lookups 28811606Sandreas.sandberg@arm.comsystem.cpu.branchPred.condPredicted 186610009 # Number of conditional branches predicted 28911570SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect 29011606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBLookups 131647101 # Number of BTB lookups 29111606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHits 122324380 # Number of BTB hits 29211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 29311606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHitPct 92.918400 # BTB Hit Percentage 29411606Sandreas.sandberg@arm.comsystem.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. 29511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 29611606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. 29711570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 232 # Number of indirect target hits. 29811606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectMisses 303 # Number of indirect misses. 29911570SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. 30011507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 30111606Sandreas.sandberg@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 30211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 30311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 31011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 31111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 31211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 32611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 32711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 32811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 32911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 33011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 33111606Sandreas.sandberg@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 33211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 33311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 33411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 34011507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 34111507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 34211507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 35611507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 35711507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 35811507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 35911507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 36011507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 36111606Sandreas.sandberg@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 36211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 36311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 37111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 37211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 38611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 38711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 38811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 38911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 39011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 39111606Sandreas.sandberg@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 39211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 39311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40011507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 40111507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 41611507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 41711507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 41811507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 41911507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 42011507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 42111507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 46 # Number of system calls 42211606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 1130744162500 # Cumulative time (in ticks) in various power states 42311606Sandreas.sandberg@arm.comsystem.cpu.numCycles 2261488325 # number of cpu cycles simulated 42411507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 42511507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 42611507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 1544563088 # Number of instructions committed 42711507SCurtis.Dunham@arm.comsystem.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed 42811606Sandreas.sandberg@arm.comsystem.cpu.discardedOps 41363718 # Number of ops (including micro ops) which were discarded before commit 42911507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 43011606Sandreas.sandberg@arm.comsystem.cpu.cpi 1.464161 # CPI: cycles per instruction 43111606Sandreas.sandberg@arm.comsystem.cpu.ipc 0.682985 # IPC: instructions per cycle 43211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 43511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 43611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 43711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 43811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 43911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 44011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 44211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 44311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 44411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 44511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 44911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 45011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 45111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 45211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 45311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 45411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 45511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 45611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 45711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 45811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction 45911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 46011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 46111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 46211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 46311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction 46411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 46511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 46611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 1664032481 # Class of committed instruction 46711606Sandreas.sandberg@arm.comsystem.cpu.tickCycles 1844743027 # Number of cycles that the object actually ticked 46811606Sandreas.sandberg@arm.comsystem.cpu.idleCycles 416745298 # Total number of cycles that the object has spent stopped 46911606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 47011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.replacements 9220102 # number of replacements 47111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 4085.712457 # Cycle average of tags in use 47211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.total_refs 624495296 # Total number of references to valid blocks. 47311606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.sampled_refs 9224198 # Sample count of references to valid blocks. 47411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.avg_refs 67.701853 # Average number of references to valid blocks. 47511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.warmup_cycle 9823555500 # Cycle when the warmup percentage was hit. 47611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4085.712457 # Average occupied blocks per requestor 47711606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.997488 # Average percentage of cache occupancy 47811606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.997488 # Average percentage of cache occupancy 47911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 48011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id 48111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id 48211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id 48311606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 48411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 48511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tag_accesses 1277391740 # Number of tag accesses 48611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.data_accesses 1277391740 # Number of data accesses 48711606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 48811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 454164183 # number of ReadReq hits 48911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::total 454164183 # number of ReadReq hits 49011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 170330990 # number of WriteReq hits 49111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::total 170330990 # number of WriteReq hits 49211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 49311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 49411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 49511507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 49611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 49711507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 49811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::cpu.data 624495173 # number of demand (read+write) hits 49911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::total 624495173 # number of demand (read+write) hits 50011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::cpu.data 624495174 # number of overall hits 50111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::total 624495174 # number of overall hits 50211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 7333416 # number of ReadReq misses 50311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_misses::total 7333416 # number of ReadReq misses 50411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 2255057 # number of WriteReq misses 50511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::total 2255057 # number of WriteReq misses 50611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 50711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 50811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::cpu.data 9588473 # number of demand (read+write) misses 50911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::total 9588473 # number of demand (read+write) misses 51011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::cpu.data 9588475 # number of overall misses 51111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::total 9588475 # number of overall misses 51211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000 # number of ReadReq miss cycles 51311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 192638967000 # number of ReadReq miss cycles 51411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000 # number of WriteReq miss cycles 51511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 111261397000 # number of WriteReq miss cycles 51611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 303900364000 # number of demand (read+write) miss cycles 51711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 303900364000 # number of demand (read+write) miss cycles 51811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 303900364000 # number of overall miss cycles 51911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 303900364000 # number of overall miss cycles 52011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 461497599 # number of ReadReq accesses(hits+misses) 52111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::total 461497599 # number of ReadReq accesses(hits+misses) 52211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 52311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 52411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) 52511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) 52611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 52711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 52811507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 52911507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 53011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 634083646 # number of demand (read+write) accesses 53111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::total 634083646 # number of demand (read+write) accesses 53211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 634083649 # number of overall (read+write) accesses 53311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::total 634083649 # number of overall (read+write) accesses 53411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses 53511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses 53611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses 53711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses 53811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses 53911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses 54011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.015122 # miss rate for demand accesses 54111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses 54211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses 54311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses 54411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926 # average ReadReq miss latency 54511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926 # average ReadReq miss latency 54611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492 # average WriteReq miss latency 54711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492 # average WriteReq miss latency 54811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240 # average overall miss latency 54911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 31694.344240 # average overall miss latency 55011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629 # average overall miss latency 55111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 31694.337629 # average overall miss latency 55211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55311507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55411507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 55511507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 55611507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55711507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55811606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::writebacks 3670051 # number of writebacks 55911606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::total 3670051 # number of writebacks 56011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 56111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits 56211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 364227 # number of WriteReq MSHR hits 56311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 364227 # number of WriteReq MSHR hits 56411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 364276 # number of demand (read+write) MSHR hits 56511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_hits::total 364276 # number of demand (read+write) MSHR hits 56611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 364276 # number of overall MSHR hits 56711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_hits::total 364276 # number of overall MSHR hits 56811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333367 # number of ReadReq MSHR misses 56911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 7333367 # number of ReadReq MSHR misses 57011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses 57111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses 57211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 57311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 57411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 9224197 # number of demand (read+write) MSHR misses 57511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_misses::total 9224197 # number of demand (read+write) MSHR misses 57611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 9224198 # number of overall MSHR misses 57711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_misses::total 9224198 # number of overall MSHR misses 57811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000 # number of ReadReq MSHR miss cycles 57911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000 # number of ReadReq MSHR miss cycles 58011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86626211500 # number of WriteReq MSHR miss cycles 58111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 86626211500 # number of WriteReq MSHR miss cycles 58211606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles 58311606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles 58411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500 # number of demand (read+write) MSHR miss cycles 58511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 271929707500 # number of demand (read+write) MSHR miss cycles 58611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500 # number of overall MSHR miss cycles 58711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 271929782500 # number of overall MSHR miss cycles 58811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses 58911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses 59011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 59111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 59211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses 59311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses 59411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses 59511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses 59611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses 59711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses 59811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540 # average ReadReq mshr miss latency 59911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540 # average ReadReq mshr miss latency 60011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027 # average WriteReq mshr miss latency 60111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027 # average WriteReq mshr miss latency 60211606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency 60311606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency 60411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189 # average overall mshr miss latency 60511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189 # average overall mshr miss latency 60611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124 # average overall mshr miss latency 60711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124 # average overall mshr miss latency 60811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 60911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.replacements 33 # number of replacements 61011606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 660.343836 # Cycle average of tags in use 61111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.total_refs 466264831 # Total number of references to valid blocks. 61211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. 61311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.avg_refs 567232.154501 # Average number of references to valid blocks. 61411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 61511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 660.343836 # Average occupied blocks per requestor 61611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.322434 # Average percentage of cache occupancy 61711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::total 0.322434 # Average percentage of cache occupancy 61811570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id 61911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 62011606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 62111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id 62211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id 62311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tag_accesses 932532128 # Number of tag accesses 62411606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.data_accesses 932532128 # Number of data accesses 62511606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 62611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 466264831 # number of ReadReq hits 62711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::total 466264831 # number of ReadReq hits 62811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::cpu.inst 466264831 # number of demand (read+write) hits 62911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::total 466264831 # number of demand (read+write) hits 63011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::cpu.inst 466264831 # number of overall hits 63111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::total 466264831 # number of overall hits 63211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses 63311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses 63411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses 63511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses 63611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses 63711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::total 822 # number of overall misses 63811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 62977000 # number of ReadReq miss cycles 63911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 62977000 # number of ReadReq miss cycles 64011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 62977000 # number of demand (read+write) miss cycles 64111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 62977000 # number of demand (read+write) miss cycles 64211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 62977000 # number of overall miss cycles 64311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 62977000 # number of overall miss cycles 64411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 466265653 # number of ReadReq accesses(hits+misses) 64511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::total 466265653 # number of ReadReq accesses(hits+misses) 64611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 466265653 # number of demand (read+write) accesses 64711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::total 466265653 # number of demand (read+write) accesses 64811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 466265653 # number of overall (read+write) accesses 64911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::total 466265653 # number of overall (read+write) accesses 65011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 65111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 65211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 65311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 65411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 65511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 65611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76614.355231 # average ReadReq miss latency 65711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 76614.355231 # average ReadReq miss latency 65811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency 65911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 76614.355231 # average overall miss latency 66011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency 66111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 76614.355231 # average overall miss latency 66211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 66311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 66411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 66511507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 66611507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 66711507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 66811606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::writebacks 33 # number of writebacks 66911606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::total 33 # number of writebacks 67011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 822 # number of ReadReq MSHR misses 67111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 822 # number of ReadReq MSHR misses 67211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 822 # number of demand (read+write) MSHR misses 67311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses 67411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses 67511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses 67611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62155000 # number of ReadReq MSHR miss cycles 67711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 62155000 # number of ReadReq MSHR miss cycles 67811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 62155000 # number of demand (read+write) MSHR miss cycles 67911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 62155000 # number of demand (read+write) MSHR miss cycles 68011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 62155000 # number of overall MSHR miss cycles 68111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 62155000 # number of overall MSHR miss cycles 68211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 68311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 68411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 68511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 68611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 68711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 68811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75614.355231 # average ReadReq mshr miss latency 68911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75614.355231 # average ReadReq mshr miss latency 69011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75614.355231 # average overall mshr miss latency 69111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 75614.355231 # average overall mshr miss latency 69211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75614.355231 # average overall mshr miss latency 69311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 75614.355231 # average overall mshr miss latency 69411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 69511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.replacements 2032337 # number of replacements 69611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 31884.361365 # Cycle average of tags in use 69711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.total_refs 16378235 # Total number of references to valid blocks. 69811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 2065105 # Sample count of references to valid blocks. 69911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 7.930945 # Average number of references to valid blocks. 70011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.warmup_cycle 54418076000 # Cycle when the warmup percentage was hit. 70111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 10.408988 # Average occupied blocks per requestor 70211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 25.813492 # Average occupied blocks per requestor 70311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 31848.138885 # Average occupied blocks per requestor 70411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.000318 # Average percentage of cache occupancy 70511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.000788 # Average percentage of cache occupancy 70611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.971928 # Average percentage of cache occupancy 70711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.973033 # Average percentage of cache occupancy 70811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 70911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 71011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 912 # Occupied blocks per task id 71111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2876 # Occupied blocks per task id 71211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 7195 # Occupied blocks per task id 71311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 21737 # Occupied blocks per task id 71411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 71511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tag_accesses 149613593 # Number of tag accesses 71611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.data_accesses 149613593 # Number of data accesses 71711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 71811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 3670051 # number of WritebackDirty hits 71911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 3670051 # number of WritebackDirty hits 72011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 72111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 72211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1078506 # number of ReadExReq hits 72311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1078506 # number of ReadExReq hits 72411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits 72511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits 72611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081702 # number of ReadSharedReq hits 72711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 6081702 # number of ReadSharedReq hits 72811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits 72911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 7160208 # number of demand (read+write) hits 73011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::total 7160245 # number of demand (read+write) hits 73111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits 73211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 7160208 # number of overall hits 73311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::total 7160245 # number of overall hits 73411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 812324 # number of ReadExReq misses 73511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 812324 # number of ReadExReq misses 73611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses 73711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses 73811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251666 # number of ReadSharedReq misses 73911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 1251666 # number of ReadSharedReq misses 74011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses 74111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 2063990 # number of demand (read+write) misses 74211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::total 2064775 # number of demand (read+write) misses 74311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses 74411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 2063990 # number of overall misses 74511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::total 2064775 # number of overall misses 74611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72440693500 # number of ReadExReq miss cycles 74711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 72440693500 # number of ReadExReq miss cycles 74811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 60501000 # number of ReadCleanReq miss cycles 74911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 60501000 # number of ReadCleanReq miss cycles 75011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 110442540000 # number of ReadSharedReq miss cycles 75111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 110442540000 # number of ReadSharedReq miss cycles 75211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 60501000 # number of demand (read+write) miss cycles 75311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 182883233500 # number of demand (read+write) miss cycles 75411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::total 182943734500 # number of demand (read+write) miss cycles 75511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 60501000 # number of overall miss cycles 75611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 182883233500 # number of overall miss cycles 75711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::total 182943734500 # number of overall miss cycles 75811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 3670051 # number of WritebackDirty accesses(hits+misses) 75911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 3670051 # number of WritebackDirty accesses(hits+misses) 76011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 76111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 76211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1890830 # number of ReadExReq accesses(hits+misses) 76311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 1890830 # number of ReadExReq accesses(hits+misses) 76411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses) 76511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses) 76611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333368 # number of ReadSharedReq accesses(hits+misses) 76711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 7333368 # number of ReadSharedReq accesses(hits+misses) 76811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 822 # number of demand (read+write) accesses 76911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 9224198 # number of demand (read+write) accesses 77011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::total 9225020 # number of demand (read+write) accesses 77111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 822 # number of overall (read+write) accesses 77211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 9224198 # number of overall (read+write) accesses 77311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::total 9225020 # number of overall (read+write) accesses 77411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429612 # miss rate for ReadExReq accesses 77511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.429612 # miss rate for ReadExReq accesses 77611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954988 # miss rate for ReadCleanReq accesses 77711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954988 # miss rate for ReadCleanReq accesses 77811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170681 # miss rate for ReadSharedReq accesses 77911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170681 # miss rate for ReadSharedReq accesses 78011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses 78111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.223758 # miss rate for demand accesses 78211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.223823 # miss rate for demand accesses 78311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses 78411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses 78511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses 78611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89177.093746 # average ReadExReq miss latency 78711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 89177.093746 # average ReadExReq miss latency 78811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77071.337580 # average ReadCleanReq miss latency 78911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77071.337580 # average ReadCleanReq miss latency 79011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88236.430485 # average ReadSharedReq miss latency 79111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88236.430485 # average ReadSharedReq miss latency 79211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency 79311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency 79411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 88602.261505 # average overall miss latency 79511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency 79611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency 79711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 88602.261505 # average overall miss latency 79811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 79911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 80011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 80111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 80211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 80411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::writebacks 1060158 # number of writebacks 80511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::total 1060158 # number of writebacks 80611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 80711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 80811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 80911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 81011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 81111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 81211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses 81311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses 81411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812324 # number of ReadExReq MSHR misses 81511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 812324 # number of ReadExReq MSHR misses 81611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses 81711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses 81811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251660 # number of ReadSharedReq MSHR misses 81911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251660 # number of ReadSharedReq MSHR misses 82011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses 82111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 2063984 # number of demand (read+write) MSHR misses 82211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 2064769 # number of demand (read+write) MSHR misses 82311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses 82411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 2063984 # number of overall MSHR misses 82511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 2064769 # number of overall MSHR misses 82611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64317453500 # number of ReadExReq MSHR miss cycles 82711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64317453500 # number of ReadExReq MSHR miss cycles 82811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52651000 # number of ReadCleanReq MSHR miss cycles 82911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52651000 # number of ReadCleanReq MSHR miss cycles 83011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 97925523500 # number of ReadSharedReq MSHR miss cycles 83111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 97925523500 # number of ReadSharedReq MSHR miss cycles 83211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52651000 # number of demand (read+write) MSHR miss cycles 83311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162242977000 # number of demand (read+write) MSHR miss cycles 83411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 162295628000 # number of demand (read+write) MSHR miss cycles 83511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52651000 # number of overall MSHR miss cycles 83611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162242977000 # number of overall MSHR miss cycles 83711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 162295628000 # number of overall MSHR miss cycles 83811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 83911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 84011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429612 # mshr miss rate for ReadExReq accesses 84111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429612 # mshr miss rate for ReadExReq accesses 84211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses 84311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses 84411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses 84511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses 84611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses 84711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for demand accesses 84811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.223823 # mshr miss rate for demand accesses 84911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses 85011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for overall accesses 85111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.223823 # mshr miss rate for overall accesses 85211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746 # average ReadExReq mshr miss latency 85311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746 # average ReadExReq mshr miss latency 85411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580 # average ReadCleanReq mshr miss latency 85511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580 # average ReadCleanReq mshr miss latency 85611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701 # average ReadSharedReq mshr miss latency 85711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701 # average ReadSharedReq mshr miss latency 85811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency 85911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency 86011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency 86111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency 86211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency 86311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency 86411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 18445155 # Total number of requests made to the snoop filter. 86511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 9220147 # Number of requests hitting in the snoop filter with a single holder of the requested data. 86611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 86711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1445 # Total number of snoops made to the snoop filter. 86811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 86911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 87011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 87111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 7334190 # Transaction distribution 87211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 4730209 # Transaction distribution 87311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution 87411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution 87511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution 87611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution 87711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution 87811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 7333368 # Transaction distribution 87911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) 88011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668498 # Packet count per connected master and slave (bytes) 88111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count::total 27670175 # Packet count per connected master and slave (bytes) 88211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) 88311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825231936 # Cumulative packet size per connected master and slave (bytes) 88411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size::total 825286656 # Cumulative packet size per connected master and slave (bytes) 88511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoops 2032337 # Total snoops (count) 88611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoopTraffic 67850112 # Total snoop traffic (bytes) 88711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 11257357 # Request fanout histogram 88811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000272 # Request fanout histogram 88911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.016509 # Request fanout histogram 89011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 89111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 11254306 99.97% 99.97% # Request fanout histogram 89211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 3045 0.03% 100.00% # Request fanout histogram 89311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 89411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 89511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 89611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 89711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 11257357 # Request fanout histogram 89811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 12892661500 # Layer occupancy (ticks) 89911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 90011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) 90111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 90211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 13836299994 # Layer occupancy (ticks) 90311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 90411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 4095876 # Total number of requests made to the snoop filter. 90511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 2031264 # Number of requests hitting in the snoop filter with a single holder of the requested data. 90611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 90711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 90811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 90911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 91011606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 91111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 1252445 # Transaction distribution 91211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 1060158 # Transaction distribution 91311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 970949 # Transaction distribution 91411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 812324 # Transaction distribution 91511606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 812324 # Transaction distribution 91611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 1252445 # Transaction distribution 91711606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160645 # Packet count per connected master and slave (bytes) 91811606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 6160645 # Packet count per connected master and slave (bytes) 91911606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995328 # Cumulative packet size per connected master and slave (bytes) 92011606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 199995328 # Cumulative packet size per connected master and slave (bytes) 92111507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 92211570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 92311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 2064769 # Request fanout histogram 92411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 92511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 92611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 92711606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 2064769 100.00% 100.00% # Request fanout histogram 92811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 92911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 93011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 93111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 93211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 2064769 # Request fanout histogram 93311606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 8803577000 # Layer occupancy (ticks) 93411507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 93511606Sandreas.sandberg@arm.comsystem.membus.respLayer1.occupancy 11289358000 # Layer occupancy (ticks) 93611507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 1.0 # Layer utilization (%) 93711507SCurtis.Dunham@arm.com 93811507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 939