111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 1.150356 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 1150356296500 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 1150356296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 374766 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 403753 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 279117141 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 273688 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 4121.41 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 1544563088 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 1664032481 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 1711606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory 1811860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 132097728 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 132147968 # Number of bytes read from this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory 2111606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 67851072 # Number of bytes written to this memory 2311860Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 67851072 # Number of bytes written to this memory 2411606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory 2511860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 2064027 # Number of read requests responded to by this memory 2611860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 2064812 # Number of read requests responded to by this memory 2711860Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1060173 # Number of write requests responded to by this memory 2811860Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1060173 # Number of write requests responded to by this memory 2911860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 43673 # Total read bandwidth from this memory (bytes/s) 3011860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 114832012 # Total read bandwidth from this memory (bytes/s) 3111860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 114875685 # Total read bandwidth from this memory (bytes/s) 3211860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 43673 # Instruction read bandwidth from this memory (bytes/s) 3311860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 43673 # Instruction read bandwidth from this memory (bytes/s) 3411860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 58982658 # Write bandwidth from this memory (bytes/s) 3511860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 58982658 # Write bandwidth from this memory (bytes/s) 3611860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 58982658 # Total bandwidth to/from this memory (bytes/s) 3711860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 43673 # Total bandwidth to/from this memory (bytes/s) 3811860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 114832012 # Total bandwidth to/from this memory (bytes/s) 3911860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 173858343 # Total bandwidth to/from this memory (bytes/s) 4011860Sandreas.hansson@arm.comsystem.physmem.readReqs 2064812 # Number of read requests accepted 4111860Sandreas.hansson@arm.comsystem.physmem.writeReqs 1060173 # Number of write requests accepted 4211860Sandreas.hansson@arm.comsystem.physmem.readBursts 2064812 # Number of DRAM read bursts, including those serviced by the write queue 4311860Sandreas.hansson@arm.comsystem.physmem.writeBursts 1060173 # Number of DRAM write bursts, including those merged in the write queue 4411860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 132064448 # Total number of bytes read from DRAM 4511860Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 83520 # Total number of bytes read from write queue 4611860Sandreas.hansson@arm.comsystem.physmem.bytesWritten 67849344 # Total number of bytes written to DRAM 4711860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 132147968 # Total read bytes from the system interface side 4811860Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 67851072 # Total written bytes from the system interface side 4911860Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 1305 # Number of DRAM read bursts serviced by the write queue 5011507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5111507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 128530 # Per bank write bursts 5311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 125798 # Per bank write bursts 5411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 122667 # Per bank write bursts 5511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 124564 # Per bank write bursts 5611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 123583 # Per bank write bursts 5711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 123689 # Per bank write bursts 5811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 124368 # Per bank write bursts 5911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 124965 # Per bank write bursts 6011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 132503 # Per bank write bursts 6111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 134776 # Per bank write bursts 6211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 133237 # Per bank write bursts 6311680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 134508 # Per bank write bursts 6411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 134521 # Per bank write bursts 6511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 134606 # Per bank write bursts 6611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 130538 # Per bank write bursts 6711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 130654 # Per bank write bursts 6811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 66782 # Per bank write bursts 6911860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 64941 # Per bank write bursts 7011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 63176 # Per bank write bursts 7111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 63581 # Per bank write bursts 7211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 63564 # Per bank write bursts 7311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 63647 # Per bank write bursts 7411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 65050 # Per bank write bursts 7511860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 66062 # Per bank write bursts 7611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 67977 # Per bank write bursts 7711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 68434 # Per bank write bursts 7811860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 68153 # Per bank write bursts 7911860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 68587 # Per bank write bursts 8011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 68034 # Per bank write bursts 8111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 68534 # Per bank write bursts 8211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 67158 # Per bank write bursts 8311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::15 66466 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8511507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8611860Sandreas.hansson@arm.comsystem.physmem.totGap 1150356195500 # Total gap between requests 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9311860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 2064812 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10011860Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1060173 # Write request sizes (log2) 10111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 1919552 # What read queue length does an incoming req see 10211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 143941 # What read queue length does an incoming req see 10311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 30915 # What write queue length does an incoming req see 14911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 32043 # What write queue length does an incoming req see 15011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 57354 # What write queue length does an incoming req see 15111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 62496 # What write queue length does an incoming req see 15211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 62733 # What write queue length does an incoming req see 15311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 62829 # What write queue length does an incoming req see 15411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 62687 # What write queue length does an incoming req see 15511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 62667 # What write queue length does an incoming req see 15611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see 15711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 62549 # What write queue length does an incoming req see 15811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 62604 # What write queue length does an incoming req see 15911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 62637 # What write queue length does an incoming req see 16011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 62661 # What write queue length does an incoming req see 16111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 62650 # What write queue length does an incoming req see 16211860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 62796 # What write queue length does an incoming req see 16311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 63099 # What write queue length does an incoming req see 16411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 62454 # What write queue length does an incoming req see 16511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 62359 # What write queue length does an incoming req see 16611860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 30 # What write queue length does an incoming req see 16711860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see 16811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 17011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 17111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1927714 # Bytes accessed per row activation 19811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 103.704114 # Bytes accessed per row activation 19911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 81.833686 # Bytes accessed per row activation 20011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 125.867792 # Bytes accessed per row activation 20111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 1497696 77.69% 77.69% # Bytes accessed per row activation 20211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 310699 16.12% 93.81% # Bytes accessed per row activation 20311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 52184 2.71% 96.52% # Bytes accessed per row activation 20411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 20631 1.07% 97.59% # Bytes accessed per row activation 20511754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation 20611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 7807 0.40% 98.67% # Bytes accessed per row activation 20711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 5185 0.27% 98.94% # Bytes accessed per row activation 20811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 5186 0.27% 99.21% # Bytes accessed per row activation 20911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 15252 0.79% 100.00% # Bytes accessed per row activation 21011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1927714 # Bytes accessed per row activation 21111860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 62200 # Reads before turning the bus around for writes 21211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 33.128826 # Reads before turning the bus around for writes 21311860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::gmean 23.842942 # Reads before turning the bus around for writes 21411860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 148.982645 # Reads before turning the bus around for writes 21511860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 62161 99.94% 99.94% # Reads before turning the bus around for writes 21611680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes 21711606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes 21811860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes 21911860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes 22011680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes 22111680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes 22211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 22311507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes 22411680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes 22511860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 62200 # Reads before turning the bus around for writes 22611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 62200 # Writes before turning the bus around for reads 22711860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.044148 # Writes before turning the bus around for reads 22811860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.013066 # Writes before turning the bus around for reads 22911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 1.029999 # Writes before turning the bus around for reads 23011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 29988 48.21% 48.21% # Writes before turning the bus around for reads 23111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::17 1141 1.83% 50.05% # Writes before turning the bus around for reads 23211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 29436 47.32% 97.37% # Writes before turning the bus around for reads 23311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::19 1609 2.59% 99.96% # Writes before turning the bus around for reads 23411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20 24 0.04% 100.00% # Writes before turning the bus around for reads 23511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::21 2 0.00% 100.00% # Writes before turning the bus around for reads 23611860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 62200 # Writes before turning the bus around for reads 23711860Sandreas.hansson@arm.comsystem.physmem.totQLat 60011294750 # Total ticks spent queuing 23811860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 98702051000 # Total ticks spent from burst creation until serviced by the DRAM 23911860Sandreas.hansson@arm.comsystem.physmem.totBusLat 10317535000 # Total ticks spent in databus transfers 24011860Sandreas.hansson@arm.comsystem.physmem.avgQLat 29082.19 # Average queueing delay per DRAM burst 24111507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 24211860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 47832.19 # Average memory access latency per DRAM burst 24311860Sandreas.hansson@arm.comsystem.physmem.avgRdBW 114.80 # Average DRAM read bandwidth in MiByte/s 24411860Sandreas.hansson@arm.comsystem.physmem.avgWrBW 58.98 # Average achieved write bandwidth in MiByte/s 24511860Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 114.88 # Average system read bandwidth in MiByte/s 24611860Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 58.98 # Average system write bandwidth in MiByte/s 24711507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 24811680SCurtis.Dunham@arm.comsystem.physmem.busUtil 1.36 # Data bus utilization in percentage 24911680SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads 25011680SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes 25111507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 25211860Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.14 # Average write queue length when enqueuing 25311860Sandreas.hansson@arm.comsystem.physmem.readRowHits 775182 # Number of row buffer hits during reads 25411860Sandreas.hansson@arm.comsystem.physmem.writeRowHits 420747 # Number of row buffer hits during writes 25511860Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 37.57 # Row buffer hit rate for reads 25611860Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 39.69 # Row buffer hit rate for writes 25711860Sandreas.hansson@arm.comsystem.physmem.avgGap 368115.75 # Average gap between requests 25811680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined 25911860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 6705024060 # Energy for activate commands per rank (pJ) 26011860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 3563778240 # Energy for precharge commands per rank (pJ) 26111860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 7126890960 # Energy for read commands per rank (pJ) 26211860Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 2697711660 # Energy for write commands per rank (pJ) 26311860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 71598184320.000015 # Energy for refresh commands per rank (pJ) 26411860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 47589199680 # Energy for active background per rank (pJ) 26511860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 2602904160 # Energy for precharge background per rank (pJ) 26611860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 242927855970 # Energy for active power-down per rank (pJ) 26711860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 71960703840 # Energy for precharge power-down per rank (pJ) 26811860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 82354339920 # Energy for self refresh per rank (pJ) 26911860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 539151608970 # Total energy per rank (pJ) 27011860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 468.682274 # Core power per rank (mW) 27111860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 1039160467250 # Total Idle time Per DRAM Rank 27211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 3513710000 # Time in different power states 27311860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 30352766000 # Time in different power states 27411860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 319025802500 # Time in different power states 27511860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 187397997250 # Time in different power states 27611860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 77329050000 # Time in different power states 27711860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 532736970750 # Time in different power states 27811860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 7058925300 # Energy for activate commands per rank (pJ) 27911860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 3751896390 # Energy for precharge commands per rank (pJ) 28011860Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 7606549020 # Energy for read commands per rank (pJ) 28111680SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) 28211860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 71153184960.000015 # Energy for refresh commands per rank (pJ) 28311860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 47703954360 # Energy for active background per rank (pJ) 28411860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 2452947360 # Energy for precharge background per rank (pJ) 28511860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 248582355720 # Energy for active power-down per rank (pJ) 28611860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 68636874240 # Energy for precharge power-down per rank (pJ) 28711860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 80784488595 # Energy for self refresh per rank (pJ) 28811860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 540590019675 # Total energy per rank (pJ) 28911860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 469.932679 # Core power per rank (mW) 29011860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 1039304472000 # Total Idle time Per DRAM Rank 29111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 3115835000 # Time in different power states 29211860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 30156708000 # Time in different power states 29311860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 315425606000 # Time in different power states 29411860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 178743425250 # Time in different power states 29511860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 77779220750 # Time in different power states 29611860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 545135501500 # Time in different power states 29711860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 29811860Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 240030332 # Number of BP lookups 29911860Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 186613747 # Number of conditional branches predicted 30011860Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 14536765 # Number of conditional branches incorrect 30111860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 132238924 # Number of BTB lookups 30211860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 122337864 # Number of BTB hits 30311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 30411860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 92.512749 # BTB Hit Percentage 30511860Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 15662658 # Number of times the RAS was used to get a target. 30611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 30711860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 538 # Number of indirect predictor lookups. 30811570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 232 # Number of indirect target hits. 30911860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 306 # Number of indirect misses. 31011570SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. 31111507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 31211860Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 32611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 32711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 32811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 33211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 33311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 33411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 33511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 33711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 33811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 33911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 34011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 34111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 34211860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 35611507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 35711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 35811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35911507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 36011507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 36111507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 36211507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 36311507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 36411507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 36511507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36611507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 36711507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 36811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 36911507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 37011507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 37111507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 37211860Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 38611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 38711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 38811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 39211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 39311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 39411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 39511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 39711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 39811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 39911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 40011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 40111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 40211860Sandreas.hansson@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 41611507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 41711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 41811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41911507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 42011507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42111507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 42211507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 42311507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 42411507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 42511507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42611507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 42711507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 42811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 42911507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 43011507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 43111507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 43211955Sgabeblack@google.comsystem.cpu.workload.numSyscalls 46 # Number of system calls 43311860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 1150356296500 # Cumulative time (in ticks) in various power states 43411860Sandreas.hansson@arm.comsystem.cpu.numCycles 2300712593 # number of cpu cycles simulated 43511507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43611507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 43711507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 1544563088 # Number of instructions committed 43811507SCurtis.Dunham@arm.comsystem.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed 43911860Sandreas.hansson@arm.comsystem.cpu.discardedOps 41389188 # Number of ops (including micro ops) which were discarded before commit 44011507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 44111860Sandreas.hansson@arm.comsystem.cpu.cpi 1.489556 # CPI: cycles per instruction 44211860Sandreas.hansson@arm.comsystem.cpu.ipc 0.671341 # IPC: instructions per cycle 44311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 44411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction 44511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 44911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 45011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 45111687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction 45211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 45311687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction 45411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 45511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 45611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 45711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 45811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 45911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 46011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 46111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 46211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 46311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 46411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 46511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 46611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 46711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 46811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 46911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 47011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 47111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction 47211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 47311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 47411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 47511687Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction 47611687Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemWrite 174847022 10.51% 100.00% # Class of committed instruction 47711687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction 47811687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction 47911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 48011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 48111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 1664032481 # Class of committed instruction 48211860Sandreas.hansson@arm.comsystem.cpu.tickCycles 1845105384 # Number of cycles that the object actually ticked 48311860Sandreas.hansson@arm.comsystem.cpu.idleCycles 455607209 # Total number of cycles that the object has spent stopped 48411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 48511860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 9220185 # number of replacements 48611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 4085.806447 # Cycle average of tags in use 48711860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 624504262 # Total number of references to valid blocks. 48811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 9224281 # Sample count of references to valid blocks. 48911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 67.702216 # Average number of references to valid blocks. 49011680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. 49111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4085.806447 # Average occupied blocks per requestor 49211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy 49311680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy 49411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 49511680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id 49611680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 # Occupied blocks per task id 49711680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id 49811680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id 49911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 50011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 1277413521 # Number of tag accesses 50111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 1277413521 # Number of data accesses 50211860Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 50311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 454174952 # number of ReadReq hits 50411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 454174952 # number of ReadReq hits 50511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 170329187 # number of WriteReq hits 50611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 170329187 # number of WriteReq hits 50711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 50811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 50911507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 51011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 51111507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 51211507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 51311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 624504139 # number of demand (read+write) hits 51411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 624504139 # number of demand (read+write) hits 51511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 624504140 # number of overall hits 51611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 624504140 # number of overall hits 51711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 7333496 # number of ReadReq misses 51811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 7333496 # number of ReadReq misses 51911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 2256860 # number of WriteReq misses 52011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 2256860 # number of WriteReq misses 52111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 52211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 52311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 9590356 # number of demand (read+write) misses 52411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 9590356 # number of demand (read+write) misses 52511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 9590358 # number of overall misses 52611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 9590358 # number of overall misses 52711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 208281810000 # number of ReadReq miss cycles 52811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 208281810000 # number of ReadReq miss cycles 52911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 119887020500 # number of WriteReq miss cycles 53011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 119887020500 # number of WriteReq miss cycles 53111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 328168830500 # number of demand (read+write) miss cycles 53211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 328168830500 # number of demand (read+write) miss cycles 53311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 328168830500 # number of overall miss cycles 53411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 328168830500 # number of overall miss cycles 53511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 461508448 # number of ReadReq accesses(hits+misses) 53611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 461508448 # number of ReadReq accesses(hits+misses) 53711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 53811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 53911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) 54011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) 54111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 54211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 54311507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 54411507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 54511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 634094495 # number of demand (read+write) accesses 54611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 634094495 # number of demand (read+write) accesses 54711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 634094498 # number of overall (read+write) accesses 54811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 634094498 # number of overall (read+write) accesses 54911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses 55011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses 55111680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses 55211680SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses 55311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses 55411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses 55511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.015124 # miss rate for demand accesses 55611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.015124 # miss rate for demand accesses 55711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.015124 # miss rate for overall accesses 55811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.015124 # miss rate for overall accesses 55911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28401.435005 # average ReadReq miss latency 56011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 28401.435005 # average ReadReq miss latency 56111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53121.159709 # average WriteReq miss latency 56211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 53121.159709 # average WriteReq miss latency 56311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 34218.628641 # average overall miss latency 56411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 34218.628641 # average overall miss latency 56511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 34218.621505 # average overall miss latency 56611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 34218.621505 # average overall miss latency 56711507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 56811507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 56911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 57011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 57111507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 57211507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 57311860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 3670078 # number of writebacks 57411860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 3670078 # number of writebacks 57511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 57611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits 57711860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 366027 # number of WriteReq MSHR hits 57811860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 366027 # number of WriteReq MSHR hits 57911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 366076 # number of demand (read+write) MSHR hits 58011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 366076 # number of demand (read+write) MSHR hits 58111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 366076 # number of overall MSHR hits 58211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 366076 # number of overall MSHR hits 58311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333447 # number of ReadReq MSHR misses 58411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 7333447 # number of ReadReq MSHR misses 58511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890833 # number of WriteReq MSHR misses 58611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 1890833 # number of WriteReq MSHR misses 58711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 58811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 58911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 9224280 # number of demand (read+write) MSHR misses 59011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 9224280 # number of demand (read+write) MSHR misses 59111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 9224281 # number of overall MSHR misses 59211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 9224281 # number of overall MSHR misses 59311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200943921500 # number of ReadReq MSHR miss cycles 59411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 200943921500 # number of ReadReq MSHR miss cycles 59511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92449770000 # number of WriteReq MSHR miss cycles 59611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 92449770000 # number of WriteReq MSHR miss cycles 59711680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles 59811680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles 59911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 293393691500 # number of demand (read+write) MSHR miss cycles 60011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 293393691500 # number of demand (read+write) MSHR miss cycles 60111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 293393772500 # number of overall MSHR miss cycles 60211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 293393772500 # number of overall MSHR miss cycles 60311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses 60411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses 60511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 60611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 60711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses 60811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses 60911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses 61011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses 61111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses 61211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses 61311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27401.019125 # average ReadReq mshr miss latency 61411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27401.019125 # average ReadReq mshr miss latency 61511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48893.672789 # average WriteReq mshr miss latency 61611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48893.672789 # average WriteReq mshr miss latency 61711680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency 61811680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency 61911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31806.676673 # average overall mshr miss latency 62011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 31806.676673 # average overall mshr miss latency 62111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31806.682006 # average overall mshr miss latency 62211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 31806.682006 # average overall mshr miss latency 62311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 62411606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.replacements 33 # number of replacements 62511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 660.481453 # Cycle average of tags in use 62611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 466324528 # Total number of references to valid blocks. 62711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. 62811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 567304.778589 # Average number of references to valid blocks. 62911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 63011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 660.481453 # Average occupied blocks per requestor 63111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.322501 # Average percentage of cache occupancy 63211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.322501 # Average percentage of cache occupancy 63311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id 63411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 63511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 63611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id 63711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id 63811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 932651522 # Number of tag accesses 63911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 932651522 # Number of data accesses 64011860Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 64111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 466324528 # number of ReadReq hits 64211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 466324528 # number of ReadReq hits 64311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 466324528 # number of demand (read+write) hits 64411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 466324528 # number of demand (read+write) hits 64511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 466324528 # number of overall hits 64611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 466324528 # number of overall hits 64711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses 64811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses 64911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses 65011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses 65111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses 65211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::total 822 # number of overall misses 65311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 75338000 # number of ReadReq miss cycles 65411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 75338000 # number of ReadReq miss cycles 65511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 75338000 # number of demand (read+write) miss cycles 65611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 75338000 # number of demand (read+write) miss cycles 65711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 75338000 # number of overall miss cycles 65811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 75338000 # number of overall miss cycles 65911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 466325350 # number of ReadReq accesses(hits+misses) 66011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 466325350 # number of ReadReq accesses(hits+misses) 66111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 466325350 # number of demand (read+write) accesses 66211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 466325350 # number of demand (read+write) accesses 66311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 466325350 # number of overall (read+write) accesses 66411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 466325350 # number of overall (read+write) accesses 66511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 66611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 66711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 66811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 66911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 67011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 67111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91652.068127 # average ReadReq miss latency 67211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 91652.068127 # average ReadReq miss latency 67311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency 67411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 91652.068127 # average overall miss latency 67511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency 67611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 91652.068127 # average overall miss latency 67711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 67811507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 67911507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 68011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 68111507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 68211507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 68311606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::writebacks 33 # number of writebacks 68411606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::total 33 # number of writebacks 68511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 822 # number of ReadReq MSHR misses 68611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 822 # number of ReadReq MSHR misses 68711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 822 # number of demand (read+write) MSHR misses 68811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses 68911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses 69011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses 69111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74516000 # number of ReadReq MSHR miss cycles 69211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 74516000 # number of ReadReq MSHR miss cycles 69311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 74516000 # number of demand (read+write) MSHR miss cycles 69411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 74516000 # number of demand (read+write) MSHR miss cycles 69511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 74516000 # number of overall MSHR miss cycles 69611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 74516000 # number of overall MSHR miss cycles 69711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 69811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 69911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 70011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 70111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 70211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 70311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90652.068127 # average ReadReq mshr miss latency 70411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90652.068127 # average ReadReq mshr miss latency 70511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency 70611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency 70711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency 70811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency 70911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 71011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 2032379 # number of replacements 71111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 31895.934748 # Cycle average of tags in use 71211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 16378358 # Total number of references to valid blocks. 71311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 2065147 # Sample count of references to valid blocks. 71411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 7.930844 # Average number of references to valid blocks. 71511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. 71611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 10.372068 # Average occupied blocks per requestor 71711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 25.532774 # Average occupied blocks per requestor 71811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 31860.029906 # Average occupied blocks per requestor 71911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy 72011680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy 72111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.972291 # Average percentage of cache occupancy 72211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.973387 # Average percentage of cache occupancy 72311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 72411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 72511680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 831 # Occupied blocks per task id 72611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 2946 # Occupied blocks per task id 72711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 7191 # Occupied blocks per task id 72811680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 # Occupied blocks per task id 72911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 73011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 149614963 # Number of tag accesses 73111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 149614963 # Number of data accesses 73211860Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 73311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 3670078 # number of WritebackDirty hits 73411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 3670078 # number of WritebackDirty hits 73511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 73611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 73711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 1078495 # number of ReadExReq hits 73811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 1078495 # number of ReadExReq hits 73911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits 74011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits 74111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081752 # number of ReadSharedReq hits 74211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 6081752 # number of ReadSharedReq hits 74311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits 74411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 7160247 # number of demand (read+write) hits 74511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 7160284 # number of demand (read+write) hits 74611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits 74711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 7160247 # number of overall hits 74811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 7160284 # number of overall hits 74911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 812338 # number of ReadExReq misses 75011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 812338 # number of ReadExReq misses 75111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses 75211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses 75311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251696 # number of ReadSharedReq misses 75411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 1251696 # number of ReadSharedReq misses 75511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses 75611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 2064034 # number of demand (read+write) misses 75711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 2064819 # number of demand (read+write) misses 75811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses 75911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 2064034 # number of overall misses 76011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 2064819 # number of overall misses 76111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78265681500 # number of ReadExReq miss cycles 76211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 78265681500 # number of ReadExReq miss cycles 76311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72863000 # number of ReadCleanReq miss cycles 76411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 72863000 # number of ReadCleanReq miss cycles 76511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 126082122000 # number of ReadSharedReq miss cycles 76611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 126082122000 # number of ReadSharedReq miss cycles 76711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 72863000 # number of demand (read+write) miss cycles 76811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 204347803500 # number of demand (read+write) miss cycles 76911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 204420666500 # number of demand (read+write) miss cycles 77011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 72863000 # number of overall miss cycles 77111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 204347803500 # number of overall miss cycles 77211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 204420666500 # number of overall miss cycles 77311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 3670078 # number of WritebackDirty accesses(hits+misses) 77411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 3670078 # number of WritebackDirty accesses(hits+misses) 77511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 77611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 77711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 1890833 # number of ReadExReq accesses(hits+misses) 77811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 1890833 # number of ReadExReq accesses(hits+misses) 77911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses) 78011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses) 78111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333448 # number of ReadSharedReq accesses(hits+misses) 78211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 7333448 # number of ReadSharedReq accesses(hits+misses) 78311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 822 # number of demand (read+write) accesses 78411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 9224281 # number of demand (read+write) accesses 78511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 9225103 # number of demand (read+write) accesses 78611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 822 # number of overall (read+write) accesses 78711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 9224281 # number of overall (read+write) accesses 78811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 9225103 # number of overall (read+write) accesses 78911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429619 # miss rate for ReadExReq accesses 79011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.429619 # miss rate for ReadExReq accesses 79111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954988 # miss rate for ReadCleanReq accesses 79211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954988 # miss rate for ReadCleanReq accesses 79311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170683 # miss rate for ReadSharedReq accesses 79411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170683 # miss rate for ReadSharedReq accesses 79511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses 79611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.223761 # miss rate for demand accesses 79711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.223826 # miss rate for demand accesses 79811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses 79911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.223761 # miss rate for overall accesses 80011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.223826 # miss rate for overall accesses 80111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96346.202566 # average ReadExReq miss latency 80211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 96346.202566 # average ReadExReq miss latency 80311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92819.108280 # average ReadCleanReq miss latency 80411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92819.108280 # average ReadCleanReq miss latency 80511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100729.028454 # average ReadSharedReq miss latency 80611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100729.028454 # average ReadSharedReq miss latency 80711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92819.108280 # average overall miss latency 80811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 99004.087869 # average overall miss latency 80911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 99001.736472 # average overall miss latency 81011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92819.108280 # average overall miss latency 81111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 99004.087869 # average overall miss latency 81211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 99001.736472 # average overall miss latency 81311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 81411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 81511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 81611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 81711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 81811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81911860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 1060173 # number of writebacks 82011860Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 1060173 # number of writebacks 82111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 7 # number of ReadSharedReq MSHR hits 82211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 7 # number of ReadSharedReq MSHR hits 82311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits 82411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 82511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits 82611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits 82711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses 82811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses 82911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812338 # number of ReadExReq MSHR misses 83011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 812338 # number of ReadExReq MSHR misses 83111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses 83211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses 83311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251689 # number of ReadSharedReq MSHR misses 83411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251689 # number of ReadSharedReq MSHR misses 83511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses 83611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 2064027 # number of demand (read+write) MSHR misses 83711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 2064812 # number of demand (read+write) MSHR misses 83811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses 83911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 2064027 # number of overall MSHR misses 84011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 2064812 # number of overall MSHR misses 84111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70142301500 # number of ReadExReq MSHR miss cycles 84211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70142301500 # number of ReadExReq MSHR miss cycles 84311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65013000 # number of ReadCleanReq MSHR miss cycles 84411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65013000 # number of ReadCleanReq MSHR miss cycles 84511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113564745500 # number of ReadSharedReq MSHR miss cycles 84611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113564745500 # number of ReadSharedReq MSHR miss cycles 84711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65013000 # number of demand (read+write) MSHR miss cycles 84811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183707047000 # number of demand (read+write) MSHR miss cycles 84911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 183772060000 # number of demand (read+write) MSHR miss cycles 85011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65013000 # number of overall MSHR miss cycles 85111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183707047000 # number of overall MSHR miss cycles 85211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 183772060000 # number of overall MSHR miss cycles 85311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 85411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 85511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429619 # mshr miss rate for ReadExReq accesses 85611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429619 # mshr miss rate for ReadExReq accesses 85711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses 85811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses 85911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170682 # mshr miss rate for ReadSharedReq accesses 86011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170682 # mshr miss rate for ReadSharedReq accesses 86111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses 86211860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for demand accesses 86311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.223825 # mshr miss rate for demand accesses 86411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses 86511860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for overall accesses 86611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.223825 # mshr miss rate for overall accesses 86711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86346.202566 # average ReadExReq mshr miss latency 86811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86346.202566 # average ReadExReq mshr miss latency 86911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82819.108280 # average ReadCleanReq mshr miss latency 87011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82819.108280 # average ReadCleanReq mshr miss latency 87111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90729.203101 # average ReadSharedReq mshr miss latency 87211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90729.203101 # average ReadSharedReq mshr miss latency 87311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency 87411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency 87511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency 87611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency 87711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency 87811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency 87911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 18445321 # Total number of requests made to the snoop filter. 88011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 9220230 # Number of requests hitting in the snoop filter with a single holder of the requested data. 88111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 88211680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. 88311680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 88411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 88511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 88611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 7334270 # Transaction distribution 88711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 4730251 # Transaction distribution 88811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution 88911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 6522313 # Transaction distribution 89011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 1890833 # Transaction distribution 89111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 1890833 # Transaction distribution 89211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution 89311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 7333448 # Transaction distribution 89411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) 89511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668747 # Packet count per connected master and slave (bytes) 89611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 27670424 # Packet count per connected master and slave (bytes) 89711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) 89811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825238976 # Cumulative packet size per connected master and slave (bytes) 89911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 825293696 # Cumulative packet size per connected master and slave (bytes) 90011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 2032379 # Total snoops (count) 90111860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopTraffic 67851072 # Total snoop traffic (bytes) 90211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 11257482 # Request fanout histogram 90311680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram 90411680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram 90511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 90611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 11254432 99.97% 99.97% # Request fanout histogram 90711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram 90811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 90911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 91011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 91111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 91211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 11257482 # Request fanout histogram 91311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 12892771500 # Layer occupancy (ticks) 91411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 91511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) 91611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 91711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 13836424993 # Layer occupancy (ticks) 91811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 91911860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 4095962 # Total number of requests made to the snoop filter. 92011860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 2031307 # Number of requests hitting in the snoop filter with a single holder of the requested data. 92111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 92211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 92311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 92411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 92511860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states 92611860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 1252474 # Transaction distribution 92711860Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1060173 # Transaction distribution 92811860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 970977 # Transaction distribution 92911860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 812338 # Transaction distribution 93011860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 812338 # Transaction distribution 93111860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 1252474 # Transaction distribution 93211860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160774 # Packet count per connected master and slave (bytes) 93311860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 6160774 # Packet count per connected master and slave (bytes) 93411860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199999040 # Cumulative packet size per connected master and slave (bytes) 93511860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 199999040 # Cumulative packet size per connected master and slave (bytes) 93611507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 93711570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 93811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2064812 # Request fanout histogram 93911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 94011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 94111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 94211860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 2064812 100.00% 100.00% # Request fanout histogram 94311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 94411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 94511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 94611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 94711860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2064812 # Request fanout histogram 94811860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 8805297000 # Layer occupancy (ticks) 94911507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.8 # Layer utilization (%) 95011860Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 11285202500 # Layer occupancy (ticks) 95111507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 1.0 # Layer utilization (%) 95211507SCurtis.Dunham@arm.com 95311507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 954