stats.txt revision 9568:cd1351d4d850
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.025578 # Number of seconds simulated 4sim_ticks 25577832000 # Number of ticks simulated 5final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 133487 # Simulator instruction rate (inst/s) 8host_op_rate 189436 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48151664 # Simulator tick rate (ticks/s) 10host_mem_usage 268312 # Number of bytes of host memory used 11host_seconds 531.19 # Real time elapsed on the host 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 100626876 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 128779 # Total number of read requests seen 38system.physmem.writeReqs 83944 # Total number of write requests seen 39system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 8241856 # Total number of bytes read from memory 41system.physmem.bytesWritten 5372416 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 25577735000 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 128779 # Categorize read packet sizes 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes 94system.physmem.writePktSize::6 83944 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 127system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 159system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests 161system.physmem.totBusLat 643885000 # Total cycles spent in databus access 162system.physmem.totBankLat 1400217500 # Total cycles spent in bank access 163system.physmem.avgQLat 24884.85 # Average queueing delay per request 164system.physmem.avgBankLat 10873.20 # Average bank access latency per request 165system.physmem.avgBusLat 5000.00 # Average bus latency per request 166system.physmem.avgMemAccLat 40758.05 # Average memory access latency 167system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 172system.physmem.busUtil 4.16 # Data bus utilization in percentage 173system.physmem.avgRdQLen 0.21 # Average read queue length over time 174system.physmem.avgWrQLen 9.73 # Average write queue length over time 175system.physmem.readRowHits 116758 # Number of row buffer hits during reads 176system.physmem.writeRowHits 52879 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes 179system.physmem.avgGap 120239.63 # Average gap between requests 180system.cpu.branchPred.lookups 16629564 # Number of BP lookups 181system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 186system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage 187system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions. 189system.cpu.dtb.inst_hits 0 # ITB inst hits 190system.cpu.dtb.inst_misses 0 # ITB inst misses 191system.cpu.dtb.read_hits 0 # DTB read hits 192system.cpu.dtb.read_misses 0 # DTB read misses 193system.cpu.dtb.write_hits 0 # DTB write hits 194system.cpu.dtb.write_misses 0 # DTB write misses 195system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 196system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 197system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 198system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 199system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 200system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 201system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 202system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 203system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 204system.cpu.dtb.read_accesses 0 # DTB read accesses 205system.cpu.dtb.write_accesses 0 # DTB write accesses 206system.cpu.dtb.inst_accesses 0 # ITB inst accesses 207system.cpu.dtb.hits 0 # DTB hits 208system.cpu.dtb.misses 0 # DTB misses 209system.cpu.dtb.accesses 0 # DTB accesses 210system.cpu.itb.inst_hits 0 # ITB inst hits 211system.cpu.itb.inst_misses 0 # ITB inst misses 212system.cpu.itb.read_hits 0 # DTB read hits 213system.cpu.itb.read_misses 0 # DTB read misses 214system.cpu.itb.write_hits 0 # DTB write hits 215system.cpu.itb.write_misses 0 # DTB write misses 216system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 217system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 218system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 219system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 220system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 221system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 222system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 223system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 224system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 225system.cpu.itb.read_accesses 0 # DTB read accesses 226system.cpu.itb.write_accesses 0 # DTB write accesses 227system.cpu.itb.inst_accesses 0 # ITB inst accesses 228system.cpu.itb.hits 0 # DTB hits 229system.cpu.itb.misses 0 # DTB misses 230system.cpu.itb.accesses 0 # DTB accesses 231system.cpu.workload.num_syscalls 1946 # Number of system calls 232system.cpu.numCycles 51155665 # number of cpu cycles simulated 233system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 234system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 235system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss 236system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed 237system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered 238system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken 239system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked 240system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing 241system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked 242system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 243system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps 244system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR 245system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched 246system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed 247system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle 265system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle 266system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle 267system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked 268system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running 269system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking 270system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing 271system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch 272system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction 273system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode 274system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode 275system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing 276system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle 277system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking 278system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst 279system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running 280system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking 281system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename 282system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full 283system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full 284system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full 285system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers 286system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed 287system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made 288system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups 289system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups 290system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed 291system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing 292system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed 293system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed 294system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer 295system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit. 296system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit. 297system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads. 298system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores. 299system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec) 300system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ 301system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued 302system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued 303system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling 304system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph 305system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed 306system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle 323system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 324system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available 325system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available 326system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available 327system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available 328system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available 329system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available 332system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available 353system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available 354system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available 355system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 356system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 357system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 358system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued 359system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued 360system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued 361system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued 362system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued 363system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued 364system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued 365system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued 366system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.89% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.89% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.89% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.89% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.89% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.89% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.89% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.89% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.89% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued 387system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued 388system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued 389system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 390system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 391system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued 392system.cpu.iq.rate 2.096836 # Inst issue rate 393system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested 394system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst) 395system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads 396system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes 397system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses 398system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads 399system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes 400system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses 401system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses 402system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses 403system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores 404system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 405system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed 406system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed 407system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations 408system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed 409system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 410system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 411system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled 412system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked 413system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 414system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing 415system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking 416system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking 417system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ 418system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch 419system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions 420system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions 421system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions 422system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall 423system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall 424system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations 425system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly 426system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly 427system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute 428system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions 429system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed 430system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute 431system.cpu.iew.exec_swp 0 # number of swp insts executed 432system.cpu.iew.exec_nop 9761 # number of nop insts executed 433system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed 434system.cpu.iew.exec_branches 14602542 # Number of branches executed 435system.cpu.iew.exec_stores 21344564 # Number of stores executed 436system.cpu.iew.exec_rate 2.076700 # Inst execution rate 437system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit 438system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back 439system.cpu.iew.wb_producers 53282087 # num instructions producing a value 440system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value 441system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 442system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle 443system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back 444system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 445system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit 446system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 447system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted 448system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle 465system.cpu.commit.committedInsts 70913181 # Number of instructions committed 466system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed 467system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 468system.cpu.commit.refs 47862846 # Number of memory references committed 469system.cpu.commit.loads 27307108 # Number of loads committed 470system.cpu.commit.membars 15920 # Number of memory barriers committed 471system.cpu.commit.branches 13741505 # Number of branches committed 472system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 473system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. 474system.cpu.commit.function_calls 1679850 # Number of function calls committed. 475system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached 476system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 477system.cpu.rob.rob_reads 149959530 # The number of ROB reads 478system.cpu.rob.rob_writes 224865260 # The number of ROB writes 479system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself 480system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling 481system.cpu.committedInsts 70907629 # Number of Instructions Simulated 482system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated 483system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated 484system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction 485system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads 486system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle 487system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads 488system.cpu.int_regfile_reads 511661173 # number of integer regfile reads 489system.cpu.int_regfile_writes 103341311 # number of integer regfile writes 490system.cpu.fp_regfile_reads 804 # number of floating regfile reads 491system.cpu.fp_regfile_writes 688 # number of floating regfile writes 492system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads 493system.cpu.misc_regfile_writes 31840 # number of misc regfile writes 494system.cpu.icache.replacements 28586 # number of replacements 495system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use 496system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks. 497system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks. 498system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks. 499system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 500system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor 501system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy 502system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy 503system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits 504system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits 505system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits 506system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits 507system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits 508system.cpu.icache.overall_hits::total 11645446 # number of overall hits 509system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses 510system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses 511system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses 512system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses 513system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses 514system.cpu.icache.overall_misses::total 34686 # number of overall misses 515system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles 516system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles 517system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles 518system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles 519system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles 520system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles 521system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses) 522system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses) 523system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses 524system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses 525system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses 526system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses 527system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses 528system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses 529system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses 530system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses 531system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses 532system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses 533system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency 534system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency 535system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency 536system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency 537system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency 538system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency 539system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked 540system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 541system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked 542system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 543system.cpu.icache.avg_blocked_cycles::no_mshrs 30.440000 # average number of cycles each access was blocked 544system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 545system.cpu.icache.fast_writes 0 # number of fast writes performed 546system.cpu.icache.cache_copies 0 # number of cache copies performed 547system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3741 # number of ReadReq MSHR hits 548system.cpu.icache.ReadReq_mshr_hits::total 3741 # number of ReadReq MSHR hits 549system.cpu.icache.demand_mshr_hits::cpu.inst 3741 # number of demand (read+write) MSHR hits 550system.cpu.icache.demand_mshr_hits::total 3741 # number of demand (read+write) MSHR hits 551system.cpu.icache.overall_mshr_hits::cpu.inst 3741 # number of overall MSHR hits 552system.cpu.icache.overall_mshr_hits::total 3741 # number of overall MSHR hits 553system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30945 # number of ReadReq MSHR misses 554system.cpu.icache.ReadReq_mshr_misses::total 30945 # number of ReadReq MSHR misses 555system.cpu.icache.demand_mshr_misses::cpu.inst 30945 # number of demand (read+write) MSHR misses 556system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses 557system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses 558system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses 559system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles 560system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles 561system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles 562system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles 563system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles 564system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles 565system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses 566system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses 567system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses 568system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses 569system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses 570system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses 571system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency 572system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency 573system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency 574system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency 575system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency 576system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency 577system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 578system.cpu.l2cache.replacements 95649 # number of replacements 579system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use 580system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks. 581system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks. 582system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks. 583system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 584system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor 585system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor 586system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor 587system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy 588system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy 589system.cpu.l2cache.occ_percent::cpu.data 0.054317 # Average percentage of cache occupancy 590system.cpu.l2cache.occ_percent::total 0.918275 # Average percentage of cache occupancy 591system.cpu.l2cache.ReadReq_hits::cpu.inst 25825 # number of ReadReq hits 592system.cpu.l2cache.ReadReq_hits::cpu.data 33460 # number of ReadReq hits 593system.cpu.l2cache.ReadReq_hits::total 59285 # number of ReadReq hits 594system.cpu.l2cache.Writeback_hits::writebacks 129109 # number of Writeback hits 595system.cpu.l2cache.Writeback_hits::total 129109 # number of Writeback hits 596system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 597system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 598system.cpu.l2cache.ReadExReq_hits::cpu.data 4785 # number of ReadExReq hits 599system.cpu.l2cache.ReadExReq_hits::total 4785 # number of ReadExReq hits 600system.cpu.l2cache.demand_hits::cpu.inst 25825 # number of demand (read+write) hits 601system.cpu.l2cache.demand_hits::cpu.data 38245 # number of demand (read+write) hits 602system.cpu.l2cache.demand_hits::total 64070 # number of demand (read+write) hits 603system.cpu.l2cache.overall_hits::cpu.inst 25825 # number of overall hits 604system.cpu.l2cache.overall_hits::cpu.data 38245 # number of overall hits 605system.cpu.l2cache.overall_hits::total 64070 # number of overall hits 606system.cpu.l2cache.ReadReq_misses::cpu.inst 4676 # number of ReadReq misses 607system.cpu.l2cache.ReadReq_misses::cpu.data 21922 # number of ReadReq misses 608system.cpu.l2cache.ReadReq_misses::total 26598 # number of ReadReq misses 609system.cpu.l2cache.UpgradeReq_misses::cpu.data 312 # number of UpgradeReq misses 610system.cpu.l2cache.UpgradeReq_misses::total 312 # number of UpgradeReq misses 611system.cpu.l2cache.ReadExReq_misses::cpu.data 102257 # number of ReadExReq misses 612system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses 613system.cpu.l2cache.demand_misses::cpu.inst 4676 # number of demand (read+write) misses 614system.cpu.l2cache.demand_misses::cpu.data 124179 # number of demand (read+write) misses 615system.cpu.l2cache.demand_misses::total 128855 # number of demand (read+write) misses 616system.cpu.l2cache.overall_misses::cpu.inst 4676 # number of overall misses 617system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses 618system.cpu.l2cache.overall_misses::total 128855 # number of overall misses 619system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles 620system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles 621system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles 622system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles 623system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles 624system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles 625system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles 626system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles 627system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles 628system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles 629system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles 630system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles 631system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles 632system.cpu.l2cache.ReadReq_accesses::cpu.inst 30501 # number of ReadReq accesses(hits+misses) 633system.cpu.l2cache.ReadReq_accesses::cpu.data 55382 # number of ReadReq accesses(hits+misses) 634system.cpu.l2cache.ReadReq_accesses::total 85883 # number of ReadReq accesses(hits+misses) 635system.cpu.l2cache.Writeback_accesses::writebacks 129109 # number of Writeback accesses(hits+misses) 636system.cpu.l2cache.Writeback_accesses::total 129109 # number of Writeback accesses(hits+misses) 637system.cpu.l2cache.UpgradeReq_accesses::cpu.data 332 # number of UpgradeReq accesses(hits+misses) 638system.cpu.l2cache.UpgradeReq_accesses::total 332 # number of UpgradeReq accesses(hits+misses) 639system.cpu.l2cache.ReadExReq_accesses::cpu.data 107042 # number of ReadExReq accesses(hits+misses) 640system.cpu.l2cache.ReadExReq_accesses::total 107042 # number of ReadExReq accesses(hits+misses) 641system.cpu.l2cache.demand_accesses::cpu.inst 30501 # number of demand (read+write) accesses 642system.cpu.l2cache.demand_accesses::cpu.data 162424 # number of demand (read+write) accesses 643system.cpu.l2cache.demand_accesses::total 192925 # number of demand (read+write) accesses 644system.cpu.l2cache.overall_accesses::cpu.inst 30501 # number of overall (read+write) accesses 645system.cpu.l2cache.overall_accesses::cpu.data 162424 # number of overall (read+write) accesses 646system.cpu.l2cache.overall_accesses::total 192925 # number of overall (read+write) accesses 647system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.153306 # miss rate for ReadReq accesses 648system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395833 # miss rate for ReadReq accesses 649system.cpu.l2cache.ReadReq_miss_rate::total 0.309700 # miss rate for ReadReq accesses 650system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.939759 # miss rate for UpgradeReq accesses 651system.cpu.l2cache.UpgradeReq_miss_rate::total 0.939759 # miss rate for UpgradeReq accesses 652system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955298 # miss rate for ReadExReq accesses 653system.cpu.l2cache.ReadExReq_miss_rate::total 0.955298 # miss rate for ReadExReq accesses 654system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153306 # miss rate for demand accesses 655system.cpu.l2cache.demand_miss_rate::cpu.data 0.764536 # miss rate for demand accesses 656system.cpu.l2cache.demand_miss_rate::total 0.667902 # miss rate for demand accesses 657system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153306 # miss rate for overall accesses 658system.cpu.l2cache.overall_miss_rate::cpu.data 0.764536 # miss rate for overall accesses 659system.cpu.l2cache.overall_miss_rate::total 0.667902 # miss rate for overall accesses 660system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency 661system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency 662system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency 663system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.717949 # average UpgradeReq miss latency 664system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.717949 # average UpgradeReq miss latency 665system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency 666system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency 667system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency 668system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency 669system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency 670system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency 671system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency 672system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency 673system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 674system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 675system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 677system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 678system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 679system.cpu.l2cache.fast_writes 0 # number of fast writes performed 680system.cpu.l2cache.cache_copies 0 # number of cache copies performed 681system.cpu.l2cache.writebacks::writebacks 83944 # number of writebacks 682system.cpu.l2cache.writebacks::total 83944 # number of writebacks 683system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits 684system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 685system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits 686system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits 687system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits 688system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits 689system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits 690system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits 691system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits 692system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses 693system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses 694system.cpu.l2cache.ReadReq_mshr_misses::total 26522 # number of ReadReq MSHR misses 695system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 312 # number of UpgradeReq MSHR misses 696system.cpu.l2cache.UpgradeReq_mshr_misses::total 312 # number of UpgradeReq MSHR misses 697system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses 698system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses 699system.cpu.l2cache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.demand_mshr_misses::total 128779 # number of demand (read+write) MSHR misses 702system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses 703system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses 704system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses 705system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles 707system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles 708system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles 709system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles 710system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles 711system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles 712system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles 713system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles 714system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles 715system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles 716system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles 717system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles 718system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses 721system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.939759 # mshr miss rate for UpgradeReq accesses 722system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.939759 # mshr miss rate for UpgradeReq accesses 723system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955298 # mshr miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955298 # mshr miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for demand accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 # mshr miss rate for demand accesses 728system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses 731system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency 732system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency 733system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency 734system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency 735system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency 736system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency 744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 745system.cpu.dcache.replacements 158328 # number of replacements 746system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use 747system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks. 748system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks. 749system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks. 750system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. 751system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor 752system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy 753system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy 754system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits 755system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits 756system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits 757system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits 758system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits 759system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits 760system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 761system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 762system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits 763system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits 764system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits 765system.cpu.dcache.overall_hits::total 44337915 # number of overall hits 766system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses 767system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses 768system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses 769system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses 770system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses 771system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses 772system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses 773system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses 774system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses 775system.cpu.dcache.overall_misses::total 1707154 # number of overall misses 776system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles 777system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles 778system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles 780system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles 782system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles 783system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles 784system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles 785system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles 786system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses) 787system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses) 788system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16026 # number of LoadLockedReq accesses(hits+misses) 791system.cpu.dcache.LoadLockedReq_accesses::total 16026 # number of LoadLockedReq accesses(hits+misses) 792system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 793system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 794system.cpu.dcache.demand_accesses::cpu.data 46045069 # number of demand (read+write) accesses 795system.cpu.dcache.demand_accesses::total 46045069 # number of demand (read+write) accesses 796system.cpu.dcache.overall_accesses::cpu.data 46045069 # number of overall (read+write) accesses 797system.cpu.dcache.overall_accesses::total 46045069 # number of overall (read+write) accesses 798system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses 800system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079732 # miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_miss_rate::total 0.079732 # miss rate for WriteReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002808 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002808 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 # miss rate for demand accesses 805system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses 806system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses 807system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses 808system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency 809system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency 814system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency 815system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency 816system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency 817system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency 818system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked 819system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked 820system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked 821system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked 822system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked 823system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked 824system.cpu.dcache.fast_writes 0 # number of fast writes performed 825system.cpu.dcache.cache_copies 0 # number of cache copies performed 826system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks 827system.cpu.dcache.writebacks::total 129109 # number of writebacks 828system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits 829system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits 830system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits 831system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits 832system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits 833system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits 834system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits 835system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits 836system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits 837system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits 838system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses 839system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses 840system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses 841system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses 842system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses 843system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses 844system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses 845system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses 846system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles 847system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles 848system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles 849system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles 850system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles 851system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles 852system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles 853system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles 854system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses 855system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses 856system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses 857system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses 858system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses 859system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses 860system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses 861system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses 862system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency 864system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency 870system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 871 872---------- End Simulation Statistics ---------- 873