stats.txt revision 9378:36ed6d4654bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026292 # Number of seconds simulated 4sim_ticks 26292466000 # Number of ticks simulated 5final_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 139577 # Simulator instruction rate (inst/s) 8host_op_rate 198063 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51742306 # Simulator tick rate (ticks/s) 10host_mem_usage 305460 # Number of bytes of host memory used 11host_seconds 508.14 # Real time elapsed on the host 12sim_insts 70925094 # Number of instructions simulated 13sim_ops 100644341 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 11350476 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 302110574 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 313461050 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 11350476 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 11350476 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 204330472 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 204330472 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 204330472 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 11350476 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 302110574 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 517791522 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 128777 # Total number of read requests seen 38system.physmem.writeReqs 83943 # Total number of write requests seen 39system.physmem.cpureqs 213018 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 8241664 # Total number of bytes read from memory 41system.physmem.bytesWritten 5372352 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 5372352 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 298 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 8167 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 8037 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 7896 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 7927 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 8024 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 7958 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 7983 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 8195 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 8177 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 8153 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 8060 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 8008 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 7983 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 5171 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 5231 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 5234 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 5166 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 5164 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 5232 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 5372 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 26292446500 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 128777 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 83943 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 298 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 71059 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 55263 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 2369 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 3590 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 4868161034 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 6756433034 # Sum of mem lat for all requests 176system.physmem.totBusLat 515096000 # Total cycles spent in databus access 177system.physmem.totBankLat 1373176000 # Total cycles spent in bank access 178system.physmem.avgQLat 37803.91 # Average queueing delay per request 179system.physmem.avgBankLat 10663.46 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 52467.37 # Average memory access latency 182system.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 204.33 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 3.24 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.26 # Average read queue length over time 189system.physmem.avgWrQLen 9.45 # Average write queue length over time 190system.physmem.readRowHits 118938 # Number of row buffer hits during reads 191system.physmem.writeRowHits 27082 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 32.26 # Row buffer hit rate for writes 194system.physmem.avgGap 123601.20 # Average gap between requests 195system.cpu.dtb.inst_hits 0 # ITB inst hits 196system.cpu.dtb.inst_misses 0 # ITB inst misses 197system.cpu.dtb.read_hits 0 # DTB read hits 198system.cpu.dtb.read_misses 0 # DTB read misses 199system.cpu.dtb.write_hits 0 # DTB write hits 200system.cpu.dtb.write_misses 0 # DTB write misses 201system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 202system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 203system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 204system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 205system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 206system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 207system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 208system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 209system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 210system.cpu.dtb.read_accesses 0 # DTB read accesses 211system.cpu.dtb.write_accesses 0 # DTB write accesses 212system.cpu.dtb.inst_accesses 0 # ITB inst accesses 213system.cpu.dtb.hits 0 # DTB hits 214system.cpu.dtb.misses 0 # DTB misses 215system.cpu.dtb.accesses 0 # DTB accesses 216system.cpu.itb.inst_hits 0 # ITB inst hits 217system.cpu.itb.inst_misses 0 # ITB inst misses 218system.cpu.itb.read_hits 0 # DTB read hits 219system.cpu.itb.read_misses 0 # DTB read misses 220system.cpu.itb.write_hits 0 # DTB write hits 221system.cpu.itb.write_misses 0 # DTB write misses 222system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 223system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 224system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 225system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 226system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 227system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 228system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 229system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 230system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu.itb.read_accesses 0 # DTB read accesses 232system.cpu.itb.write_accesses 0 # DTB write accesses 233system.cpu.itb.inst_accesses 0 # ITB inst accesses 234system.cpu.itb.hits 0 # DTB hits 235system.cpu.itb.misses 0 # DTB misses 236system.cpu.itb.accesses 0 # DTB accesses 237system.cpu.workload.num_syscalls 1946 # Number of system calls 238system.cpu.numCycles 52584933 # number of cpu cycles simulated 239system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 240system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 241system.cpu.BPredUnit.lookups 16605622 # Number of BP lookups 242system.cpu.BPredUnit.condPredicted 12744819 # Number of conditional branches predicted 243system.cpu.BPredUnit.condIncorrect 601134 # Number of conditional branches incorrect 244system.cpu.BPredUnit.BTBLookups 10608037 # Number of BTB lookups 245system.cpu.BPredUnit.BTBHits 7769778 # Number of BTB hits 246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 247system.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target. 248system.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions. 249system.cpu.fetch.icacheStallCycles 12549160 # Number of cycles fetch is stalled on an Icache miss 250system.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed 251system.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered 252system.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken 253system.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked 254system.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing 255system.cpu.fetch.BlockedCycles 10606958 # Number of cycles fetch has spent blocked 256system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 257system.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps 258system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR 259system.cpu.fetch.CacheLines 11672224 # Number of cache lines fetched 260system.cpu.fetch.IcacheSquashes 180779 # Number of outstanding Icache misses that were squashed 261system.cpu.fetch.rateDist::samples 46048900 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::mean 2.587178 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::0 24897026 54.07% 54.07% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::4 1463280 3.18% 70.59% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::5 1379331 3.00% 73.59% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::6 959670 2.08% 75.67% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::7 1190775 2.59% 78.26% # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::total 46048900 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle 279system.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle 280system.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle 281system.cpu.decode.BlockedCycles 8956467 # Number of cycles decode is blocked 282system.cpu.decode.RunCycles 19461806 # Number of cycles decode is running 283system.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking 284system.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing 285system.cpu.decode.BranchResolved 3326611 # Number of times decode resolved a branch 286system.cpu.decode.BranchMispred 104659 # Number of times decode detected a branch misprediction 287system.cpu.decode.DecodedInsts 116720432 # Number of instructions handled by decode 288system.cpu.decode.SquashedInsts 360894 # Number of squashed instructions handled by decode 289system.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing 290system.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle 291system.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking 292system.cpu.rename.serializeStallCycles 926852 # count of cycles rename stalled for serializing inst 293system.cpu.rename.RunCycles 19086495 # Number of cycles rename is running 294system.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking 295system.cpu.rename.RenamedInsts 114852318 # Number of instructions processed by rename 296system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full 297system.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full 298system.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full 299system.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers 300system.cpu.rename.RenamedOperands 115176508 # Number of destination operands rename has renamed 301system.cpu.rename.RenameLookups 529186359 # Number of register rename lookups that rename has made 302system.cpu.rename.int_rename_lookups 529181674 # Number of integer rename lookups 303system.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups 304system.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed 305system.cpu.rename.UndoneMaps 16015892 # Number of HB maps that are undone due to squashing 306system.cpu.rename.serializingInsts 24809 # count of serializing insts renamed 307system.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed 308system.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer 309system.cpu.memDep0.insertedLoads 29582757 # Number of loads inserted to the mem dependence unit. 310system.cpu.memDep0.insertedStores 22430841 # Number of stores inserted to the mem dependence unit. 311system.cpu.memDep0.conflictingLoads 3912004 # Number of conflicting loads. 312system.cpu.memDep0.conflictingStores 4391398 # Number of conflicting stores. 313system.cpu.iq.iqInstsAdded 111440700 # Number of instructions added to the IQ (excludes non-spec) 314system.cpu.iq.iqNonSpecInstsAdded 41006 # Number of non-speculative instructions added to the IQ 315system.cpu.iq.iqInstsIssued 107204361 # Number of instructions issued 316system.cpu.iq.iqSquashedInstsIssued 269260 # Number of squashed instructions issued 317system.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling 318system.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph 319system.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed 320system.cpu.iq.issued_per_cycle::samples 46048900 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::0 10795987 23.44% 23.44% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::4 5412181 11.75% 84.41% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::5 3900032 8.47% 92.88% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::6 1833850 3.98% 96.87% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::7 869462 1.89% 98.75% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::total 46048900 # Number of insts issued each cycle 337system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available 340system.cpu.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available 345system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available 346system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available 367system.cpu.iq.fu_full::MemRead 1351687 54.87% 59.36% # attempts to use FU when none available 368system.cpu.iq.fu_full::MemWrite 1001007 40.64% 100.00% # attempts to use FU when none available 369system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 370system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 371system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 372system.cpu.iq.FU_type_0::IntAlu 56616683 52.81% 52.81% # Type of FU issued 373system.cpu.iq.FU_type_0::IntMult 91709 0.09% 52.90% # Type of FU issued 374system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatAdd 161 0.00% 52.90% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued 380system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued 401system.cpu.iq.FU_type_0::MemRead 28875176 26.93% 79.83% # Type of FU issued 402system.cpu.iq.FU_type_0::MemWrite 21620625 20.17% 100.00% # Type of FU issued 403system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 404system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 405system.cpu.iq.FU_type_0::total 107204361 # Type of FU issued 406system.cpu.iq.rate 2.038690 # Inst issue rate 407system.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested 408system.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst) 409system.cpu.iq.int_inst_queue_reads 263189734 # Number of integer instruction queue reads 410system.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes 411system.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses 412system.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads 413system.cpu.iq.fp_inst_queue_writes 696 # Number of floating instruction queue writes 414system.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses 415system.cpu.iq.int_alu_accesses 109667441 # Number of integer alu accesses 416system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses 417system.cpu.iew.lsq.thread0.forwLoads 2181528 # Number of loads that had data forwarded from stores 418system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 419system.cpu.iew.lsq.thread0.squashedLoads 2272156 # Number of loads squashed 420system.cpu.iew.lsq.thread0.ignoredResponses 6578 # Number of memory responses ignored because the instruction is squashed 421system.cpu.iew.lsq.thread0.memOrderViolation 29396 # Number of memory ordering violations 422system.cpu.iew.lsq.thread0.squashedStores 1871610 # Number of stores squashed 423system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 424system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 425system.cpu.iew.lsq.thread0.rescheduledLoads 28 # Number of loads that were rescheduled 426system.cpu.iew.lsq.thread0.cacheBlocked 493 # Number of times an access to memory failed due to the cache being blocked 427system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 428system.cpu.iew.iewSquashCycles 1617500 # Number of cycles IEW is squashing 429system.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking 430system.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking 431system.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ 432system.cpu.iew.iewDispSquashedInsts 290951 # Number of squashed instructions skipped by dispatch 433system.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions 434system.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions 435system.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions 436system.cpu.iew.iewIQFullEvents 6480 # Number of times the IQ has become full, causing a stall 437system.cpu.iew.iewLSQFullEvents 5483 # Number of times the LSQ has become full, causing a stall 438system.cpu.iew.memOrderViolationEvents 29396 # Number of memory order violations 439system.cpu.iew.predictedTakenIncorrect 390184 # Number of branches that were predicted taken incorrectly 440system.cpu.iew.predictedNotTakenIncorrect 182395 # Number of branches that were predicted not taken incorrectly 441system.cpu.iew.branchMispredicts 572579 # Number of branch mispredicts detected at execute 442system.cpu.iew.iewExecutedInsts 106179962 # Number of executed instructions 443system.cpu.iew.iewExecLoadInsts 28578383 # Number of load instructions executed 444system.cpu.iew.iewExecSquashedInsts 1024399 # Number of squashed instructions skipped in execute 445system.cpu.iew.exec_swp 0 # number of swp insts executed 446system.cpu.iew.exec_nop 9804 # number of nop insts executed 447system.cpu.iew.exec_refs 49916161 # number of memory reference insts executed 448system.cpu.iew.exec_branches 14598129 # Number of branches executed 449system.cpu.iew.exec_stores 21337778 # Number of stores executed 450system.cpu.iew.exec_rate 2.019209 # Inst execution rate 451system.cpu.iew.wb_sent 105751543 # cumulative count of insts sent to commit 452system.cpu.iew.wb_count 105534073 # cumulative count of insts written-back 453system.cpu.iew.wb_producers 53248858 # num instructions producing a value 454system.cpu.iew.wb_consumers 103476528 # num instructions consuming a value 455system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 456system.cpu.iew.wb_rate 2.006926 # insts written-back per cycle 457system.cpu.iew.wb_fanout 0.514598 # average fanout of values written-back 458system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 459system.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit 460system.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards 461system.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted 462system.cpu.commit.committed_per_cycle::samples 44431401 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::0 15343377 34.53% 34.53% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::4 1877627 4.23% 79.25% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::5 1953879 4.40% 83.65% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::6 688656 1.55% 85.20% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::7 567495 1.28% 86.48% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::total 44431401 # Number of insts commited each cycle 479system.cpu.commit.committedInsts 70930646 # Number of instructions committed 480system.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed 481system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 482system.cpu.commit.refs 47869832 # Number of memory references committed 483system.cpu.commit.loads 27310601 # Number of loads committed 484system.cpu.commit.membars 15920 # Number of memory barriers committed 485system.cpu.commit.branches 13744998 # Number of branches committed 486system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 487system.cpu.commit.int_insts 91486751 # Number of committed integer instructions. 488system.cpu.commit.function_calls 1679850 # Number of function calls committed. 489system.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached 490system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 491system.cpu.rob.rob_reads 149890854 # The number of ROB reads 492system.cpu.rob.rob_writes 224611140 # The number of ROB writes 493system.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself 494system.cpu.idleCycles 6536033 # Total number of cycles that the CPU has spent unscheduled due to idling 495system.cpu.committedInsts 70925094 # Number of Instructions Simulated 496system.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated 497system.cpu.committedInsts_total 70925094 # Number of Instructions Simulated 498system.cpu.cpi 0.741415 # CPI: Cycles Per Instruction 499system.cpu.cpi_total 0.741415 # CPI: Total CPI of All Threads 500system.cpu.ipc 1.348772 # IPC: Instructions Per Cycle 501system.cpu.ipc_total 1.348772 # IPC: Total IPC of All Threads 502system.cpu.int_regfile_reads 511431338 # number of integer regfile reads 503system.cpu.int_regfile_writes 103318196 # number of integer regfile writes 504system.cpu.fp_regfile_reads 686 # number of floating regfile reads 505system.cpu.fp_regfile_writes 582 # number of floating regfile writes 506system.cpu.misc_regfile_reads 49170129 # number of misc regfile reads 507system.cpu.misc_regfile_writes 38826 # number of misc regfile writes 508system.cpu.icache.replacements 30543 # number of replacements 509system.cpu.icache.tagsinuse 1820.333452 # Cycle average of tags in use 510system.cpu.icache.total_refs 11635566 # Total number of references to valid blocks. 511system.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks. 512system.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks. 513system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 514system.cpu.icache.occ_blocks::cpu.inst 1820.333452 # Average occupied blocks per requestor 515system.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy 516system.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy 517system.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits 518system.cpu.icache.ReadReq_hits::total 11635567 # number of ReadReq hits 519system.cpu.icache.demand_hits::cpu.inst 11635567 # number of demand (read+write) hits 520system.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits 521system.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits 522system.cpu.icache.overall_hits::total 11635567 # number of overall hits 523system.cpu.icache.ReadReq_misses::cpu.inst 36657 # number of ReadReq misses 524system.cpu.icache.ReadReq_misses::total 36657 # number of ReadReq misses 525system.cpu.icache.demand_misses::cpu.inst 36657 # number of demand (read+write) misses 526system.cpu.icache.demand_misses::total 36657 # number of demand (read+write) misses 527system.cpu.icache.overall_misses::cpu.inst 36657 # number of overall misses 528system.cpu.icache.overall_misses::total 36657 # number of overall misses 529system.cpu.icache.ReadReq_miss_latency::cpu.inst 709011999 # number of ReadReq miss cycles 530system.cpu.icache.ReadReq_miss_latency::total 709011999 # number of ReadReq miss cycles 531system.cpu.icache.demand_miss_latency::cpu.inst 709011999 # number of demand (read+write) miss cycles 532system.cpu.icache.demand_miss_latency::total 709011999 # number of demand (read+write) miss cycles 533system.cpu.icache.overall_miss_latency::cpu.inst 709011999 # number of overall miss cycles 534system.cpu.icache.overall_miss_latency::total 709011999 # number of overall miss cycles 535system.cpu.icache.ReadReq_accesses::cpu.inst 11672224 # number of ReadReq accesses(hits+misses) 536system.cpu.icache.ReadReq_accesses::total 11672224 # number of ReadReq accesses(hits+misses) 537system.cpu.icache.demand_accesses::cpu.inst 11672224 # number of demand (read+write) accesses 538system.cpu.icache.demand_accesses::total 11672224 # number of demand (read+write) accesses 539system.cpu.icache.overall_accesses::cpu.inst 11672224 # number of overall (read+write) accesses 540system.cpu.icache.overall_accesses::total 11672224 # number of overall (read+write) accesses 541system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses 542system.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses 543system.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses 544system.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses 545system.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses 546system.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses 547system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19341.790081 # average ReadReq miss latency 548system.cpu.icache.ReadReq_avg_miss_latency::total 19341.790081 # average ReadReq miss latency 549system.cpu.icache.demand_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency 550system.cpu.icache.demand_avg_miss_latency::total 19341.790081 # average overall miss latency 551system.cpu.icache.overall_avg_miss_latency::cpu.inst 19341.790081 # average overall miss latency 552system.cpu.icache.overall_avg_miss_latency::total 19341.790081 # average overall miss latency 553system.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked 554system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 555system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked 556system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 557system.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked 558system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 559system.cpu.icache.fast_writes 0 # number of fast writes performed 560system.cpu.icache.cache_copies 0 # number of cache copies performed 561system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits 562system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits 563system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits 564system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits 565system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits 566system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits 567system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses 568system.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses 569system.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses 570system.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses 571system.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses 572system.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses 573system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580604499 # number of ReadReq MSHR miss cycles 574system.cpu.icache.ReadReq_mshr_miss_latency::total 580604499 # number of ReadReq MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::cpu.inst 580604499 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.demand_mshr_miss_latency::total 580604499 # number of demand (read+write) MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::cpu.inst 580604499 # number of overall MSHR miss cycles 578system.cpu.icache.overall_mshr_miss_latency::total 580604499 # number of overall MSHR miss cycles 579system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses 580system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses 581system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses 582system.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses 583system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses 584system.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.139734 # average ReadReq mshr miss latency 586system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.139734 # average ReadReq mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency 588system.cpu.icache.demand_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.139734 # average overall mshr miss latency 590system.cpu.icache.overall_avg_mshr_miss_latency::total 17656.139734 # average overall mshr miss latency 591system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 592system.cpu.dcache.replacements 158306 # number of replacements 593system.cpu.dcache.tagsinuse 4072.986675 # Cycle average of tags in use 594system.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks. 595system.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks. 596system.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks. 597system.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit. 598system.cpu.dcache.occ_blocks::cpu.data 4072.986675 # Average occupied blocks per requestor 599system.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy 600system.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy 601system.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits 602system.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits 603system.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits 604system.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits 605system.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits 606system.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits 607system.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits 608system.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits 609system.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits 610system.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits 611system.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits 612system.cpu.dcache.overall_hits::total 44303188 # number of overall hits 613system.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses 614system.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses 615system.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses 616system.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses 617system.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses 618system.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses 619system.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses 620system.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses 621system.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses 622system.cpu.dcache.overall_misses::total 1709363 # number of overall misses 623system.cpu.dcache.ReadReq_miss_latency::cpu.data 4670085000 # number of ReadReq miss cycles 624system.cpu.dcache.ReadReq_miss_latency::total 4670085000 # number of ReadReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles 626system.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles 627system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles 628system.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles 629system.cpu.dcache.demand_miss_latency::cpu.data 124709257981 # number of demand (read+write) miss cycles 630system.cpu.dcache.demand_miss_latency::total 124709257981 # number of demand (read+write) miss cycles 631system.cpu.dcache.overall_miss_latency::cpu.data 124709257981 # number of overall miss cycles 632system.cpu.dcache.overall_miss_latency::total 124709257981 # number of overall miss cycles 633system.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) 634system.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) 635system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 636system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 637system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) 638system.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) 639system.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) 640system.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) 641system.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses 642system.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses 643system.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses 644system.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses 645system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses 646system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses 647system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses 648system.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses 649system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses 650system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses 651system.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses 652system.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses 653system.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses 654system.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses 655system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.295264 # average ReadReq miss latency 656system.cpu.dcache.ReadReq_avg_miss_latency::total 37471.295264 # average ReadReq miss latency 657system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency 658system.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency 659system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency 660system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency 661system.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency 662system.cpu.dcache.demand_avg_miss_latency::total 72956.568020 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568020 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::total 72956.568020 # average overall miss latency 665system.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked 666system.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked 667system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked 668system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked 670system.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked 671system.cpu.dcache.fast_writes 0 # number of fast writes performed 672system.cpu.dcache.cache_copies 0 # number of cache copies performed 673system.cpu.dcache.writebacks::writebacks 129052 # number of writebacks 674system.cpu.dcache.writebacks::total 129052 # number of writebacks 675system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits 676system.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits 678system.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits 679system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits 680system.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits 681system.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits 682system.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits 683system.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits 684system.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits 685system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses 686system.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses 687system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses 688system.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses 689system.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses 690system.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses 691system.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses 692system.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses 693system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060277500 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.ReadReq_mshr_miss_latency::total 2060277500 # number of ReadReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313869992 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.demand_mshr_miss_latency::total 10313869992 # number of demand (read+write) MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313869992 # number of overall MSHR miss cycles 700system.cpu.dcache.overall_mshr_miss_latency::total 10313869992 # number of overall MSHR miss cycles 701system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses 702system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses 703system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses 704system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses 705system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses 706system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses 707system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses 708system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses 709system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.782030 # average ReadReq mshr miss latency 710system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.782030 # average ReadReq mshr miss latency 711system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency 712system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency 713system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency 714system.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency 715system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.546316 # average overall mshr miss latency 716system.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.546316 # average overall mshr miss latency 717system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 718system.cpu.l2cache.replacements 95650 # number of replacements 719system.cpu.l2cache.tagsinuse 30136.955692 # Cycle average of tags in use 720system.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks. 721system.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks. 722system.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks. 723system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 724system.cpu.l2cache.occ_blocks::writebacks 26880.895911 # Average occupied blocks per requestor 725system.cpu.l2cache.occ_blocks::cpu.inst 1379.489976 # Average occupied blocks per requestor 726system.cpu.l2cache.occ_blocks::cpu.data 1876.569805 # Average occupied blocks per requestor 727system.cpu.l2cache.occ_percent::writebacks 0.820340 # Average percentage of cache occupancy 728system.cpu.l2cache.occ_percent::cpu.inst 0.042099 # Average percentage of cache occupancy 729system.cpu.l2cache.occ_percent::cpu.data 0.057268 # Average percentage of cache occupancy 730system.cpu.l2cache.occ_percent::total 0.919707 # Average percentage of cache occupancy 731system.cpu.l2cache.ReadReq_hits::cpu.inst 27693 # number of ReadReq hits 732system.cpu.l2cache.ReadReq_hits::cpu.data 33453 # number of ReadReq hits 733system.cpu.l2cache.ReadReq_hits::total 61146 # number of ReadReq hits 734system.cpu.l2cache.Writeback_hits::writebacks 129052 # number of Writeback hits 735system.cpu.l2cache.Writeback_hits::total 129052 # number of Writeback hits 736system.cpu.l2cache.UpgradeReq_hits::cpu.data 19 # number of UpgradeReq hits 737system.cpu.l2cache.UpgradeReq_hits::total 19 # number of UpgradeReq hits 738system.cpu.l2cache.ReadExReq_hits::cpu.data 4778 # number of ReadExReq hits 739system.cpu.l2cache.ReadExReq_hits::total 4778 # number of ReadExReq hits 740system.cpu.l2cache.demand_hits::cpu.inst 27693 # number of demand (read+write) hits 741system.cpu.l2cache.demand_hits::cpu.data 38231 # number of demand (read+write) hits 742system.cpu.l2cache.demand_hits::total 65924 # number of demand (read+write) hits 743system.cpu.l2cache.overall_hits::cpu.inst 27693 # number of overall hits 744system.cpu.l2cache.overall_hits::cpu.data 38231 # number of overall hits 745system.cpu.l2cache.overall_hits::total 65924 # number of overall hits 746system.cpu.l2cache.ReadReq_misses::cpu.inst 4680 # number of ReadReq misses 747system.cpu.l2cache.ReadReq_misses::cpu.data 21915 # number of ReadReq misses 748system.cpu.l2cache.ReadReq_misses::total 26595 # number of ReadReq misses 749system.cpu.l2cache.UpgradeReq_misses::cpu.data 298 # number of UpgradeReq misses 750system.cpu.l2cache.UpgradeReq_misses::total 298 # number of UpgradeReq misses 751system.cpu.l2cache.ReadExReq_misses::cpu.data 102256 # number of ReadExReq misses 752system.cpu.l2cache.ReadExReq_misses::total 102256 # number of ReadExReq misses 753system.cpu.l2cache.demand_misses::cpu.inst 4680 # number of demand (read+write) misses 754system.cpu.l2cache.demand_misses::cpu.data 124171 # number of demand (read+write) misses 755system.cpu.l2cache.demand_misses::total 128851 # number of demand (read+write) misses 756system.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses 757system.cpu.l2cache.overall_misses::cpu.data 124171 # number of overall misses 758system.cpu.l2cache.overall_misses::total 128851 # number of overall misses 759system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269870000 # number of ReadReq miss cycles 760system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664898500 # number of ReadReq miss cycles 761system.cpu.l2cache.ReadReq_miss_latency::total 1934768500 # number of ReadReq miss cycles 762system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles 763system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles 764system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8091962000 # number of ReadExReq miss cycles 765system.cpu.l2cache.ReadExReq_miss_latency::total 8091962000 # number of ReadExReq miss cycles 766system.cpu.l2cache.demand_miss_latency::cpu.inst 269870000 # number of demand (read+write) miss cycles 767system.cpu.l2cache.demand_miss_latency::cpu.data 9756860500 # number of demand (read+write) miss cycles 768system.cpu.l2cache.demand_miss_latency::total 10026730500 # number of demand (read+write) miss cycles 769system.cpu.l2cache.overall_miss_latency::cpu.inst 269870000 # number of overall miss cycles 770system.cpu.l2cache.overall_miss_latency::cpu.data 9756860500 # number of overall miss cycles 771system.cpu.l2cache.overall_miss_latency::total 10026730500 # number of overall miss cycles 772system.cpu.l2cache.ReadReq_accesses::cpu.inst 32373 # number of ReadReq accesses(hits+misses) 773system.cpu.l2cache.ReadReq_accesses::cpu.data 55368 # number of ReadReq accesses(hits+misses) 774system.cpu.l2cache.ReadReq_accesses::total 87741 # number of ReadReq accesses(hits+misses) 775system.cpu.l2cache.Writeback_accesses::writebacks 129052 # number of Writeback accesses(hits+misses) 776system.cpu.l2cache.Writeback_accesses::total 129052 # number of Writeback accesses(hits+misses) 777system.cpu.l2cache.UpgradeReq_accesses::cpu.data 317 # number of UpgradeReq accesses(hits+misses) 778system.cpu.l2cache.UpgradeReq_accesses::total 317 # number of UpgradeReq accesses(hits+misses) 779system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) 780system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) 781system.cpu.l2cache.demand_accesses::cpu.inst 32373 # number of demand (read+write) accesses 782system.cpu.l2cache.demand_accesses::cpu.data 162402 # number of demand (read+write) accesses 783system.cpu.l2cache.demand_accesses::total 194775 # number of demand (read+write) accesses 784system.cpu.l2cache.overall_accesses::cpu.inst 32373 # number of overall (read+write) accesses 785system.cpu.l2cache.overall_accesses::cpu.data 162402 # number of overall (read+write) accesses 786system.cpu.l2cache.overall_accesses::total 194775 # number of overall (read+write) accesses 787system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.144565 # miss rate for ReadReq accesses 788system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395806 # miss rate for ReadReq accesses 789system.cpu.l2cache.ReadReq_miss_rate::total 0.303108 # miss rate for ReadReq accesses 790system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.940063 # miss rate for UpgradeReq accesses 791system.cpu.l2cache.UpgradeReq_miss_rate::total 0.940063 # miss rate for UpgradeReq accesses 792system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955360 # miss rate for ReadExReq accesses 793system.cpu.l2cache.ReadExReq_miss_rate::total 0.955360 # miss rate for ReadExReq accesses 794system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144565 # miss rate for demand accesses 795system.cpu.l2cache.demand_miss_rate::cpu.data 0.764590 # miss rate for demand accesses 796system.cpu.l2cache.demand_miss_rate::total 0.661538 # miss rate for demand accesses 797system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144565 # miss rate for overall accesses 798system.cpu.l2cache.overall_miss_rate::cpu.data 0.764590 # miss rate for overall accesses 799system.cpu.l2cache.overall_miss_rate::total 0.661538 # miss rate for overall accesses 800system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.529915 # average ReadReq miss latency 801system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.727812 # average ReadReq miss latency 802system.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.332581 # average ReadReq miss latency 803system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 77.181208 # average UpgradeReq miss latency 804system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 77.181208 # average UpgradeReq miss latency 805system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79134.349085 # average ReadExReq miss latency 806system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79134.349085 # average ReadExReq miss latency 807system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency 808system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency 809system.cpu.l2cache.demand_avg_miss_latency::total 77816.474067 # average overall miss latency 810system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.529915 # average overall miss latency 811system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.000032 # average overall miss latency 812system.cpu.l2cache.overall_avg_miss_latency::total 77816.474067 # average overall miss latency 813system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 816system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 817system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu.l2cache.fast_writes 0 # number of fast writes performed 820system.cpu.l2cache.cache_copies 0 # number of cache copies performed 821system.cpu.l2cache.writebacks::writebacks 83943 # number of writebacks 822system.cpu.l2cache.writebacks::total 83943 # number of writebacks 823system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits 824system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 825system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 826system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits 827system.cpu.l2cache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits 828system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits 829system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits 830system.cpu.l2cache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits 831system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits 832system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses 833system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses 834system.cpu.l2cache.ReadReq_mshr_misses::total 26521 # number of ReadReq MSHR misses 835system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 298 # number of UpgradeReq MSHR misses 836system.cpu.l2cache.UpgradeReq_mshr_misses::total 298 # number of UpgradeReq MSHR misses 837system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses 838system.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses 839system.cpu.l2cache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses 840system.cpu.l2cache.demand_mshr_misses::cpu.data 124113 # number of demand (read+write) MSHR misses 841system.cpu.l2cache.demand_mshr_misses::total 128777 # number of demand (read+write) MSHR misses 842system.cpu.l2cache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses 843system.cpu.l2cache.overall_mshr_misses::cpu.data 124113 # number of overall MSHR misses 844system.cpu.l2cache.overall_mshr_misses::total 128777 # number of overall MSHR misses 845system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210181444 # number of ReadReq MSHR miss cycles 846system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1389842080 # number of ReadReq MSHR miss cycles 847system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600023524 # number of ReadReq MSHR miss cycles 848system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2980298 # number of UpgradeReq MSHR miss cycles 849system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2980298 # number of UpgradeReq MSHR miss cycles 850system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6821241683 # number of ReadExReq MSHR miss cycles 851system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6821241683 # number of ReadExReq MSHR miss cycles 852system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210181444 # number of demand (read+write) MSHR miss cycles 853system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8211083763 # number of demand (read+write) MSHR miss cycles 854system.cpu.l2cache.demand_mshr_miss_latency::total 8421265207 # number of demand (read+write) MSHR miss cycles 855system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210181444 # number of overall MSHR miss cycles 856system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8211083763 # number of overall MSHR miss cycles 857system.cpu.l2cache.overall_mshr_miss_latency::total 8421265207 # number of overall MSHR miss cycles 858system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for ReadReq accesses 859system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394759 # mshr miss rate for ReadReq accesses 860system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.302265 # mshr miss rate for ReadReq accesses 861system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.940063 # mshr miss rate for UpgradeReq accesses 862system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.940063 # mshr miss rate for UpgradeReq accesses 863system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955360 # mshr miss rate for ReadExReq accesses 864system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955360 # mshr miss rate for ReadExReq accesses 865system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for demand accesses 866system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for demand accesses 867system.cpu.l2cache.demand_mshr_miss_rate::total 0.661158 # mshr miss rate for demand accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for overall accesses 870system.cpu.l2cache.overall_mshr_miss_rate::total 0.661158 # mshr miss rate for overall accesses 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45064.632075 # average ReadReq mshr miss latency 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63587.961751 # average ReadReq mshr miss latency 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.437163 # average ReadReq mshr miss latency 874system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 875system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66707.495726 # average ReadExReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66707.495726 # average ReadExReq mshr miss latency 878system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency 879system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency 880system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency 881system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45064.632075 # average overall mshr miss latency 882system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency 883system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.171374 # average overall mshr miss latency 884system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 885 886---------- End Simulation Statistics ---------- 887