stats.txt revision 9079:9a244ebdc3c9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.023981 # Number of seconds simulated 4sim_ticks 23981004500 # Number of ticks simulated 5final_tick 23981004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 169152 # Simulator instruction rate (inst/s) 8host_op_rate 240031 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57193739 # Simulator tick rate (ticks/s) 10host_mem_usage 242580 # Number of bytes of host memory used 11host_seconds 419.29 # Real time elapsed on the host 12sim_insts 70924419 # Number of instructions simulated 13sim_ops 100643666 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8029184 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8356160 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5417856 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5417856 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125456 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 130565 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 84654 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 84654 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 13634792 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 334814332 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 348449124 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 13634792 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 13634792 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 225922813 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 225922813 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 225922813 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 13634792 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 334814332 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 574371937 # Total bandwidth to/from this memory (bytes/s) 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 45system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 46system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 47system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 48system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 49system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 50system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 51system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52system.cpu.dtb.read_accesses 0 # DTB read accesses 53system.cpu.dtb.write_accesses 0 # DTB write accesses 54system.cpu.dtb.inst_accesses 0 # ITB inst accesses 55system.cpu.dtb.hits 0 # DTB hits 56system.cpu.dtb.misses 0 # DTB misses 57system.cpu.dtb.accesses 0 # DTB accesses 58system.cpu.itb.inst_hits 0 # ITB inst hits 59system.cpu.itb.inst_misses 0 # ITB inst misses 60system.cpu.itb.read_hits 0 # DTB read hits 61system.cpu.itb.read_misses 0 # DTB read misses 62system.cpu.itb.write_hits 0 # DTB write hits 63system.cpu.itb.write_misses 0 # DTB write misses 64system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 65system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 66system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 67system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 69system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 70system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 71system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 1946 # Number of system calls 80system.cpu.numCycles 47962010 # number of cpu cycles simulated 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 83system.cpu.BPredUnit.lookups 16947214 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 12982117 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 655322 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 11804628 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 7961599 # Number of BTB hits 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 89system.cpu.BPredUnit.usedRAS 1880669 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 114490 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 12764738 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 87540471 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 16947214 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 9842268 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 21772804 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 2768546 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 10027678 # Number of cycles fetch has spent blocked 98system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 99system.cpu.fetch.PendingTrapStallCycles 361 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 12061426 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 218802 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 46590944 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.639937 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.350838 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::0 24839551 53.31% 53.31% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 2175787 4.67% 57.98% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 1999394 4.29% 62.28% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 2026993 4.35% 66.63% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 1551688 3.33% 69.96% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 1408138 3.02% 72.98% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 990048 2.12% 75.10% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 1240896 2.66% 77.77% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 10358449 22.23% 100.00% # Number of instructions fetched each cycle (Total) 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 118system.cpu.fetch.rateDist::total 46590944 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.353347 # Number of branch fetches per cycle 120system.cpu.fetch.rate 1.825204 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 14883106 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 8408681 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 19993372 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 1386692 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 1919093 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 3458129 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 108409 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 120163882 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 373498 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 1919093 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 16645469 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 2316120 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 802815 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 19569476 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 5337971 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 117636894 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 44 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 9686 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 4512387 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.FullRegisterEvents 221 # Number of times there has been no free registers 141system.cpu.rename.RenamedOperands 117778889 # Number of destination operands rename has renamed 142system.cpu.rename.RenameLookups 541771281 # Number of register rename lookups that rename has made 143system.cpu.rename.int_rename_lookups 541766916 # Number of integer rename lookups 144system.cpu.rename.fp_rename_lookups 4365 # Number of floating rename lookups 145system.cpu.rename.CommittedMaps 99159536 # Number of HB maps that are committed 146system.cpu.rename.UndoneMaps 18619353 # Number of HB maps that are undone due to squashing 147system.cpu.rename.serializingInsts 37368 # count of serializing insts renamed 148system.cpu.rename.tempSerializingInsts 37363 # count of temporary serializing insts renamed 149system.cpu.rename.skidInsts 12895568 # count of insts added to the skid buffer 150system.cpu.memDep0.insertedLoads 30067923 # Number of loads inserted to the mem dependence unit. 151system.cpu.memDep0.insertedStores 22776958 # Number of stores inserted to the mem dependence unit. 152system.cpu.memDep0.conflictingLoads 3590168 # Number of conflicting loads. 153system.cpu.memDep0.conflictingStores 4248242 # Number of conflicting stores. 154system.cpu.iq.iqInstsAdded 113315749 # Number of instructions added to the IQ (excludes non-spec) 155system.cpu.iq.iqNonSpecInstsAdded 51911 # Number of non-speculative instructions added to the IQ 156system.cpu.iq.iqInstsIssued 108455143 # Number of instructions issued 157system.cpu.iq.iqSquashedInstsIssued 350648 # Number of squashed instructions issued 158system.cpu.iq.iqSquashedInstsExamined 12554662 # Number of squashed instructions iterated over during squash; mainly for profiling 159system.cpu.iq.iqSquashedOperandsExamined 29999283 # Number of squashed operands that are examined and possibly removed from graph 160system.cpu.iq.iqSquashedNonSpecRemoved 14767 # Number of squashed non-spec instructions that were removed 161system.cpu.iq.issued_per_cycle::samples 46590944 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::mean 2.327816 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::stdev 1.997244 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::0 11127507 23.88% 23.88% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::1 8067707 17.32% 41.20% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::2 7375197 15.83% 57.03% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::3 7162683 15.37% 72.40% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::4 5557871 11.93% 84.33% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::5 3930157 8.44% 92.77% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::6 1905355 4.09% 96.86% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::7 881142 1.89% 98.75% # Number of insts issued each cycle 173system.cpu.iq.issued_per_cycle::8 583325 1.25% 100.00% # Number of insts issued each cycle 174system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 176system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 177system.cpu.iq.issued_per_cycle::total 46590944 # Number of insts issued each cycle 178system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 179system.cpu.iq.fu_full::IntAlu 112830 4.40% 4.40% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available 181system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available 187system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available 207system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemRead 1425910 55.61% 60.01% # attempts to use FU when none available 209system.cpu.iq.fu_full::MemWrite 1025351 39.99% 100.00% # attempts to use FU when none available 210system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 212system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 213system.cpu.iq.FU_type_0::IntAlu 57362458 52.89% 52.89% # Type of FU issued 214system.cpu.iq.FU_type_0::IntMult 91498 0.08% 52.97% # Type of FU issued 215system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatAdd 129 0.00% 52.97% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.97% # Type of FU issued 221system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.97% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.97% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.97% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.97% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.97% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.97% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.97% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.97% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.97% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.97% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.97% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.97% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.97% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.97% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.97% # Type of FU issued 236system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.97% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.97% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Type of FU issued 239system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued 241system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued 242system.cpu.iq.FU_type_0::MemRead 29209051 26.93% 79.91% # Type of FU issued 243system.cpu.iq.FU_type_0::MemWrite 21792000 20.09% 100.00% # Type of FU issued 244system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 245system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 246system.cpu.iq.FU_type_0::total 108455143 # Type of FU issued 247system.cpu.iq.rate 2.261272 # Inst issue rate 248system.cpu.iq.fu_busy_cnt 2564091 # FU busy when requested 249system.cpu.iq.fu_busy_rate 0.023642 # FU busy rate (busy events/executed inst) 250system.cpu.iq.int_inst_queue_reads 266415556 # Number of integer instruction queue reads 251system.cpu.iq.int_inst_queue_writes 125949072 # Number of integer instruction queue writes 252system.cpu.iq.int_inst_queue_wakeup_accesses 106420629 # Number of integer instruction queue wakeup accesses 253system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads 254system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes 255system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses 256system.cpu.iq.int_alu_accesses 111019028 # Number of integer alu accesses 257system.cpu.iq.fp_alu_accesses 206 # Number of floating point alu accesses 258system.cpu.iew.lsq.thread0.forwLoads 2223683 # Number of loads that had data forwarded from stores 259system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 260system.cpu.iew.lsq.thread0.squashedLoads 2757457 # Number of loads squashed 261system.cpu.iew.lsq.thread0.ignoredResponses 7931 # Number of memory responses ignored because the instruction is squashed 262system.cpu.iew.lsq.thread0.memOrderViolation 28755 # Number of memory ordering violations 263system.cpu.iew.lsq.thread0.squashedStores 2217862 # Number of stores squashed 264system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 265system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 266system.cpu.iew.lsq.thread0.rescheduledLoads 49 # Number of loads that were rescheduled 267system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked 268system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 269system.cpu.iew.iewSquashCycles 1919093 # Number of cycles IEW is squashing 270system.cpu.iew.iewBlockCycles 944512 # Number of cycles IEW is blocking 271system.cpu.iew.iewUnblockCycles 30820 # Number of cycles IEW is unblocking 272system.cpu.iew.iewDispatchedInsts 113447794 # Number of instructions dispatched to IQ 273system.cpu.iew.iewDispSquashedInsts 342667 # Number of squashed instructions skipped by dispatch 274system.cpu.iew.iewDispLoadInsts 30067923 # Number of dispatched load instructions 275system.cpu.iew.iewDispStoreInsts 22776958 # Number of dispatched store instructions 276system.cpu.iew.iewDispNonSpecInsts 35363 # Number of dispatched non-speculative instructions 277system.cpu.iew.iewIQFullEvents 1047 # Number of times the IQ has become full, causing a stall 278system.cpu.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall 279system.cpu.iew.memOrderViolationEvents 28755 # Number of memory order violations 280system.cpu.iew.predictedTakenIncorrect 424789 # Number of branches that were predicted taken incorrectly 281system.cpu.iew.predictedNotTakenIncorrect 263529 # Number of branches that were predicted not taken incorrectly 282system.cpu.iew.branchMispredicts 688318 # Number of branch mispredicts detected at execute 283system.cpu.iew.iewExecutedInsts 107242187 # Number of executed instructions 284system.cpu.iew.iewExecLoadInsts 28840669 # Number of load instructions executed 285system.cpu.iew.iewExecSquashedInsts 1212956 # Number of squashed instructions skipped in execute 286system.cpu.iew.exec_swp 0 # number of swp insts executed 287system.cpu.iew.exec_nop 80134 # number of nop insts executed 288system.cpu.iew.exec_refs 50312690 # number of memory reference insts executed 289system.cpu.iew.exec_branches 14662886 # Number of branches executed 290system.cpu.iew.exec_stores 21472021 # Number of stores executed 291system.cpu.iew.exec_rate 2.235982 # Inst execution rate 292system.cpu.iew.wb_sent 106754958 # cumulative count of insts sent to commit 293system.cpu.iew.wb_count 106420762 # cumulative count of insts written-back 294system.cpu.iew.wb_producers 53610539 # num instructions producing a value 295system.cpu.iew.wb_consumers 104702454 # num instructions consuming a value 296system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 297system.cpu.iew.wb_rate 2.218855 # insts written-back per cycle 298system.cpu.iew.wb_fanout 0.512028 # average fanout of values written-back 299system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 300system.cpu.commit.commitCommittedInsts 70929971 # The number of committed instructions 301system.cpu.commit.commitCommittedOps 100649218 # The number of committed instructions 302system.cpu.commit.commitSquashedInsts 12799085 # The number of squashed insts skipped by commit 303system.cpu.commit.commitNonSpecStalls 37144 # The number of times commit has been forced to stall to communicate backwards 304system.cpu.commit.branchMispredicts 611847 # The number of times a branch was mispredicted 305system.cpu.commit.committed_per_cycle::samples 44671852 # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::mean 2.253079 # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::stdev 2.750865 # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::0 15424353 34.53% 34.53% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::1 11724908 26.25% 60.77% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::2 3540913 7.93% 68.70% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::3 2916552 6.53% 75.23% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::4 1906207 4.27% 79.50% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::5 1948042 4.36% 83.86% # Number of insts commited each cycle 315system.cpu.commit.committed_per_cycle::6 684228 1.53% 85.39% # Number of insts commited each cycle 316system.cpu.commit.committed_per_cycle::7 590770 1.32% 86.71% # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::8 5935879 13.29% 100.00% # Number of insts commited each cycle 318system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 319system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 320system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 321system.cpu.commit.committed_per_cycle::total 44671852 # Number of insts commited each cycle 322system.cpu.commit.committedInsts 70929971 # Number of instructions committed 323system.cpu.commit.committedOps 100649218 # Number of ops (including micro ops) committed 324system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 325system.cpu.commit.refs 47869562 # Number of memory references committed 326system.cpu.commit.loads 27310466 # Number of loads committed 327system.cpu.commit.membars 15920 # Number of memory barriers committed 328system.cpu.commit.branches 13671985 # Number of branches committed 329system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 330system.cpu.commit.int_insts 91486211 # Number of committed integer instructions. 331system.cpu.commit.function_calls 1679850 # Number of function calls committed. 332system.cpu.commit.bw_lim_events 5935879 # number cycles where commit BW limit reached 333system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 334system.cpu.rob.rob_reads 152158977 # The number of ROB reads 335system.cpu.rob.rob_writes 228826081 # The number of ROB writes 336system.cpu.timesIdled 61655 # Number of times that the entire CPU went into an idle state and unscheduled itself 337system.cpu.idleCycles 1371066 # Total number of cycles that the CPU has spent unscheduled due to idling 338system.cpu.committedInsts 70924419 # Number of Instructions Simulated 339system.cpu.committedOps 100643666 # Number of Ops (including micro ops) Simulated 340system.cpu.committedInsts_total 70924419 # Number of Instructions Simulated 341system.cpu.cpi 0.676241 # CPI: Cycles Per Instruction 342system.cpu.cpi_total 0.676241 # CPI: Total CPI of All Threads 343system.cpu.ipc 1.478762 # IPC: Instructions Per Cycle 344system.cpu.ipc_total 1.478762 # IPC: Total IPC of All Threads 345system.cpu.int_regfile_reads 516206868 # number of integer regfile reads 346system.cpu.int_regfile_writes 104370444 # number of integer regfile writes 347system.cpu.fp_regfile_reads 520 # number of floating regfile reads 348system.cpu.fp_regfile_writes 444 # number of floating regfile writes 349system.cpu.misc_regfile_reads 146052754 # number of misc regfile reads 350system.cpu.misc_regfile_writes 38556 # number of misc regfile writes 351system.cpu.icache.replacements 29824 # number of replacements 352system.cpu.icache.tagsinuse 1820.810833 # Cycle average of tags in use 353system.cpu.icache.total_refs 12028408 # Total number of references to valid blocks. 354system.cpu.icache.sampled_refs 31867 # Sample count of references to valid blocks. 355system.cpu.icache.avg_refs 377.456554 # Average number of references to valid blocks. 356system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 357system.cpu.icache.occ_blocks::cpu.inst 1820.810833 # Average occupied blocks per requestor 358system.cpu.icache.occ_percent::cpu.inst 0.889068 # Average percentage of cache occupancy 359system.cpu.icache.occ_percent::total 0.889068 # Average percentage of cache occupancy 360system.cpu.icache.ReadReq_hits::cpu.inst 12028408 # number of ReadReq hits 361system.cpu.icache.ReadReq_hits::total 12028408 # number of ReadReq hits 362system.cpu.icache.demand_hits::cpu.inst 12028408 # number of demand (read+write) hits 363system.cpu.icache.demand_hits::total 12028408 # number of demand (read+write) hits 364system.cpu.icache.overall_hits::cpu.inst 12028408 # number of overall hits 365system.cpu.icache.overall_hits::total 12028408 # number of overall hits 366system.cpu.icache.ReadReq_misses::cpu.inst 33018 # number of ReadReq misses 367system.cpu.icache.ReadReq_misses::total 33018 # number of ReadReq misses 368system.cpu.icache.demand_misses::cpu.inst 33018 # number of demand (read+write) misses 369system.cpu.icache.demand_misses::total 33018 # number of demand (read+write) misses 370system.cpu.icache.overall_misses::cpu.inst 33018 # number of overall misses 371system.cpu.icache.overall_misses::total 33018 # number of overall misses 372system.cpu.icache.ReadReq_miss_latency::cpu.inst 367424500 # number of ReadReq miss cycles 373system.cpu.icache.ReadReq_miss_latency::total 367424500 # number of ReadReq miss cycles 374system.cpu.icache.demand_miss_latency::cpu.inst 367424500 # number of demand (read+write) miss cycles 375system.cpu.icache.demand_miss_latency::total 367424500 # number of demand (read+write) miss cycles 376system.cpu.icache.overall_miss_latency::cpu.inst 367424500 # number of overall miss cycles 377system.cpu.icache.overall_miss_latency::total 367424500 # number of overall miss cycles 378system.cpu.icache.ReadReq_accesses::cpu.inst 12061426 # number of ReadReq accesses(hits+misses) 379system.cpu.icache.ReadReq_accesses::total 12061426 # number of ReadReq accesses(hits+misses) 380system.cpu.icache.demand_accesses::cpu.inst 12061426 # number of demand (read+write) accesses 381system.cpu.icache.demand_accesses::total 12061426 # number of demand (read+write) accesses 382system.cpu.icache.overall_accesses::cpu.inst 12061426 # number of overall (read+write) accesses 383system.cpu.icache.overall_accesses::total 12061426 # number of overall (read+write) accesses 384system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses 385system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses 386system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses 387system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses 388system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses 389system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses 390system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11128.005936 # average ReadReq miss latency 391system.cpu.icache.ReadReq_avg_miss_latency::total 11128.005936 # average ReadReq miss latency 392system.cpu.icache.demand_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency 393system.cpu.icache.demand_avg_miss_latency::total 11128.005936 # average overall miss latency 394system.cpu.icache.overall_avg_miss_latency::cpu.inst 11128.005936 # average overall miss latency 395system.cpu.icache.overall_avg_miss_latency::total 11128.005936 # average overall miss latency 396system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 400system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 401system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.cpu.icache.fast_writes 0 # number of fast writes performed 403system.cpu.icache.cache_copies 0 # number of cache copies performed 404system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1111 # number of ReadReq MSHR hits 405system.cpu.icache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits 406system.cpu.icache.demand_mshr_hits::cpu.inst 1111 # number of demand (read+write) MSHR hits 407system.cpu.icache.demand_mshr_hits::total 1111 # number of demand (read+write) MSHR hits 408system.cpu.icache.overall_mshr_hits::cpu.inst 1111 # number of overall MSHR hits 409system.cpu.icache.overall_mshr_hits::total 1111 # number of overall MSHR hits 410system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31907 # number of ReadReq MSHR misses 411system.cpu.icache.ReadReq_mshr_misses::total 31907 # number of ReadReq MSHR misses 412system.cpu.icache.demand_mshr_misses::cpu.inst 31907 # number of demand (read+write) MSHR misses 413system.cpu.icache.demand_mshr_misses::total 31907 # number of demand (read+write) MSHR misses 414system.cpu.icache.overall_mshr_misses::cpu.inst 31907 # number of overall MSHR misses 415system.cpu.icache.overall_mshr_misses::total 31907 # number of overall MSHR misses 416system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244055000 # number of ReadReq MSHR miss cycles 417system.cpu.icache.ReadReq_mshr_miss_latency::total 244055000 # number of ReadReq MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244055000 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::total 244055000 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244055000 # number of overall MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::total 244055000 # number of overall MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for ReadReq accesses 423system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002645 # mshr miss rate for ReadReq accesses 424system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for demand accesses 425system.cpu.icache.demand_mshr_miss_rate::total 0.002645 # mshr miss rate for demand accesses 426system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002645 # mshr miss rate for overall accesses 427system.cpu.icache.overall_mshr_miss_rate::total 0.002645 # mshr miss rate for overall accesses 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7648.948507 # average ReadReq mshr miss latency 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7648.948507 # average ReadReq mshr miss latency 430system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency 431system.cpu.icache.demand_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency 432system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7648.948507 # average overall mshr miss latency 433system.cpu.icache.overall_avg_mshr_miss_latency::total 7648.948507 # average overall mshr miss latency 434system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 435system.cpu.dcache.replacements 158597 # number of replacements 436system.cpu.dcache.tagsinuse 4071.944277 # Cycle average of tags in use 437system.cpu.dcache.total_refs 44611539 # Total number of references to valid blocks. 438system.cpu.dcache.sampled_refs 162693 # Sample count of references to valid blocks. 439system.cpu.dcache.avg_refs 274.206874 # Average number of references to valid blocks. 440system.cpu.dcache.warmup_cycle 262057000 # Cycle when the warmup percentage was hit. 441system.cpu.dcache.occ_blocks::cpu.data 4071.944277 # Average occupied blocks per requestor 442system.cpu.dcache.occ_percent::cpu.data 0.994127 # Average percentage of cache occupancy 443system.cpu.dcache.occ_percent::total 0.994127 # Average percentage of cache occupancy 444system.cpu.dcache.ReadReq_hits::cpu.data 26269994 # number of ReadReq hits 445system.cpu.dcache.ReadReq_hits::total 26269994 # number of ReadReq hits 446system.cpu.dcache.WriteReq_hits::cpu.data 18301608 # number of WriteReq hits 447system.cpu.dcache.WriteReq_hits::total 18301608 # number of WriteReq hits 448system.cpu.dcache.LoadLockedReq_hits::cpu.data 20534 # number of LoadLockedReq hits 449system.cpu.dcache.LoadLockedReq_hits::total 20534 # number of LoadLockedReq hits 450system.cpu.dcache.StoreCondReq_hits::cpu.data 19277 # number of StoreCondReq hits 451system.cpu.dcache.StoreCondReq_hits::total 19277 # number of StoreCondReq hits 452system.cpu.dcache.demand_hits::cpu.data 44571602 # number of demand (read+write) hits 453system.cpu.dcache.demand_hits::total 44571602 # number of demand (read+write) hits 454system.cpu.dcache.overall_hits::cpu.data 44571602 # number of overall hits 455system.cpu.dcache.overall_hits::total 44571602 # number of overall hits 456system.cpu.dcache.ReadReq_misses::cpu.data 105369 # number of ReadReq misses 457system.cpu.dcache.ReadReq_misses::total 105369 # number of ReadReq misses 458system.cpu.dcache.WriteReq_misses::cpu.data 1548293 # number of WriteReq misses 459system.cpu.dcache.WriteReq_misses::total 1548293 # number of WriteReq misses 460system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses 461system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses 462system.cpu.dcache.demand_misses::cpu.data 1653662 # number of demand (read+write) misses 463system.cpu.dcache.demand_misses::total 1653662 # number of demand (read+write) misses 464system.cpu.dcache.overall_misses::cpu.data 1653662 # number of overall misses 465system.cpu.dcache.overall_misses::total 1653662 # number of overall misses 466system.cpu.dcache.ReadReq_miss_latency::cpu.data 2114831500 # number of ReadReq miss cycles 467system.cpu.dcache.ReadReq_miss_latency::total 2114831500 # number of ReadReq miss cycles 468system.cpu.dcache.WriteReq_miss_latency::cpu.data 52578719498 # number of WriteReq miss cycles 469system.cpu.dcache.WriteReq_miss_latency::total 52578719498 # number of WriteReq miss cycles 470system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447000 # number of LoadLockedReq miss cycles 471system.cpu.dcache.LoadLockedReq_miss_latency::total 447000 # number of LoadLockedReq miss cycles 472system.cpu.dcache.demand_miss_latency::cpu.data 54693550998 # number of demand (read+write) miss cycles 473system.cpu.dcache.demand_miss_latency::total 54693550998 # number of demand (read+write) miss cycles 474system.cpu.dcache.overall_miss_latency::cpu.data 54693550998 # number of overall miss cycles 475system.cpu.dcache.overall_miss_latency::total 54693550998 # number of overall miss cycles 476system.cpu.dcache.ReadReq_accesses::cpu.data 26375363 # number of ReadReq accesses(hits+misses) 477system.cpu.dcache.ReadReq_accesses::total 26375363 # number of ReadReq accesses(hits+misses) 478system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 479system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 480system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20573 # number of LoadLockedReq accesses(hits+misses) 481system.cpu.dcache.LoadLockedReq_accesses::total 20573 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.StoreCondReq_accesses::cpu.data 19277 # number of StoreCondReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::total 19277 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.demand_accesses::cpu.data 46225264 # number of demand (read+write) accesses 485system.cpu.dcache.demand_accesses::total 46225264 # number of demand (read+write) accesses 486system.cpu.dcache.overall_accesses::cpu.data 46225264 # number of overall (read+write) accesses 487system.cpu.dcache.overall_accesses::total 46225264 # number of overall (read+write) accesses 488system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003995 # miss rate for ReadReq accesses 489system.cpu.dcache.ReadReq_miss_rate::total 0.003995 # miss rate for ReadReq accesses 490system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078000 # miss rate for WriteReq accesses 491system.cpu.dcache.WriteReq_miss_rate::total 0.078000 # miss rate for WriteReq accesses 492system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001896 # miss rate for LoadLockedReq accesses 493system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001896 # miss rate for LoadLockedReq accesses 494system.cpu.dcache.demand_miss_rate::cpu.data 0.035774 # miss rate for demand accesses 495system.cpu.dcache.demand_miss_rate::total 0.035774 # miss rate for demand accesses 496system.cpu.dcache.overall_miss_rate::cpu.data 0.035774 # miss rate for overall accesses 497system.cpu.dcache.overall_miss_rate::total 0.035774 # miss rate for overall accesses 498system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20070.718143 # average ReadReq miss latency 499system.cpu.dcache.ReadReq_avg_miss_latency::total 20070.718143 # average ReadReq miss latency 500system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33959.153402 # average WriteReq miss latency 501system.cpu.dcache.WriteReq_avg_miss_latency::total 33959.153402 # average WriteReq miss latency 502system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11461.538462 # average LoadLockedReq miss latency 503system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11461.538462 # average LoadLockedReq miss latency 504system.cpu.dcache.demand_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency 505system.cpu.dcache.demand_avg_miss_latency::total 33074.201982 # average overall miss latency 506system.cpu.dcache.overall_avg_miss_latency::cpu.data 33074.201982 # average overall miss latency 507system.cpu.dcache.overall_avg_miss_latency::total 33074.201982 # average overall miss latency 508system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 509system.cpu.dcache.blocked_cycles::no_targets 196000 # number of cycles access was blocked 510system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked 512system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_targets 19600 # average number of cycles each access was blocked 514system.cpu.dcache.fast_writes 0 # number of fast writes performed 515system.cpu.dcache.cache_copies 0 # number of cache copies performed 516system.cpu.dcache.writebacks::writebacks 128124 # number of writebacks 517system.cpu.dcache.writebacks::total 128124 # number of writebacks 518system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49671 # number of ReadReq MSHR hits 519system.cpu.dcache.ReadReq_mshr_hits::total 49671 # number of ReadReq MSHR hits 520system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1441258 # number of WriteReq MSHR hits 521system.cpu.dcache.WriteReq_mshr_hits::total 1441258 # number of WriteReq MSHR hits 522system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits 523system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits 524system.cpu.dcache.demand_mshr_hits::cpu.data 1490929 # number of demand (read+write) MSHR hits 525system.cpu.dcache.demand_mshr_hits::total 1490929 # number of demand (read+write) MSHR hits 526system.cpu.dcache.overall_mshr_hits::cpu.data 1490929 # number of overall MSHR hits 527system.cpu.dcache.overall_mshr_hits::total 1490929 # number of overall MSHR hits 528system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55698 # number of ReadReq MSHR misses 529system.cpu.dcache.ReadReq_mshr_misses::total 55698 # number of ReadReq MSHR misses 530system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107035 # number of WriteReq MSHR misses 531system.cpu.dcache.WriteReq_mshr_misses::total 107035 # number of WriteReq MSHR misses 532system.cpu.dcache.demand_mshr_misses::cpu.data 162733 # number of demand (read+write) MSHR misses 533system.cpu.dcache.demand_mshr_misses::total 162733 # number of demand (read+write) MSHR misses 534system.cpu.dcache.overall_mshr_misses::cpu.data 162733 # number of overall MSHR misses 535system.cpu.dcache.overall_mshr_misses::total 162733 # number of overall MSHR misses 536system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 907626500 # number of ReadReq MSHR miss cycles 537system.cpu.dcache.ReadReq_mshr_miss_latency::total 907626500 # number of ReadReq MSHR miss cycles 538system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3661924998 # number of WriteReq MSHR miss cycles 539system.cpu.dcache.WriteReq_mshr_miss_latency::total 3661924998 # number of WriteReq MSHR miss cycles 540system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4569551498 # number of demand (read+write) MSHR miss cycles 541system.cpu.dcache.demand_mshr_miss_latency::total 4569551498 # number of demand (read+write) MSHR miss cycles 542system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4569551498 # number of overall MSHR miss cycles 543system.cpu.dcache.overall_mshr_miss_latency::total 4569551498 # number of overall MSHR miss cycles 544system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses 545system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses 546system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 547system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 548system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for demand accesses 549system.cpu.dcache.demand_mshr_miss_rate::total 0.003520 # mshr miss rate for demand accesses 550system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for overall accesses 551system.cpu.dcache.overall_mshr_miss_rate::total 0.003520 # mshr miss rate for overall accesses 552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16295.495350 # average ReadReq mshr miss latency 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16295.495350 # average ReadReq mshr miss latency 554system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34212.407138 # average WriteReq mshr miss latency 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34212.407138 # average WriteReq mshr miss latency 556system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28080.054433 # average overall mshr miss latency 557system.cpu.dcache.demand_avg_mshr_miss_latency::total 28080.054433 # average overall mshr miss latency 558system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28080.054433 # average overall mshr miss latency 559system.cpu.dcache.overall_avg_mshr_miss_latency::total 28080.054433 # average overall mshr miss latency 560system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 561system.cpu.l2cache.replacements 97993 # number of replacements 562system.cpu.l2cache.tagsinuse 28658.689941 # Cycle average of tags in use 563system.cpu.l2cache.total_refs 86749 # Total number of references to valid blocks. 564system.cpu.l2cache.sampled_refs 128784 # Sample count of references to valid blocks. 565system.cpu.l2cache.avg_refs 0.673601 # Average number of references to valid blocks. 566system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 567system.cpu.l2cache.occ_blocks::writebacks 25863.719355 # Average occupied blocks per requestor 568system.cpu.l2cache.occ_blocks::cpu.inst 1158.363470 # Average occupied blocks per requestor 569system.cpu.l2cache.occ_blocks::cpu.data 1636.607116 # Average occupied blocks per requestor 570system.cpu.l2cache.occ_percent::writebacks 0.789298 # Average percentage of cache occupancy 571system.cpu.l2cache.occ_percent::cpu.inst 0.035350 # Average percentage of cache occupancy 572system.cpu.l2cache.occ_percent::cpu.data 0.049945 # Average percentage of cache occupancy 573system.cpu.l2cache.occ_percent::total 0.874594 # Average percentage of cache occupancy 574system.cpu.l2cache.ReadReq_hits::cpu.inst 26734 # number of ReadReq hits 575system.cpu.l2cache.ReadReq_hits::cpu.data 32452 # number of ReadReq hits 576system.cpu.l2cache.ReadReq_hits::total 59186 # number of ReadReq hits 577system.cpu.l2cache.Writeback_hits::writebacks 128124 # number of Writeback hits 578system.cpu.l2cache.Writeback_hits::total 128124 # number of Writeback hits 579system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits 580system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits 581system.cpu.l2cache.ReadExReq_hits::cpu.data 4717 # number of ReadExReq hits 582system.cpu.l2cache.ReadExReq_hits::total 4717 # number of ReadExReq hits 583system.cpu.l2cache.demand_hits::cpu.inst 26734 # number of demand (read+write) hits 584system.cpu.l2cache.demand_hits::cpu.data 37169 # number of demand (read+write) hits 585system.cpu.l2cache.demand_hits::total 63903 # number of demand (read+write) hits 586system.cpu.l2cache.overall_hits::cpu.inst 26734 # number of overall hits 587system.cpu.l2cache.overall_hits::cpu.data 37169 # number of overall hits 588system.cpu.l2cache.overall_hits::total 63903 # number of overall hits 589system.cpu.l2cache.ReadReq_misses::cpu.inst 5128 # number of ReadReq misses 590system.cpu.l2cache.ReadReq_misses::cpu.data 23210 # number of ReadReq misses 591system.cpu.l2cache.ReadReq_misses::total 28338 # number of ReadReq misses 592system.cpu.l2cache.UpgradeReq_misses::cpu.data 37 # number of UpgradeReq misses 593system.cpu.l2cache.UpgradeReq_misses::total 37 # number of UpgradeReq misses 594system.cpu.l2cache.ReadExReq_misses::cpu.data 102314 # number of ReadExReq misses 595system.cpu.l2cache.ReadExReq_misses::total 102314 # number of ReadExReq misses 596system.cpu.l2cache.demand_misses::cpu.inst 5128 # number of demand (read+write) misses 597system.cpu.l2cache.demand_misses::cpu.data 125524 # number of demand (read+write) misses 598system.cpu.l2cache.demand_misses::total 130652 # number of demand (read+write) misses 599system.cpu.l2cache.overall_misses::cpu.inst 5128 # number of overall misses 600system.cpu.l2cache.overall_misses::cpu.data 125524 # number of overall misses 601system.cpu.l2cache.overall_misses::total 130652 # number of overall misses 602system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175705500 # number of ReadReq miss cycles 603system.cpu.l2cache.ReadReq_miss_latency::cpu.data 794795000 # number of ReadReq miss cycles 604system.cpu.l2cache.ReadReq_miss_latency::total 970500500 # number of ReadReq miss cycles 605system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3514306000 # number of ReadExReq miss cycles 606system.cpu.l2cache.ReadExReq_miss_latency::total 3514306000 # number of ReadExReq miss cycles 607system.cpu.l2cache.demand_miss_latency::cpu.inst 175705500 # number of demand (read+write) miss cycles 608system.cpu.l2cache.demand_miss_latency::cpu.data 4309101000 # number of demand (read+write) miss cycles 609system.cpu.l2cache.demand_miss_latency::total 4484806500 # number of demand (read+write) miss cycles 610system.cpu.l2cache.overall_miss_latency::cpu.inst 175705500 # number of overall miss cycles 611system.cpu.l2cache.overall_miss_latency::cpu.data 4309101000 # number of overall miss cycles 612system.cpu.l2cache.overall_miss_latency::total 4484806500 # number of overall miss cycles 613system.cpu.l2cache.ReadReq_accesses::cpu.inst 31862 # number of ReadReq accesses(hits+misses) 614system.cpu.l2cache.ReadReq_accesses::cpu.data 55662 # number of ReadReq accesses(hits+misses) 615system.cpu.l2cache.ReadReq_accesses::total 87524 # number of ReadReq accesses(hits+misses) 616system.cpu.l2cache.Writeback_accesses::writebacks 128124 # number of Writeback accesses(hits+misses) 617system.cpu.l2cache.Writeback_accesses::total 128124 # number of Writeback accesses(hits+misses) 618system.cpu.l2cache.UpgradeReq_accesses::cpu.data 40 # number of UpgradeReq accesses(hits+misses) 619system.cpu.l2cache.UpgradeReq_accesses::total 40 # number of UpgradeReq accesses(hits+misses) 620system.cpu.l2cache.ReadExReq_accesses::cpu.data 107031 # number of ReadExReq accesses(hits+misses) 621system.cpu.l2cache.ReadExReq_accesses::total 107031 # number of ReadExReq accesses(hits+misses) 622system.cpu.l2cache.demand_accesses::cpu.inst 31862 # number of demand (read+write) accesses 623system.cpu.l2cache.demand_accesses::cpu.data 162693 # number of demand (read+write) accesses 624system.cpu.l2cache.demand_accesses::total 194555 # number of demand (read+write) accesses 625system.cpu.l2cache.overall_accesses::cpu.inst 31862 # number of overall (read+write) accesses 626system.cpu.l2cache.overall_accesses::cpu.data 162693 # number of overall (read+write) accesses 627system.cpu.l2cache.overall_accesses::total 194555 # number of overall (read+write) accesses 628system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.160944 # miss rate for ReadReq accesses 629system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.416981 # miss rate for ReadReq accesses 630system.cpu.l2cache.ReadReq_miss_rate::total 0.323774 # miss rate for ReadReq accesses 631system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.925000 # miss rate for UpgradeReq accesses 632system.cpu.l2cache.UpgradeReq_miss_rate::total 0.925000 # miss rate for UpgradeReq accesses 633system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955929 # miss rate for ReadExReq accesses 634system.cpu.l2cache.ReadExReq_miss_rate::total 0.955929 # miss rate for ReadExReq accesses 635system.cpu.l2cache.demand_miss_rate::cpu.inst 0.160944 # miss rate for demand accesses 636system.cpu.l2cache.demand_miss_rate::cpu.data 0.771539 # miss rate for demand accesses 637system.cpu.l2cache.demand_miss_rate::total 0.671543 # miss rate for demand accesses 638system.cpu.l2cache.overall_miss_rate::cpu.inst 0.160944 # miss rate for overall accesses 639system.cpu.l2cache.overall_miss_rate::cpu.data 0.771539 # miss rate for overall accesses 640system.cpu.l2cache.overall_miss_rate::total 0.671543 # miss rate for overall accesses 641system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34263.943058 # average ReadReq miss latency 642system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34243.644981 # average ReadReq miss latency 643system.cpu.l2cache.ReadReq_avg_miss_latency::total 34247.318089 # average ReadReq miss latency 644system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34348.241687 # average ReadExReq miss latency 645system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34348.241687 # average ReadExReq miss latency 646system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34263.943058 # average overall miss latency 647system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34328.901246 # average overall miss latency 648system.cpu.l2cache.demand_avg_miss_latency::total 34326.351682 # average overall miss latency 649system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34263.943058 # average overall miss latency 650system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34328.901246 # average overall miss latency 651system.cpu.l2cache.overall_avg_miss_latency::total 34326.351682 # average overall miss latency 652system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 653system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 655system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 656system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 657system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.cpu.l2cache.fast_writes 0 # number of fast writes performed 659system.cpu.l2cache.cache_copies 0 # number of cache copies performed 660system.cpu.l2cache.writebacks::writebacks 84654 # number of writebacks 661system.cpu.l2cache.writebacks::total 84654 # number of writebacks 662system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 19 # number of ReadReq MSHR hits 663system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits 664system.cpu.l2cache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits 665system.cpu.l2cache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits 666system.cpu.l2cache.demand_mshr_hits::cpu.data 68 # number of demand (read+write) MSHR hits 667system.cpu.l2cache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits 668system.cpu.l2cache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits 669system.cpu.l2cache.overall_mshr_hits::cpu.data 68 # number of overall MSHR hits 670system.cpu.l2cache.overall_mshr_hits::total 87 # number of overall MSHR hits 671system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5109 # number of ReadReq MSHR misses 672system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23142 # number of ReadReq MSHR misses 673system.cpu.l2cache.ReadReq_mshr_misses::total 28251 # number of ReadReq MSHR misses 674system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37 # number of UpgradeReq MSHR misses 675system.cpu.l2cache.UpgradeReq_mshr_misses::total 37 # number of UpgradeReq MSHR misses 676system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102314 # number of ReadExReq MSHR misses 677system.cpu.l2cache.ReadExReq_mshr_misses::total 102314 # number of ReadExReq MSHR misses 678system.cpu.l2cache.demand_mshr_misses::cpu.inst 5109 # number of demand (read+write) MSHR misses 679system.cpu.l2cache.demand_mshr_misses::cpu.data 125456 # number of demand (read+write) MSHR misses 680system.cpu.l2cache.demand_mshr_misses::total 130565 # number of demand (read+write) MSHR misses 681system.cpu.l2cache.overall_mshr_misses::cpu.inst 5109 # number of overall MSHR misses 682system.cpu.l2cache.overall_mshr_misses::cpu.data 125456 # number of overall MSHR misses 683system.cpu.l2cache.overall_mshr_misses::total 130565 # number of overall MSHR misses 684system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 158798500 # number of ReadReq MSHR miss cycles 685system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 719908500 # number of ReadReq MSHR miss cycles 686system.cpu.l2cache.ReadReq_mshr_miss_latency::total 878707000 # number of ReadReq MSHR miss cycles 687system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1150000 # number of UpgradeReq MSHR miss cycles 688system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1150000 # number of UpgradeReq MSHR miss cycles 689system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3191239500 # number of ReadExReq MSHR miss cycles 690system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3191239500 # number of ReadExReq MSHR miss cycles 691system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158798500 # number of demand (read+write) MSHR miss cycles 692system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3911148000 # number of demand (read+write) MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_latency::total 4069946500 # number of demand (read+write) MSHR miss cycles 694system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158798500 # number of overall MSHR miss cycles 695system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3911148000 # number of overall MSHR miss cycles 696system.cpu.l2cache.overall_mshr_miss_latency::total 4069946500 # number of overall MSHR miss cycles 697system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for ReadReq accesses 698system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415759 # mshr miss rate for ReadReq accesses 699system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.322780 # mshr miss rate for ReadReq accesses 700system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.925000 # mshr miss rate for UpgradeReq accesses 701system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.925000 # mshr miss rate for UpgradeReq accesses 702system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955929 # mshr miss rate for ReadExReq accesses 703system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955929 # mshr miss rate for ReadExReq accesses 704system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for demand accesses 705system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771121 # mshr miss rate for demand accesses 706system.cpu.l2cache.demand_mshr_miss_rate::total 0.671096 # mshr miss rate for demand accesses 707system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.160348 # mshr miss rate for overall accesses 708system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771121 # mshr miss rate for overall accesses 709system.cpu.l2cache.overall_mshr_miss_rate::total 0.671096 # mshr miss rate for overall accesses 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.110002 # average ReadReq mshr miss latency 711system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31108.309567 # average ReadReq mshr miss latency 712system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31103.571555 # average ReadReq mshr miss latency 713system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31081.081081 # average UpgradeReq mshr miss latency 714system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31081.081081 # average UpgradeReq mshr miss latency 715system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31190.643509 # average ReadExReq mshr miss latency 716system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31190.643509 # average ReadExReq mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.110002 # average overall mshr miss latency 718system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31175.455937 # average overall mshr miss latency 719system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31171.803316 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.110002 # average overall mshr miss latency 721system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31175.455937 # average overall mshr miss latency 722system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31171.803316 # average overall mshr miss latency 723system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 724 725---------- End Simulation Statistics ---------- 726