stats.txt revision 8893:e29c604a2582
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.030756 # Number of seconds simulated 4sim_ticks 30755543500 # Number of ticks simulated 5final_tick 30755543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 147147 # Simulator instruction rate (inst/s) 8host_op_rate 208812 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 63815156 # Simulator tick rate (ticks/s) 10host_mem_usage 235936 # Number of bytes of host memory used 11host_seconds 481.95 # Real time elapsed on the host 12sim_insts 70917252 # Number of instructions simulated 13sim_ops 100636500 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 8681216 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 364288 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 5661440 # Number of bytes written to this memory 17system.physmem.num_reads 135644 # Number of read requests responded to by this memory 18system.physmem.num_writes 88460 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 282265082 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 11844629 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 184078685 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 466343767 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.dtb.inst_hits 0 # ITB inst hits 25system.cpu.dtb.inst_misses 0 # ITB inst misses 26system.cpu.dtb.read_hits 0 # DTB read hits 27system.cpu.dtb.read_misses 0 # DTB read misses 28system.cpu.dtb.write_hits 0 # DTB write hits 29system.cpu.dtb.write_misses 0 # DTB write misses 30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 36system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 37system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 38system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39system.cpu.dtb.read_accesses 0 # DTB read accesses 40system.cpu.dtb.write_accesses 0 # DTB write accesses 41system.cpu.dtb.inst_accesses 0 # ITB inst accesses 42system.cpu.dtb.hits 0 # DTB hits 43system.cpu.dtb.misses 0 # DTB misses 44system.cpu.dtb.accesses 0 # DTB accesses 45system.cpu.itb.inst_hits 0 # ITB inst hits 46system.cpu.itb.inst_misses 0 # ITB inst misses 47system.cpu.itb.read_hits 0 # DTB read hits 48system.cpu.itb.read_misses 0 # DTB read misses 49system.cpu.itb.write_hits 0 # DTB write hits 50system.cpu.itb.write_misses 0 # DTB write misses 51system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 52system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 53system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 54system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 55system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 56system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60system.cpu.itb.read_accesses 0 # DTB read accesses 61system.cpu.itb.write_accesses 0 # DTB write accesses 62system.cpu.itb.inst_accesses 0 # ITB inst accesses 63system.cpu.itb.hits 0 # DTB hits 64system.cpu.itb.misses 0 # DTB misses 65system.cpu.itb.accesses 0 # DTB accesses 66system.cpu.workload.num_syscalls 1946 # Number of system calls 67system.cpu.numCycles 61511088 # number of cpu cycles simulated 68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu.BPredUnit.lookups 17165899 # Number of BP lookups 71system.cpu.BPredUnit.condPredicted 13150342 # Number of conditional branches predicted 72system.cpu.BPredUnit.condIncorrect 741670 # Number of conditional branches incorrect 73system.cpu.BPredUnit.BTBLookups 12130394 # Number of BTB lookups 74system.cpu.BPredUnit.BTBHits 8128680 # Number of BTB hits 75system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 76system.cpu.BPredUnit.usedRAS 1854457 # Number of times the RAS was used to get a target. 77system.cpu.BPredUnit.RASInCorrect 183977 # Number of incorrect RAS predictions. 78system.cpu.fetch.icacheStallCycles 13000354 # Number of cycles fetch is stalled on an Icache miss 79system.cpu.fetch.Insts 87655737 # Number of instructions fetch has processed 80system.cpu.fetch.Branches 17165899 # Number of branches that fetch encountered 81system.cpu.fetch.predictedBranches 9983137 # Number of branches that fetch has predicted taken 82system.cpu.fetch.Cycles 21873848 # Number of cycles fetch has run and was not squashing or blocked 83system.cpu.fetch.SquashCycles 2772277 # Number of cycles fetch has spent squashing 84system.cpu.fetch.BlockedCycles 23278441 # Number of cycles fetch has spent blocked 85system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 86system.cpu.fetch.PendingTrapStallCycles 2074 # Number of stall cycles due to pending traps 87system.cpu.fetch.CacheLines 12226708 # Number of cache lines fetched 88system.cpu.fetch.IcacheSquashes 230090 # Number of outstanding Icache misses that were squashed 89system.cpu.fetch.rateDist::samples 60107424 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::mean 2.046912 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::stdev 3.144766 # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::0 38251797 63.64% 63.64% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::1 2252747 3.75% 67.39% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::2 1977441 3.29% 70.68% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::3 2053713 3.42% 74.09% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::4 1587290 2.64% 76.73% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::5 1440263 2.40% 79.13% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::6 985496 1.64% 80.77% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::7 1267048 2.11% 82.88% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::8 10291629 17.12% 100.00% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::total 60107424 # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.branchRate 0.279070 # Number of branch fetches per cycle 107system.cpu.fetch.rate 1.425040 # Number of inst fetches per cycle 108system.cpu.decode.IdleCycles 14856562 # Number of cycles decode is idle 109system.cpu.decode.BlockedCycles 22001240 # Number of cycles decode is blocked 110system.cpu.decode.RunCycles 20371729 # Number of cycles decode is running 111system.cpu.decode.UnblockCycles 1031804 # Number of cycles decode is unblocking 112system.cpu.decode.SquashCycles 1846089 # Number of cycles decode is squashing 113system.cpu.decode.BranchResolved 3466450 # Number of times decode resolved a branch 114system.cpu.decode.BranchMispred 109251 # Number of times decode detected a branch misprediction 115system.cpu.decode.DecodedInsts 119897530 # Number of instructions handled by decode 116system.cpu.decode.SquashedInsts 366577 # Number of squashed instructions handled by decode 117system.cpu.rename.SquashCycles 1846089 # Number of cycles rename is squashing 118system.cpu.rename.IdleCycles 16668221 # Number of cycles rename is idle 119system.cpu.rename.BlockCycles 1965297 # Number of cycles rename is blocking 120system.cpu.rename.serializeStallCycles 15638738 # count of cycles rename stalled for serializing inst 121system.cpu.rename.RunCycles 19567499 # Number of cycles rename is running 122system.cpu.rename.UnblockCycles 4421580 # Number of cycles rename is unblocking 123system.cpu.rename.RenamedInsts 116607925 # Number of instructions processed by rename 124system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full 125system.cpu.rename.IQFullEvents 4528 # Number of times rename has blocked due to IQ full 126system.cpu.rename.LSQFullEvents 3022237 # Number of times rename has blocked due to LSQ full 127system.cpu.rename.FullRegisterEvents 40 # Number of times there has been no free registers 128system.cpu.rename.RenamedOperands 116831766 # Number of destination operands rename has renamed 129system.cpu.rename.RenameLookups 536941360 # Number of register rename lookups that rename has made 130system.cpu.rename.int_rename_lookups 536932869 # Number of integer rename lookups 131system.cpu.rename.fp_rename_lookups 8491 # Number of floating rename lookups 132system.cpu.rename.CommittedMaps 99148069 # Number of HB maps that are committed 133system.cpu.rename.UndoneMaps 17683697 # Number of HB maps that are undone due to squashing 134system.cpu.rename.serializingInsts 794887 # count of serializing insts renamed 135system.cpu.rename.tempSerializingInsts 794929 # count of temporary serializing insts renamed 136system.cpu.rename.skidInsts 12663863 # count of insts added to the skid buffer 137system.cpu.memDep0.insertedLoads 29905745 # Number of loads inserted to the mem dependence unit. 138system.cpu.memDep0.insertedStores 22497839 # Number of stores inserted to the mem dependence unit. 139system.cpu.memDep0.conflictingLoads 2550433 # Number of conflicting loads. 140system.cpu.memDep0.conflictingStores 3605599 # Number of conflicting stores. 141system.cpu.iq.iqInstsAdded 111646205 # Number of instructions added to the IQ (excludes non-spec) 142system.cpu.iq.iqNonSpecInstsAdded 783462 # Number of non-speculative instructions added to the IQ 143system.cpu.iq.iqInstsIssued 107783359 # Number of instructions issued 144system.cpu.iq.iqSquashedInstsIssued 315194 # Number of squashed instructions issued 145system.cpu.iq.iqSquashedInstsExamined 11596172 # Number of squashed instructions iterated over during squash; mainly for profiling 146system.cpu.iq.iqSquashedOperandsExamined 28526322 # Number of squashed operands that are examined and possibly removed from graph 147system.cpu.iq.iqSquashedNonSpecRemoved 79963 # Number of squashed non-spec instructions that were removed 148system.cpu.iq.issued_per_cycle::samples 60107424 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::mean 1.793179 # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::stdev 1.923398 # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::0 21602316 35.94% 35.94% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::1 11403464 18.97% 54.91% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::2 8200759 13.64% 68.55% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::3 7319332 12.18% 80.73% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::4 4922118 8.19% 88.92% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::5 3558954 5.92% 94.84% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::6 1700735 2.83% 97.67% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::7 865239 1.44% 99.11% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::8 534507 0.89% 100.00% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::total 60107424 # Number of insts issued each cycle 165system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 166system.cpu.iq.fu_full::IntAlu 107169 4.01% 4.01% # attempts to use FU when none available 167system.cpu.iq.fu_full::IntMult 0 0.00% 4.01% # attempts to use FU when none available 168system.cpu.iq.fu_full::IntDiv 0 0.00% 4.01% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.01% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.01% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.01% # attempts to use FU when none available 172system.cpu.iq.fu_full::FloatMult 0 0.00% 4.01% # attempts to use FU when none available 173system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.01% # attempts to use FU when none available 174system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.01% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.01% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.01% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.01% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.01% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.01% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.01% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdMult 0 0.00% 4.01% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.01% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdShift 0 0.00% 4.01% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.01% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.01% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.01% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.01% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.01% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.01% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.01% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.01% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.01% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.01% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.01% # attempts to use FU when none available 195system.cpu.iq.fu_full::MemRead 1504678 56.36% 60.37% # attempts to use FU when none available 196system.cpu.iq.fu_full::MemWrite 1057992 39.63% 100.00% # attempts to use FU when none available 197system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 198system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 199system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 200system.cpu.iq.FU_type_0::IntAlu 56937666 52.83% 52.83% # Type of FU issued 201system.cpu.iq.FU_type_0::IntMult 88934 0.08% 52.91% # Type of FU issued 202system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.91% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatAdd 306 0.00% 52.91% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.91% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.91% # Type of FU issued 206system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.91% # Type of FU issued 207system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.91% # Type of FU issued 208system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.91% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.91% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.91% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.91% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.91% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.91% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.91% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.91% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.91% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.91% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.91% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.91% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.91% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.91% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.91% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.91% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.91% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.91% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.91% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.91% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.91% # Type of FU issued 229system.cpu.iq.FU_type_0::MemRead 29100662 27.00% 79.91% # Type of FU issued 230system.cpu.iq.FU_type_0::MemWrite 21655782 20.09% 100.00% # Type of FU issued 231system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 232system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 233system.cpu.iq.FU_type_0::total 107783359 # Type of FU issued 234system.cpu.iq.rate 1.752259 # Inst issue rate 235system.cpu.iq.fu_busy_cnt 2669841 # FU busy when requested 236system.cpu.iq.fu_busy_rate 0.024770 # FU busy rate (busy events/executed inst) 237system.cpu.iq.int_inst_queue_reads 278658374 # Number of integer instruction queue reads 238system.cpu.iq.int_inst_queue_writes 124040880 # Number of integer instruction queue writes 239system.cpu.iq.int_inst_queue_wakeup_accesses 105647232 # Number of integer instruction queue wakeup accesses 240system.cpu.iq.fp_inst_queue_reads 803 # Number of floating instruction queue reads 241system.cpu.iq.fp_inst_queue_writes 1299 # Number of floating instruction queue writes 242system.cpu.iq.fp_inst_queue_wakeup_accesses 239 # Number of floating instruction queue wakeup accesses 243system.cpu.iq.int_alu_accesses 110452800 # Number of integer alu accesses 244system.cpu.iq.fp_alu_accesses 400 # Number of floating point alu accesses 245system.cpu.iew.lsq.thread0.forwLoads 1897681 # Number of loads that had data forwarded from stores 246system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 247system.cpu.iew.lsq.thread0.squashedLoads 2596713 # Number of loads squashed 248system.cpu.iew.lsq.thread0.ignoredResponses 5092 # Number of memory responses ignored because the instruction is squashed 249system.cpu.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations 250system.cpu.iew.lsq.thread0.squashedStores 1940178 # Number of stores squashed 251system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 252system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 253system.cpu.iew.lsq.thread0.rescheduledLoads 48 # Number of loads that were rescheduled 254system.cpu.iew.lsq.thread0.cacheBlocked 61 # Number of times an access to memory failed due to the cache being blocked 255system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 256system.cpu.iew.iewSquashCycles 1846089 # Number of cycles IEW is squashing 257system.cpu.iew.iewBlockCycles 949061 # Number of cycles IEW is blocking 258system.cpu.iew.iewUnblockCycles 28680 # Number of cycles IEW is unblocking 259system.cpu.iew.iewDispatchedInsts 112509386 # Number of instructions dispatched to IQ 260system.cpu.iew.iewDispSquashedInsts 471926 # Number of squashed instructions skipped by dispatch 261system.cpu.iew.iewDispLoadInsts 29905745 # Number of dispatched load instructions 262system.cpu.iew.iewDispStoreInsts 22497839 # Number of dispatched store instructions 263system.cpu.iew.iewDispNonSpecInsts 767420 # Number of dispatched non-speculative instructions 264system.cpu.iew.iewIQFullEvents 1122 # Number of times the IQ has become full, causing a stall 265system.cpu.iew.iewLSQFullEvents 1174 # Number of times the LSQ has become full, causing a stall 266system.cpu.iew.memOrderViolationEvents 17660 # Number of memory order violations 267system.cpu.iew.predictedTakenIncorrect 518600 # Number of branches that were predicted taken incorrectly 268system.cpu.iew.predictedNotTakenIncorrect 257124 # Number of branches that were predicted not taken incorrectly 269system.cpu.iew.branchMispredicts 775724 # Number of branch mispredicts detected at execute 270system.cpu.iew.iewExecutedInsts 106553535 # Number of executed instructions 271system.cpu.iew.iewExecLoadInsts 28745908 # Number of load instructions executed 272system.cpu.iew.iewExecSquashedInsts 1229824 # Number of squashed instructions skipped in execute 273system.cpu.iew.exec_swp 0 # number of swp insts executed 274system.cpu.iew.exec_nop 79719 # number of nop insts executed 275system.cpu.iew.exec_refs 50100729 # number of memory reference insts executed 276system.cpu.iew.exec_branches 14610772 # Number of branches executed 277system.cpu.iew.exec_stores 21354821 # Number of stores executed 278system.cpu.iew.exec_rate 1.732265 # Inst execution rate 279system.cpu.iew.wb_sent 105985847 # cumulative count of insts sent to commit 280system.cpu.iew.wb_count 105647471 # cumulative count of insts written-back 281system.cpu.iew.wb_producers 52628676 # num instructions producing a value 282system.cpu.iew.wb_consumers 101773898 # num instructions consuming a value 283system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 284system.cpu.iew.wb_rate 1.717535 # insts written-back per cycle 285system.cpu.iew.wb_fanout 0.517114 # average fanout of values written-back 286system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 287system.cpu.commit.commitCommittedInsts 70922804 # The number of committed instructions 288system.cpu.commit.commitCommittedOps 100642052 # The number of committed instructions 289system.cpu.commit.commitSquashedInsts 11867683 # The number of squashed insts skipped by commit 290system.cpu.commit.commitNonSpecStalls 703499 # The number of times commit has been forced to stall to communicate backwards 291system.cpu.commit.branchMispredicts 697454 # The number of times a branch was mispredicted 292system.cpu.commit.committed_per_cycle::samples 58261336 # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::mean 1.727424 # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::stdev 2.444675 # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::0 25494739 43.76% 43.76% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::1 14514509 24.91% 68.67% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::2 4165612 7.15% 75.82% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::3 3613399 6.20% 82.02% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::4 2299623 3.95% 85.97% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::5 1924742 3.30% 89.27% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::6 677832 1.16% 90.44% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::7 500112 0.86% 91.30% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::8 5070768 8.70% 100.00% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::total 58261336 # Number of insts commited each cycle 309system.cpu.commit.committedInsts 70922804 # Number of instructions committed 310system.cpu.commit.committedOps 100642052 # Number of ops (including micro ops) committed 311system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 312system.cpu.commit.refs 47866693 # Number of memory references committed 313system.cpu.commit.loads 27309032 # Number of loads committed 314system.cpu.commit.membars 15920 # Number of memory barriers committed 315system.cpu.commit.branches 13670551 # Number of branches committed 316system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 317system.cpu.commit.int_insts 91480479 # Number of committed integer instructions. 318system.cpu.commit.function_calls 1679850 # Number of function calls committed. 319system.cpu.commit.bw_lim_events 5070768 # number cycles where commit BW limit reached 320system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 321system.cpu.rob.rob_reads 165675004 # The number of ROB reads 322system.cpu.rob.rob_writes 226873042 # The number of ROB writes 323system.cpu.timesIdled 61564 # Number of times that the entire CPU went into an idle state and unscheduled itself 324system.cpu.idleCycles 1403664 # Total number of cycles that the CPU has spent unscheduled due to idling 325system.cpu.committedInsts 70917252 # Number of Instructions Simulated 326system.cpu.committedOps 100636500 # Number of Ops (including micro ops) Simulated 327system.cpu.committedInsts_total 70917252 # Number of Instructions Simulated 328system.cpu.cpi 0.867364 # CPI: Cycles Per Instruction 329system.cpu.cpi_total 0.867364 # CPI: Total CPI of All Threads 330system.cpu.ipc 1.152918 # IPC: Instructions Per Cycle 331system.cpu.ipc_total 1.152918 # IPC: Total IPC of All Threads 332system.cpu.int_regfile_reads 512909735 # number of integer regfile reads 333system.cpu.int_regfile_writes 103521788 # number of integer regfile writes 334system.cpu.fp_regfile_reads 1198 # number of floating regfile reads 335system.cpu.fp_regfile_writes 998 # number of floating regfile writes 336system.cpu.misc_regfile_reads 145684870 # number of misc regfile reads 337system.cpu.misc_regfile_writes 35686 # number of misc regfile writes 338system.cpu.icache.replacements 28916 # number of replacements 339system.cpu.icache.tagsinuse 1823.894979 # Cycle average of tags in use 340system.cpu.icache.total_refs 12194402 # Total number of references to valid blocks. 341system.cpu.icache.sampled_refs 30952 # Sample count of references to valid blocks. 342system.cpu.icache.avg_refs 393.977837 # Average number of references to valid blocks. 343system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 344system.cpu.icache.occ_blocks::cpu.inst 1823.894979 # Average occupied blocks per requestor 345system.cpu.icache.occ_percent::cpu.inst 0.890574 # Average percentage of cache occupancy 346system.cpu.icache.occ_percent::total 0.890574 # Average percentage of cache occupancy 347system.cpu.icache.ReadReq_hits::cpu.inst 12194406 # number of ReadReq hits 348system.cpu.icache.ReadReq_hits::total 12194406 # number of ReadReq hits 349system.cpu.icache.demand_hits::cpu.inst 12194406 # number of demand (read+write) hits 350system.cpu.icache.demand_hits::total 12194406 # number of demand (read+write) hits 351system.cpu.icache.overall_hits::cpu.inst 12194406 # number of overall hits 352system.cpu.icache.overall_hits::total 12194406 # number of overall hits 353system.cpu.icache.ReadReq_misses::cpu.inst 32302 # number of ReadReq misses 354system.cpu.icache.ReadReq_misses::total 32302 # number of ReadReq misses 355system.cpu.icache.demand_misses::cpu.inst 32302 # number of demand (read+write) misses 356system.cpu.icache.demand_misses::total 32302 # number of demand (read+write) misses 357system.cpu.icache.overall_misses::cpu.inst 32302 # number of overall misses 358system.cpu.icache.overall_misses::total 32302 # number of overall misses 359system.cpu.icache.ReadReq_miss_latency::cpu.inst 385546000 # number of ReadReq miss cycles 360system.cpu.icache.ReadReq_miss_latency::total 385546000 # number of ReadReq miss cycles 361system.cpu.icache.demand_miss_latency::cpu.inst 385546000 # number of demand (read+write) miss cycles 362system.cpu.icache.demand_miss_latency::total 385546000 # number of demand (read+write) miss cycles 363system.cpu.icache.overall_miss_latency::cpu.inst 385546000 # number of overall miss cycles 364system.cpu.icache.overall_miss_latency::total 385546000 # number of overall miss cycles 365system.cpu.icache.ReadReq_accesses::cpu.inst 12226708 # number of ReadReq accesses(hits+misses) 366system.cpu.icache.ReadReq_accesses::total 12226708 # number of ReadReq accesses(hits+misses) 367system.cpu.icache.demand_accesses::cpu.inst 12226708 # number of demand (read+write) accesses 368system.cpu.icache.demand_accesses::total 12226708 # number of demand (read+write) accesses 369system.cpu.icache.overall_accesses::cpu.inst 12226708 # number of overall (read+write) accesses 370system.cpu.icache.overall_accesses::total 12226708 # number of overall (read+write) accesses 371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002642 # miss rate for ReadReq accesses 372system.cpu.icache.demand_miss_rate::cpu.inst 0.002642 # miss rate for demand accesses 373system.cpu.icache.overall_miss_rate::cpu.inst 0.002642 # miss rate for overall accesses 374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11935.669618 # average ReadReq miss latency 375system.cpu.icache.demand_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency 376system.cpu.icache.overall_avg_miss_latency::cpu.inst 11935.669618 # average overall miss latency 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 381system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 382system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 383system.cpu.icache.fast_writes 0 # number of fast writes performed 384system.cpu.icache.cache_copies 0 # number of cache copies performed 385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1300 # number of ReadReq MSHR hits 386system.cpu.icache.ReadReq_mshr_hits::total 1300 # number of ReadReq MSHR hits 387system.cpu.icache.demand_mshr_hits::cpu.inst 1300 # number of demand (read+write) MSHR hits 388system.cpu.icache.demand_mshr_hits::total 1300 # number of demand (read+write) MSHR hits 389system.cpu.icache.overall_mshr_hits::cpu.inst 1300 # number of overall MSHR hits 390system.cpu.icache.overall_mshr_hits::total 1300 # number of overall MSHR hits 391system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31002 # number of ReadReq MSHR misses 392system.cpu.icache.ReadReq_mshr_misses::total 31002 # number of ReadReq MSHR misses 393system.cpu.icache.demand_mshr_misses::cpu.inst 31002 # number of demand (read+write) MSHR misses 394system.cpu.icache.demand_mshr_misses::total 31002 # number of demand (read+write) MSHR misses 395system.cpu.icache.overall_mshr_misses::cpu.inst 31002 # number of overall MSHR misses 396system.cpu.icache.overall_mshr_misses::total 31002 # number of overall MSHR misses 397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 260426000 # number of ReadReq MSHR miss cycles 398system.cpu.icache.ReadReq_mshr_miss_latency::total 260426000 # number of ReadReq MSHR miss cycles 399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 260426000 # number of demand (read+write) MSHR miss cycles 400system.cpu.icache.demand_mshr_miss_latency::total 260426000 # number of demand (read+write) MSHR miss cycles 401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 260426000 # number of overall MSHR miss cycles 402system.cpu.icache.overall_mshr_miss_latency::total 260426000 # number of overall MSHR miss cycles 403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for ReadReq accesses 404system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for demand accesses 405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002536 # mshr miss rate for overall accesses 406system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8400.296755 # average ReadReq mshr miss latency 407system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8400.296755 # average overall mshr miss latency 408system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8400.296755 # average overall mshr miss latency 409system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 410system.cpu.dcache.replacements 158739 # number of replacements 411system.cpu.dcache.tagsinuse 4072.206882 # Cycle average of tags in use 412system.cpu.dcache.total_refs 44824724 # Total number of references to valid blocks. 413system.cpu.dcache.sampled_refs 162835 # Sample count of references to valid blocks. 414system.cpu.dcache.avg_refs 275.276961 # Average number of references to valid blocks. 415system.cpu.dcache.warmup_cycle 306509000 # Cycle when the warmup percentage was hit. 416system.cpu.dcache.occ_blocks::cpu.data 4072.206882 # Average occupied blocks per requestor 417system.cpu.dcache.occ_percent::cpu.data 0.994191 # Average percentage of cache occupancy 418system.cpu.dcache.occ_percent::total 0.994191 # Average percentage of cache occupancy 419system.cpu.dcache.ReadReq_hits::cpu.data 26477714 # number of ReadReq hits 420system.cpu.dcache.ReadReq_hits::total 26477714 # number of ReadReq hits 421system.cpu.dcache.WriteReq_hits::cpu.data 18310173 # number of WriteReq hits 422system.cpu.dcache.WriteReq_hits::total 18310173 # number of WriteReq hits 423system.cpu.dcache.LoadLockedReq_hits::cpu.data 18862 # number of LoadLockedReq hits 424system.cpu.dcache.LoadLockedReq_hits::total 18862 # number of LoadLockedReq hits 425system.cpu.dcache.StoreCondReq_hits::cpu.data 17842 # number of StoreCondReq hits 426system.cpu.dcache.StoreCondReq_hits::total 17842 # number of StoreCondReq hits 427system.cpu.dcache.demand_hits::cpu.data 44787887 # number of demand (read+write) hits 428system.cpu.dcache.demand_hits::total 44787887 # number of demand (read+write) hits 429system.cpu.dcache.overall_hits::cpu.data 44787887 # number of overall hits 430system.cpu.dcache.overall_hits::total 44787887 # number of overall hits 431system.cpu.dcache.ReadReq_misses::cpu.data 109145 # number of ReadReq misses 432system.cpu.dcache.ReadReq_misses::total 109145 # number of ReadReq misses 433system.cpu.dcache.WriteReq_misses::cpu.data 1539728 # number of WriteReq misses 434system.cpu.dcache.WriteReq_misses::total 1539728 # number of WriteReq misses 435system.cpu.dcache.LoadLockedReq_misses::cpu.data 32 # number of LoadLockedReq misses 436system.cpu.dcache.LoadLockedReq_misses::total 32 # number of LoadLockedReq misses 437system.cpu.dcache.demand_misses::cpu.data 1648873 # number of demand (read+write) misses 438system.cpu.dcache.demand_misses::total 1648873 # number of demand (read+write) misses 439system.cpu.dcache.overall_misses::cpu.data 1648873 # number of overall misses 440system.cpu.dcache.overall_misses::total 1648873 # number of overall misses 441system.cpu.dcache.ReadReq_miss_latency::cpu.data 2419748500 # number of ReadReq miss cycles 442system.cpu.dcache.ReadReq_miss_latency::total 2419748500 # number of ReadReq miss cycles 443system.cpu.dcache.WriteReq_miss_latency::cpu.data 52564184000 # number of WriteReq miss cycles 444system.cpu.dcache.WriteReq_miss_latency::total 52564184000 # number of WriteReq miss cycles 445system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 414000 # number of LoadLockedReq miss cycles 446system.cpu.dcache.LoadLockedReq_miss_latency::total 414000 # number of LoadLockedReq miss cycles 447system.cpu.dcache.demand_miss_latency::cpu.data 54983932500 # number of demand (read+write) miss cycles 448system.cpu.dcache.demand_miss_latency::total 54983932500 # number of demand (read+write) miss cycles 449system.cpu.dcache.overall_miss_latency::cpu.data 54983932500 # number of overall miss cycles 450system.cpu.dcache.overall_miss_latency::total 54983932500 # number of overall miss cycles 451system.cpu.dcache.ReadReq_accesses::cpu.data 26586859 # number of ReadReq accesses(hits+misses) 452system.cpu.dcache.ReadReq_accesses::total 26586859 # number of ReadReq accesses(hits+misses) 453system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 454system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 455system.cpu.dcache.LoadLockedReq_accesses::cpu.data 18894 # number of LoadLockedReq accesses(hits+misses) 456system.cpu.dcache.LoadLockedReq_accesses::total 18894 # number of LoadLockedReq accesses(hits+misses) 457system.cpu.dcache.StoreCondReq_accesses::cpu.data 17842 # number of StoreCondReq accesses(hits+misses) 458system.cpu.dcache.StoreCondReq_accesses::total 17842 # number of StoreCondReq accesses(hits+misses) 459system.cpu.dcache.demand_accesses::cpu.data 46436760 # number of demand (read+write) accesses 460system.cpu.dcache.demand_accesses::total 46436760 # number of demand (read+write) accesses 461system.cpu.dcache.overall_accesses::cpu.data 46436760 # number of overall (read+write) accesses 462system.cpu.dcache.overall_accesses::total 46436760 # number of overall (read+write) accesses 463system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004105 # miss rate for ReadReq accesses 464system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.077569 # miss rate for WriteReq accesses 465system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001694 # miss rate for LoadLockedReq accesses 466system.cpu.dcache.demand_miss_rate::cpu.data 0.035508 # miss rate for demand accesses 467system.cpu.dcache.overall_miss_rate::cpu.data 0.035508 # miss rate for overall accesses 468system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22170.035274 # average ReadReq miss latency 469system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34138.616691 # average WriteReq miss latency 470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12937.500000 # average LoadLockedReq miss latency 471system.cpu.dcache.demand_avg_miss_latency::cpu.data 33346.372037 # average overall miss latency 472system.cpu.dcache.overall_avg_miss_latency::cpu.data 33346.372037 # average overall miss latency 473system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 199000 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets 19900 # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed 481system.cpu.dcache.writebacks::writebacks 123771 # number of writebacks 482system.cpu.dcache.writebacks::total 123771 # number of writebacks 483system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53183 # number of ReadReq MSHR hits 484system.cpu.dcache.ReadReq_mshr_hits::total 53183 # number of ReadReq MSHR hits 485system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1432805 # number of WriteReq MSHR hits 486system.cpu.dcache.WriteReq_mshr_hits::total 1432805 # number of WriteReq MSHR hits 487system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 32 # number of LoadLockedReq MSHR hits 488system.cpu.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits 489system.cpu.dcache.demand_mshr_hits::cpu.data 1485988 # number of demand (read+write) MSHR hits 490system.cpu.dcache.demand_mshr_hits::total 1485988 # number of demand (read+write) MSHR hits 491system.cpu.dcache.overall_mshr_hits::cpu.data 1485988 # number of overall MSHR hits 492system.cpu.dcache.overall_mshr_hits::total 1485988 # number of overall MSHR hits 493system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55962 # number of ReadReq MSHR misses 494system.cpu.dcache.ReadReq_mshr_misses::total 55962 # number of ReadReq MSHR misses 495system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106923 # number of WriteReq MSHR misses 496system.cpu.dcache.WriteReq_mshr_misses::total 106923 # number of WriteReq MSHR misses 497system.cpu.dcache.demand_mshr_misses::cpu.data 162885 # number of demand (read+write) MSHR misses 498system.cpu.dcache.demand_mshr_misses::total 162885 # number of demand (read+write) MSHR misses 499system.cpu.dcache.overall_mshr_misses::cpu.data 162885 # number of overall MSHR misses 500system.cpu.dcache.overall_mshr_misses::total 162885 # number of overall MSHR misses 501system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1045315000 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 1045315000 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3667070000 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 3667070000 # number of WriteReq MSHR miss cycles 505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4712385000 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::total 4712385000 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4712385000 # number of overall MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::total 4712385000 # number of overall MSHR miss cycles 509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses 510system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005387 # mshr miss rate for WriteReq accesses 511system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003508 # mshr miss rate for demand accesses 512system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003508 # mshr miss rate for overall accesses 513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18679.014331 # average ReadReq mshr miss latency 514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.362803 # average WriteReq mshr miss latency 515system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28930.748688 # average overall mshr miss latency 516system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28930.748688 # average overall mshr miss latency 517system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 518system.cpu.l2cache.replacements 115379 # number of replacements 519system.cpu.l2cache.tagsinuse 18377.888131 # Cycle average of tags in use 520system.cpu.l2cache.total_refs 75936 # Total number of references to valid blocks. 521system.cpu.l2cache.sampled_refs 134247 # Sample count of references to valid blocks. 522system.cpu.l2cache.avg_refs 0.565644 # Average number of references to valid blocks. 523system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 524system.cpu.l2cache.occ_blocks::writebacks 15924.740551 # Average occupied blocks per requestor 525system.cpu.l2cache.occ_blocks::cpu.inst 876.929097 # Average occupied blocks per requestor 526system.cpu.l2cache.occ_blocks::cpu.data 1576.218483 # Average occupied blocks per requestor 527system.cpu.l2cache.occ_percent::writebacks 0.485985 # Average percentage of cache occupancy 528system.cpu.l2cache.occ_percent::cpu.inst 0.026762 # Average percentage of cache occupancy 529system.cpu.l2cache.occ_percent::cpu.data 0.048102 # Average percentage of cache occupancy 530system.cpu.l2cache.occ_percent::total 0.560849 # Average percentage of cache occupancy 531system.cpu.l2cache.ReadReq_hits::cpu.inst 25235 # number of ReadReq hits 532system.cpu.l2cache.ReadReq_hits::cpu.data 28501 # number of ReadReq hits 533system.cpu.l2cache.ReadReq_hits::total 53736 # number of ReadReq hits 534system.cpu.l2cache.Writeback_hits::writebacks 123771 # number of Writeback hits 535system.cpu.l2cache.Writeback_hits::total 123771 # number of Writeback hits 536system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits 537system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits 538system.cpu.l2cache.ReadExReq_hits::cpu.data 4314 # number of ReadExReq hits 539system.cpu.l2cache.ReadExReq_hits::total 4314 # number of ReadExReq hits 540system.cpu.l2cache.demand_hits::cpu.inst 25235 # number of demand (read+write) hits 541system.cpu.l2cache.demand_hits::cpu.data 32815 # number of demand (read+write) hits 542system.cpu.l2cache.demand_hits::total 58050 # number of demand (read+write) hits 543system.cpu.l2cache.overall_hits::cpu.inst 25235 # number of overall hits 544system.cpu.l2cache.overall_hits::cpu.data 32815 # number of overall hits 545system.cpu.l2cache.overall_hits::total 58050 # number of overall hits 546system.cpu.l2cache.ReadReq_misses::cpu.inst 5715 # number of ReadReq misses 547system.cpu.l2cache.ReadReq_misses::cpu.data 27425 # number of ReadReq misses 548system.cpu.l2cache.ReadReq_misses::total 33140 # number of ReadReq misses 549system.cpu.l2cache.UpgradeReq_misses::cpu.data 39 # number of UpgradeReq misses 550system.cpu.l2cache.UpgradeReq_misses::total 39 # number of UpgradeReq misses 551system.cpu.l2cache.ReadExReq_misses::cpu.data 102595 # number of ReadExReq misses 552system.cpu.l2cache.ReadExReq_misses::total 102595 # number of ReadExReq misses 553system.cpu.l2cache.demand_misses::cpu.inst 5715 # number of demand (read+write) misses 554system.cpu.l2cache.demand_misses::cpu.data 130020 # number of demand (read+write) misses 555system.cpu.l2cache.demand_misses::total 135735 # number of demand (read+write) misses 556system.cpu.l2cache.overall_misses::cpu.inst 5715 # number of overall misses 557system.cpu.l2cache.overall_misses::cpu.data 130020 # number of overall misses 558system.cpu.l2cache.overall_misses::total 135735 # number of overall misses 559system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 195685000 # number of ReadReq miss cycles 560system.cpu.l2cache.ReadReq_miss_latency::cpu.data 938760000 # number of ReadReq miss cycles 561system.cpu.l2cache.ReadReq_miss_latency::total 1134445000 # number of ReadReq miss cycles 562system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 34000 # number of UpgradeReq miss cycles 563system.cpu.l2cache.UpgradeReq_miss_latency::total 34000 # number of UpgradeReq miss cycles 564system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3518172500 # number of ReadExReq miss cycles 565system.cpu.l2cache.ReadExReq_miss_latency::total 3518172500 # number of ReadExReq miss cycles 566system.cpu.l2cache.demand_miss_latency::cpu.inst 195685000 # number of demand (read+write) miss cycles 567system.cpu.l2cache.demand_miss_latency::cpu.data 4456932500 # number of demand (read+write) miss cycles 568system.cpu.l2cache.demand_miss_latency::total 4652617500 # number of demand (read+write) miss cycles 569system.cpu.l2cache.overall_miss_latency::cpu.inst 195685000 # number of overall miss cycles 570system.cpu.l2cache.overall_miss_latency::cpu.data 4456932500 # number of overall miss cycles 571system.cpu.l2cache.overall_miss_latency::total 4652617500 # number of overall miss cycles 572system.cpu.l2cache.ReadReq_accesses::cpu.inst 30950 # number of ReadReq accesses(hits+misses) 573system.cpu.l2cache.ReadReq_accesses::cpu.data 55926 # number of ReadReq accesses(hits+misses) 574system.cpu.l2cache.ReadReq_accesses::total 86876 # number of ReadReq accesses(hits+misses) 575system.cpu.l2cache.Writeback_accesses::writebacks 123771 # number of Writeback accesses(hits+misses) 576system.cpu.l2cache.Writeback_accesses::total 123771 # number of Writeback accesses(hits+misses) 577system.cpu.l2cache.UpgradeReq_accesses::cpu.data 50 # number of UpgradeReq accesses(hits+misses) 578system.cpu.l2cache.UpgradeReq_accesses::total 50 # number of UpgradeReq accesses(hits+misses) 579system.cpu.l2cache.ReadExReq_accesses::cpu.data 106909 # number of ReadExReq accesses(hits+misses) 580system.cpu.l2cache.ReadExReq_accesses::total 106909 # number of ReadExReq accesses(hits+misses) 581system.cpu.l2cache.demand_accesses::cpu.inst 30950 # number of demand (read+write) accesses 582system.cpu.l2cache.demand_accesses::cpu.data 162835 # number of demand (read+write) accesses 583system.cpu.l2cache.demand_accesses::total 193785 # number of demand (read+write) accesses 584system.cpu.l2cache.overall_accesses::cpu.inst 30950 # number of overall (read+write) accesses 585system.cpu.l2cache.overall_accesses::cpu.data 162835 # number of overall (read+write) accesses 586system.cpu.l2cache.overall_accesses::total 193785 # number of overall (read+write) accesses 587system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.184653 # miss rate for ReadReq accesses 588system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.490380 # miss rate for ReadReq accesses 589system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780000 # miss rate for UpgradeReq accesses 590system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.959648 # miss rate for ReadExReq accesses 591system.cpu.l2cache.demand_miss_rate::cpu.inst 0.184653 # miss rate for demand accesses 592system.cpu.l2cache.demand_miss_rate::cpu.data 0.798477 # miss rate for demand accesses 593system.cpu.l2cache.overall_miss_rate::cpu.inst 0.184653 # miss rate for overall accesses 594system.cpu.l2cache.overall_miss_rate::cpu.data 0.798477 # miss rate for overall accesses 595system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34240.594926 # average ReadReq miss latency 596system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34230.082042 # average ReadReq miss latency 597system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 871.794872 # average UpgradeReq miss latency 598system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34291.851455 # average ReadExReq miss latency 599system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34240.594926 # average overall miss latency 600system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34278.822489 # average overall miss latency 601system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34240.594926 # average overall miss latency 602system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34278.822489 # average overall miss latency 603system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 604system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 605system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 606system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 607system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 608system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 609system.cpu.l2cache.fast_writes 0 # number of fast writes performed 610system.cpu.l2cache.cache_copies 0 # number of cache copies performed 611system.cpu.l2cache.writebacks::writebacks 88460 # number of writebacks 612system.cpu.l2cache.writebacks::total 88460 # number of writebacks 613system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 23 # number of ReadReq MSHR hits 614system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits 615system.cpu.l2cache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 616system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits 617system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits 618system.cpu.l2cache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits 619system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits 620system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits 621system.cpu.l2cache.overall_mshr_hits::total 90 # number of overall MSHR hits 622system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5692 # number of ReadReq MSHR misses 623system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27358 # number of ReadReq MSHR misses 624system.cpu.l2cache.ReadReq_mshr_misses::total 33050 # number of ReadReq MSHR misses 625system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 39 # number of UpgradeReq MSHR misses 626system.cpu.l2cache.UpgradeReq_mshr_misses::total 39 # number of UpgradeReq MSHR misses 627system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102595 # number of ReadExReq MSHR misses 628system.cpu.l2cache.ReadExReq_mshr_misses::total 102595 # number of ReadExReq MSHR misses 629system.cpu.l2cache.demand_mshr_misses::cpu.inst 5692 # number of demand (read+write) MSHR misses 630system.cpu.l2cache.demand_mshr_misses::cpu.data 129953 # number of demand (read+write) MSHR misses 631system.cpu.l2cache.demand_mshr_misses::total 135645 # number of demand (read+write) MSHR misses 632system.cpu.l2cache.overall_mshr_misses::cpu.inst 5692 # number of overall MSHR misses 633system.cpu.l2cache.overall_mshr_misses::cpu.data 129953 # number of overall MSHR misses 634system.cpu.l2cache.overall_mshr_misses::total 135645 # number of overall MSHR misses 635system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 176784500 # number of ReadReq MSHR miss cycles 636system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 850283000 # number of ReadReq MSHR miss cycles 637system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1027067500 # number of ReadReq MSHR miss cycles 638system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1211000 # number of UpgradeReq MSHR miss cycles 639system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1211000 # number of UpgradeReq MSHR miss cycles 640system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3193896000 # number of ReadExReq MSHR miss cycles 641system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3193896000 # number of ReadExReq MSHR miss cycles 642system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176784500 # number of demand (read+write) MSHR miss cycles 643system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4044179000 # number of demand (read+write) MSHR miss cycles 644system.cpu.l2cache.demand_mshr_miss_latency::total 4220963500 # number of demand (read+write) MSHR miss cycles 645system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176784500 # number of overall MSHR miss cycles 646system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4044179000 # number of overall MSHR miss cycles 647system.cpu.l2cache.overall_mshr_miss_latency::total 4220963500 # number of overall MSHR miss cycles 648system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for ReadReq accesses 649system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.489182 # mshr miss rate for ReadReq accesses 650system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780000 # mshr miss rate for UpgradeReq accesses 651system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959648 # mshr miss rate for ReadExReq accesses 652system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for demand accesses 653system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.798066 # mshr miss rate for demand accesses 654system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.183910 # mshr miss rate for overall accesses 655system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.798066 # mshr miss rate for overall accesses 656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31058.415320 # average ReadReq mshr miss latency 657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31079.866949 # average ReadReq mshr miss latency 658system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31051.282051 # average UpgradeReq mshr miss latency 659system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31131.107754 # average ReadExReq mshr miss latency 660system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31058.415320 # average overall mshr miss latency 661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31120.320424 # average overall mshr miss latency 662system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31058.415320 # average overall mshr miss latency 663system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31120.320424 # average overall mshr miss latency 664system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 665 666---------- End Simulation Statistics ---------- 667