stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.031183 # Number of seconds simulated 4sim_ticks 31183407000 # Number of ticks simulated 5final_tick 31183407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 157932 # Simulator instruction rate (inst/s) 8host_tick_rate 48938242 # Simulator tick rate (ticks/s) 9host_mem_usage 229072 # Number of bytes of host memory used 10host_seconds 637.20 # Real time elapsed on the host 11sim_insts 100634165 # Number of instructions simulated 12system.physmem.bytes_read 8651648 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 350016 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 5661184 # Number of bytes written to this memory 15system.physmem.num_reads 135182 # Number of read requests responded to by this memory 16system.physmem.num_writes 88456 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 277443962 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 11224431 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 181544756 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 458988718 # Total bandwidth to/from this memory (bytes/s) 22system.cpu.dtb.inst_hits 0 # ITB inst hits 23system.cpu.dtb.inst_misses 0 # ITB inst misses 24system.cpu.dtb.read_hits 0 # DTB read hits 25system.cpu.dtb.read_misses 0 # DTB read misses 26system.cpu.dtb.write_hits 0 # DTB write hits 27system.cpu.dtb.write_misses 0 # DTB write misses 28system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 29system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 33system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 34system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 35system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 36system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37system.cpu.dtb.read_accesses 0 # DTB read accesses 38system.cpu.dtb.write_accesses 0 # DTB write accesses 39system.cpu.dtb.inst_accesses 0 # ITB inst accesses 40system.cpu.dtb.hits 0 # DTB hits 41system.cpu.dtb.misses 0 # DTB misses 42system.cpu.dtb.accesses 0 # DTB accesses 43system.cpu.itb.inst_hits 0 # ITB inst hits 44system.cpu.itb.inst_misses 0 # ITB inst misses 45system.cpu.itb.read_hits 0 # DTB read hits 46system.cpu.itb.read_misses 0 # DTB read misses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 50system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 51system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 52system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 53system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 54system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 56system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 57system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 58system.cpu.itb.read_accesses 0 # DTB read accesses 59system.cpu.itb.write_accesses 0 # DTB write accesses 60system.cpu.itb.inst_accesses 0 # ITB inst accesses 61system.cpu.itb.hits 0 # DTB hits 62system.cpu.itb.misses 0 # DTB misses 63system.cpu.itb.accesses 0 # DTB accesses 64system.cpu.workload.num_syscalls 1946 # Number of system calls 65system.cpu.numCycles 62366815 # number of cpu cycles simulated 66system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 67system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 68system.cpu.BPredUnit.lookups 17631068 # Number of BP lookups 69system.cpu.BPredUnit.condPredicted 11525225 # Number of conditional branches predicted 70system.cpu.BPredUnit.condIncorrect 822451 # Number of conditional branches incorrect 71system.cpu.BPredUnit.BTBLookups 15041021 # Number of BTB lookups 72system.cpu.BPredUnit.BTBHits 9743390 # Number of BTB hits 73system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 74system.cpu.BPredUnit.usedRAS 1887340 # Number of times the RAS was used to get a target. 75system.cpu.BPredUnit.RASInCorrect 176888 # Number of incorrect RAS predictions. 76system.cpu.fetch.icacheStallCycles 12968459 # Number of cycles fetch is stalled on an Icache miss 77system.cpu.fetch.Insts 88523933 # Number of instructions fetch has processed 78system.cpu.fetch.Branches 17631068 # Number of branches that fetch encountered 79system.cpu.fetch.predictedBranches 11630730 # Number of branches that fetch has predicted taken 80system.cpu.fetch.Cycles 22984896 # Number of cycles fetch has run and was not squashing or blocked 81system.cpu.fetch.SquashCycles 2898005 # Number of cycles fetch has spent squashing 82system.cpu.fetch.BlockedCycles 23107334 # Number of cycles fetch has spent blocked 83system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 84system.cpu.fetch.PendingTrapStallCycles 525 # Number of stall cycles due to pending traps 85system.cpu.fetch.CacheLines 12208408 # Number of cache lines fetched 86system.cpu.fetch.IcacheSquashes 230644 # Number of outstanding Icache misses that were squashed 87system.cpu.fetch.rateDist::samples 61059715 # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::mean 2.021356 # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::stdev 3.077680 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::0 38090584 62.38% 62.38% # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::1 2437224 3.99% 66.37% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::2 2605062 4.27% 70.64% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::3 2470326 4.05% 74.69% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::4 1717744 2.81% 77.50% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::5 1704134 2.79% 80.29% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::6 1004081 1.64% 81.93% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::7 1295541 2.12% 84.06% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::8 9735019 15.94% 100.00% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::total 61059715 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.branchRate 0.282700 # Number of branch fetches per cycle 105system.cpu.fetch.rate 1.419408 # Number of inst fetches per cycle 106system.cpu.decode.IdleCycles 14872380 # Number of cycles decode is idle 107system.cpu.decode.BlockedCycles 21838408 # Number of cycles decode is blocked 108system.cpu.decode.RunCycles 21376813 # Number of cycles decode is running 109system.cpu.decode.UnblockCycles 1070090 # Number of cycles decode is unblocking 110system.cpu.decode.SquashCycles 1902024 # Number of cycles decode is squashing 111system.cpu.decode.BranchResolved 3467429 # Number of times decode resolved a branch 112system.cpu.decode.BranchMispred 98061 # Number of times decode detected a branch misprediction 113system.cpu.decode.DecodedInsts 120316029 # Number of instructions handled by decode 114system.cpu.decode.SquashedInsts 332599 # Number of squashed instructions handled by decode 115system.cpu.rename.SquashCycles 1902024 # Number of cycles rename is squashing 116system.cpu.rename.IdleCycles 16801594 # Number of cycles rename is idle 117system.cpu.rename.BlockCycles 2005674 # Number of cycles rename is blocking 118system.cpu.rename.serializeStallCycles 15516104 # count of cycles rename stalled for serializing inst 119system.cpu.rename.RunCycles 20489827 # Number of cycles rename is running 120system.cpu.rename.UnblockCycles 4344492 # Number of cycles rename is unblocking 121system.cpu.rename.RenamedInsts 117017437 # Number of instructions processed by rename 122system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 123system.cpu.rename.IQFullEvents 3607 # Number of times rename has blocked due to IQ full 124system.cpu.rename.LSQFullEvents 2996198 # Number of times rename has blocked due to LSQ full 125system.cpu.rename.FullRegisterEvents 60 # Number of times there has been no free registers 126system.cpu.rename.RenamedOperands 118959985 # Number of destination operands rename has renamed 127system.cpu.rename.RenameLookups 538237718 # Number of register rename lookups that rename has made 128system.cpu.rename.int_rename_lookups 538236225 # Number of integer rename lookups 129system.cpu.rename.fp_rename_lookups 1493 # Number of floating rename lookups 130system.cpu.rename.CommittedMaps 99144333 # Number of HB maps that are committed 131system.cpu.rename.UndoneMaps 19815652 # Number of HB maps that are undone due to squashing 132system.cpu.rename.serializingInsts 778147 # count of serializing insts renamed 133system.cpu.rename.tempSerializingInsts 778546 # count of temporary serializing insts renamed 134system.cpu.rename.skidInsts 12135199 # count of insts added to the skid buffer 135system.cpu.memDep0.insertedLoads 29749057 # Number of loads inserted to the mem dependence unit. 136system.cpu.memDep0.insertedStores 22305499 # Number of stores inserted to the mem dependence unit. 137system.cpu.memDep0.conflictingLoads 2463618 # Number of conflicting loads. 138system.cpu.memDep0.conflictingStores 3436887 # Number of conflicting stores. 139system.cpu.iq.iqInstsAdded 111737256 # Number of instructions added to the IQ (excludes non-spec) 140system.cpu.iq.iqNonSpecInstsAdded 774255 # Number of non-speculative instructions added to the IQ 141system.cpu.iq.iqInstsIssued 107616850 # Number of instructions issued 142system.cpu.iq.iqSquashedInstsIssued 306406 # Number of squashed instructions issued 143system.cpu.iq.iqSquashedInstsExamined 11658627 # Number of squashed instructions iterated over during squash; mainly for profiling 144system.cpu.iq.iqSquashedOperandsExamined 29328565 # Number of squashed operands that are examined and possibly removed from graph 145system.cpu.iq.iqSquashedNonSpecRemoved 71223 # Number of squashed non-spec instructions that were removed 146system.cpu.iq.issued_per_cycle::samples 61059715 # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::mean 1.762485 # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::stdev 1.902924 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::0 22160160 36.29% 36.29% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::1 11614525 19.02% 55.31% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::2 8577298 14.05% 69.36% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::3 7396039 12.11% 81.47% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::4 4782616 7.83% 89.31% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::5 3521695 5.77% 95.07% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::6 1664317 2.73% 97.80% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::7 809749 1.33% 99.13% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::8 533316 0.87% 100.00% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::total 61059715 # Number of insts issued each cycle 163system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 164system.cpu.iq.fu_full::IntAlu 88066 3.33% 3.33% # attempts to use FU when none available 165system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available 166system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available 167system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available 168system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available 172system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available 193system.cpu.iq.fu_full::MemRead 1488278 56.33% 59.66% # attempts to use FU when none available 194system.cpu.iq.fu_full::MemWrite 1065734 40.34% 100.00% # attempts to use FU when none available 195system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 196system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 197system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 198system.cpu.iq.FU_type_0::IntAlu 57002654 52.97% 52.97% # Type of FU issued 199system.cpu.iq.FU_type_0::IntMult 87399 0.08% 53.05% # Type of FU issued 200system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.05% # Type of FU issued 201system.cpu.iq.FU_type_0::FloatAdd 39 0.00% 53.05% # Type of FU issued 202system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.05% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.05% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.05% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.05% # Type of FU issued 206system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.05% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.05% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.05% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.05% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.05% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.05% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.05% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.05% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.05% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.05% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.05% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.05% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.05% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.05% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.05% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.05% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.05% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.05% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.05% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.05% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.05% # Type of FU issued 227system.cpu.iq.FU_type_0::MemRead 28992824 26.94% 79.99% # Type of FU issued 228system.cpu.iq.FU_type_0::MemWrite 21533927 20.01% 100.00% # Type of FU issued 229system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 230system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 231system.cpu.iq.FU_type_0::total 107616850 # Type of FU issued 232system.cpu.iq.rate 1.725547 # Inst issue rate 233system.cpu.iq.fu_busy_cnt 2642078 # FU busy when requested 234system.cpu.iq.fu_busy_rate 0.024551 # FU busy rate (busy events/executed inst) 235system.cpu.iq.int_inst_queue_reads 279241693 # Number of integer instruction queue reads 236system.cpu.iq.int_inst_queue_writes 124185257 # Number of integer instruction queue writes 237system.cpu.iq.int_inst_queue_wakeup_accesses 105412682 # Number of integer instruction queue wakeup accesses 238system.cpu.iq.fp_inst_queue_reads 206 # Number of floating instruction queue reads 239system.cpu.iq.fp_inst_queue_writes 204 # Number of floating instruction queue writes 240system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses 241system.cpu.iq.int_alu_accesses 110258821 # Number of integer alu accesses 242system.cpu.iq.fp_alu_accesses 107 # Number of floating point alu accesses 243system.cpu.iew.lsq.thread0.forwLoads 1870348 # Number of loads that had data forwarded from stores 244system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 245system.cpu.iew.lsq.thread0.squashedLoads 2440492 # Number of loads squashed 246system.cpu.iew.lsq.thread0.ignoredResponses 3482 # Number of memory responses ignored because the instruction is squashed 247system.cpu.iew.lsq.thread0.memOrderViolation 15956 # Number of memory ordering violations 248system.cpu.iew.lsq.thread0.squashedStores 1748305 # Number of stores squashed 249system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 250system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 251system.cpu.iew.lsq.thread0.rescheduledLoads 52 # Number of loads that were rescheduled 252system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked 253system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 254system.cpu.iew.iewSquashCycles 1902024 # Number of cycles IEW is squashing 255system.cpu.iew.iewBlockCycles 953128 # Number of cycles IEW is blocking 256system.cpu.iew.iewUnblockCycles 28578 # Number of cycles IEW is unblocking 257system.cpu.iew.iewDispatchedInsts 112587966 # Number of instructions dispatched to IQ 258system.cpu.iew.iewDispSquashedInsts 618611 # Number of squashed instructions skipped by dispatch 259system.cpu.iew.iewDispLoadInsts 29749057 # Number of dispatched load instructions 260system.cpu.iew.iewDispStoreInsts 22305499 # Number of dispatched store instructions 261system.cpu.iew.iewDispNonSpecInsts 756996 # Number of dispatched non-speculative instructions 262system.cpu.iew.iewIQFullEvents 1135 # Number of times the IQ has become full, causing a stall 263system.cpu.iew.iewLSQFullEvents 1192 # Number of times the LSQ has become full, causing a stall 264system.cpu.iew.memOrderViolationEvents 15956 # Number of memory order violations 265system.cpu.iew.predictedTakenIncorrect 682416 # Number of branches that were predicted taken incorrectly 266system.cpu.iew.predictedNotTakenIncorrect 198748 # Number of branches that were predicted not taken incorrectly 267system.cpu.iew.branchMispredicts 881164 # Number of branch mispredicts detected at execute 268system.cpu.iew.iewExecutedInsts 106274273 # Number of executed instructions 269system.cpu.iew.iewExecLoadInsts 28622040 # Number of load instructions executed 270system.cpu.iew.iewExecSquashedInsts 1342577 # Number of squashed instructions skipped in execute 271system.cpu.iew.exec_swp 0 # number of swp insts executed 272system.cpu.iew.exec_nop 76455 # number of nop insts executed 273system.cpu.iew.exec_refs 49853649 # number of memory reference insts executed 274system.cpu.iew.exec_branches 14601408 # Number of branches executed 275system.cpu.iew.exec_stores 21231609 # Number of stores executed 276system.cpu.iew.exec_rate 1.704020 # Inst execution rate 277system.cpu.iew.wb_sent 105725224 # cumulative count of insts sent to commit 278system.cpu.iew.wb_count 105412758 # cumulative count of insts written-back 279system.cpu.iew.wb_producers 52507879 # num instructions producing a value 280system.cpu.iew.wb_consumers 101154765 # num instructions consuming a value 281system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 282system.cpu.iew.wb_rate 1.690206 # insts written-back per cycle 283system.cpu.iew.wb_fanout 0.519085 # average fanout of values written-back 284system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 285system.cpu.commit.commitCommittedInsts 100639717 # The number of committed instructions 286system.cpu.commit.commitSquashedInsts 11948697 # The number of squashed insts skipped by commit 287system.cpu.commit.commitNonSpecStalls 703032 # The number of times commit has been forced to stall to communicate backwards 288system.cpu.commit.branchMispredicts 788200 # The number of times a branch was mispredicted 289system.cpu.commit.committed_per_cycle::samples 59157692 # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::mean 1.701211 # Number of insts commited each cycle 291system.cpu.commit.committed_per_cycle::stdev 2.430896 # Number of insts commited each cycle 292system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::0 26246617 44.37% 44.37% # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::1 14635662 24.74% 69.11% # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::2 4223894 7.14% 76.25% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::3 3641491 6.16% 82.40% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::4 2268632 3.83% 86.24% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::5 1889350 3.19% 89.43% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::6 703853 1.19% 90.62% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::7 498146 0.84% 91.46% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::8 5050047 8.54% 100.00% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::total 59157692 # Number of insts commited each cycle 306system.cpu.commit.count 100639717 # Number of instructions committed 307system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 308system.cpu.commit.refs 47865759 # Number of memory references committed 309system.cpu.commit.loads 27308565 # Number of loads committed 310system.cpu.commit.membars 15920 # Number of memory barriers committed 311system.cpu.commit.branches 13670084 # Number of branches committed 312system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 313system.cpu.commit.int_insts 91478611 # Number of committed integer instructions. 314system.cpu.commit.function_calls 1679850 # Number of function calls committed. 315system.cpu.commit.bw_lim_events 5050047 # number cycles where commit BW limit reached 316system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 317system.cpu.rob.rob_reads 166670760 # The number of ROB reads 318system.cpu.rob.rob_writes 227084538 # The number of ROB writes 319system.cpu.timesIdled 61622 # Number of times that the entire CPU went into an idle state and unscheduled itself 320system.cpu.idleCycles 1307100 # Total number of cycles that the CPU has spent unscheduled due to idling 321system.cpu.committedInsts 100634165 # Number of Instructions Simulated 322system.cpu.committedInsts_total 100634165 # Number of Instructions Simulated 323system.cpu.cpi 0.619738 # CPI: Cycles Per Instruction 324system.cpu.cpi_total 0.619738 # CPI: Total CPI of All Threads 325system.cpu.ipc 1.613585 # IPC: Instructions Per Cycle 326system.cpu.ipc_total 1.613585 # IPC: Total IPC of All Threads 327system.cpu.int_regfile_reads 511657086 # number of integer regfile reads 328system.cpu.int_regfile_writes 103892124 # number of integer regfile writes 329system.cpu.fp_regfile_reads 166 # number of floating regfile reads 330system.cpu.fp_regfile_writes 126 # number of floating regfile writes 331system.cpu.misc_regfile_reads 146210782 # number of misc regfile reads 332system.cpu.misc_regfile_writes 34752 # number of misc regfile writes 333system.cpu.icache.replacements 26083 # number of replacements 334system.cpu.icache.tagsinuse 1805.405384 # Cycle average of tags in use 335system.cpu.icache.total_refs 12179175 # Total number of references to valid blocks. 336system.cpu.icache.sampled_refs 28115 # Sample count of references to valid blocks. 337system.cpu.icache.avg_refs 433.191357 # Average number of references to valid blocks. 338system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 339system.cpu.icache.occ_blocks::0 1805.405384 # Average occupied blocks per context 340system.cpu.icache.occ_percent::0 0.881546 # Average percentage of cache occupancy 341system.cpu.icache.ReadReq_hits 12179178 # number of ReadReq hits 342system.cpu.icache.demand_hits 12179178 # number of demand (read+write) hits 343system.cpu.icache.overall_hits 12179178 # number of overall hits 344system.cpu.icache.ReadReq_misses 29230 # number of ReadReq misses 345system.cpu.icache.demand_misses 29230 # number of demand (read+write) misses 346system.cpu.icache.overall_misses 29230 # number of overall misses 347system.cpu.icache.ReadReq_miss_latency 357885000 # number of ReadReq miss cycles 348system.cpu.icache.demand_miss_latency 357885000 # number of demand (read+write) miss cycles 349system.cpu.icache.overall_miss_latency 357885000 # number of overall miss cycles 350system.cpu.icache.ReadReq_accesses 12208408 # number of ReadReq accesses(hits+misses) 351system.cpu.icache.demand_accesses 12208408 # number of demand (read+write) accesses 352system.cpu.icache.overall_accesses 12208408 # number of overall (read+write) accesses 353system.cpu.icache.ReadReq_miss_rate 0.002394 # miss rate for ReadReq accesses 354system.cpu.icache.demand_miss_rate 0.002394 # miss rate for demand accesses 355system.cpu.icache.overall_miss_rate 0.002394 # miss rate for overall accesses 356system.cpu.icache.ReadReq_avg_miss_latency 12243.756415 # average ReadReq miss latency 357system.cpu.icache.demand_avg_miss_latency 12243.756415 # average overall miss latency 358system.cpu.icache.overall_avg_miss_latency 12243.756415 # average overall miss latency 359system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 360system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 361system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 362system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 363system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 364system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 365system.cpu.icache.fast_writes 0 # number of fast writes performed 366system.cpu.icache.cache_copies 0 # number of cache copies performed 367system.cpu.icache.writebacks 1 # number of writebacks 368system.cpu.icache.ReadReq_mshr_hits 1069 # number of ReadReq MSHR hits 369system.cpu.icache.demand_mshr_hits 1069 # number of demand (read+write) MSHR hits 370system.cpu.icache.overall_mshr_hits 1069 # number of overall MSHR hits 371system.cpu.icache.ReadReq_mshr_misses 28161 # number of ReadReq MSHR misses 372system.cpu.icache.demand_mshr_misses 28161 # number of demand (read+write) MSHR misses 373system.cpu.icache.overall_mshr_misses 28161 # number of overall MSHR misses 374system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 375system.cpu.icache.ReadReq_mshr_miss_latency 246973000 # number of ReadReq MSHR miss cycles 376system.cpu.icache.demand_mshr_miss_latency 246973000 # number of demand (read+write) MSHR miss cycles 377system.cpu.icache.overall_mshr_miss_latency 246973000 # number of overall MSHR miss cycles 378system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 379system.cpu.icache.ReadReq_mshr_miss_rate 0.002307 # mshr miss rate for ReadReq accesses 380system.cpu.icache.demand_mshr_miss_rate 0.002307 # mshr miss rate for demand accesses 381system.cpu.icache.overall_mshr_miss_rate 0.002307 # mshr miss rate for overall accesses 382system.cpu.icache.ReadReq_avg_mshr_miss_latency 8770.036575 # average ReadReq mshr miss latency 383system.cpu.icache.demand_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency 384system.cpu.icache.overall_avg_mshr_miss_latency 8770.036575 # average overall mshr miss latency 385system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 386system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 387system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 388system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 389system.cpu.dcache.replacements 157879 # number of replacements 390system.cpu.dcache.tagsinuse 4072.329363 # Cycle average of tags in use 391system.cpu.dcache.total_refs 44742203 # Total number of references to valid blocks. 392system.cpu.dcache.sampled_refs 161975 # Sample count of references to valid blocks. 393system.cpu.dcache.avg_refs 276.229066 # Average number of references to valid blocks. 394system.cpu.dcache.warmup_cycle 306596000 # Cycle when the warmup percentage was hit. 395system.cpu.dcache.occ_blocks::0 4072.329363 # Average occupied blocks per context 396system.cpu.dcache.occ_percent::0 0.994221 # Average percentage of cache occupancy 397system.cpu.dcache.ReadReq_hits 26395464 # number of ReadReq hits 398system.cpu.dcache.WriteReq_hits 18310275 # number of WriteReq hits 399system.cpu.dcache.LoadLockedReq_hits 18919 # number of LoadLockedReq hits 400system.cpu.dcache.StoreCondReq_hits 17375 # number of StoreCondReq hits 401system.cpu.dcache.demand_hits 44705739 # number of demand (read+write) hits 402system.cpu.dcache.overall_hits 44705739 # number of overall hits 403system.cpu.dcache.ReadReq_misses 108834 # number of ReadReq misses 404system.cpu.dcache.WriteReq_misses 1539626 # number of WriteReq misses 405system.cpu.dcache.LoadLockedReq_misses 27 # number of LoadLockedReq misses 406system.cpu.dcache.demand_misses 1648460 # number of demand (read+write) misses 407system.cpu.dcache.overall_misses 1648460 # number of overall misses 408system.cpu.dcache.ReadReq_miss_latency 2418698500 # number of ReadReq miss cycles 409system.cpu.dcache.WriteReq_miss_latency 52283649500 # number of WriteReq miss cycles 410system.cpu.dcache.LoadLockedReq_miss_latency 386000 # number of LoadLockedReq miss cycles 411system.cpu.dcache.demand_miss_latency 54702348000 # number of demand (read+write) miss cycles 412system.cpu.dcache.overall_miss_latency 54702348000 # number of overall miss cycles 413system.cpu.dcache.ReadReq_accesses 26504298 # number of ReadReq accesses(hits+misses) 414system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) 415system.cpu.dcache.LoadLockedReq_accesses 18946 # number of LoadLockedReq accesses(hits+misses) 416system.cpu.dcache.StoreCondReq_accesses 17375 # number of StoreCondReq accesses(hits+misses) 417system.cpu.dcache.demand_accesses 46354199 # number of demand (read+write) accesses 418system.cpu.dcache.overall_accesses 46354199 # number of overall (read+write) accesses 419system.cpu.dcache.ReadReq_miss_rate 0.004106 # miss rate for ReadReq accesses 420system.cpu.dcache.WriteReq_miss_rate 0.077563 # miss rate for WriteReq accesses 421system.cpu.dcache.LoadLockedReq_miss_rate 0.001425 # miss rate for LoadLockedReq accesses 422system.cpu.dcache.demand_miss_rate 0.035562 # miss rate for demand accesses 423system.cpu.dcache.overall_miss_rate 0.035562 # miss rate for overall accesses 424system.cpu.dcache.ReadReq_avg_miss_latency 22223.739824 # average ReadReq miss latency 425system.cpu.dcache.WriteReq_avg_miss_latency 33958.668859 # average WriteReq miss latency 426system.cpu.dcache.LoadLockedReq_avg_miss_latency 14296.296296 # average LoadLockedReq miss latency 427system.cpu.dcache.demand_avg_miss_latency 33183.909831 # average overall miss latency 428system.cpu.dcache.overall_avg_miss_latency 33183.909831 # average overall miss latency 429system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 430system.cpu.dcache.blocked_cycles::no_targets 190500 # number of cycles access was blocked 431system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 432system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked 433system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 434system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked 435system.cpu.dcache.fast_writes 0 # number of fast writes performed 436system.cpu.dcache.cache_copies 0 # number of cache copies performed 437system.cpu.dcache.writebacks 123472 # number of writebacks 438system.cpu.dcache.ReadReq_mshr_hits 53734 # number of ReadReq MSHR hits 439system.cpu.dcache.WriteReq_mshr_hits 1432703 # number of WriteReq MSHR hits 440system.cpu.dcache.LoadLockedReq_mshr_hits 27 # number of LoadLockedReq MSHR hits 441system.cpu.dcache.demand_mshr_hits 1486437 # number of demand (read+write) MSHR hits 442system.cpu.dcache.overall_mshr_hits 1486437 # number of overall MSHR hits 443system.cpu.dcache.ReadReq_mshr_misses 55100 # number of ReadReq MSHR misses 444system.cpu.dcache.WriteReq_mshr_misses 106923 # number of WriteReq MSHR misses 445system.cpu.dcache.demand_mshr_misses 162023 # number of demand (read+write) MSHR misses 446system.cpu.dcache.overall_mshr_misses 162023 # number of overall MSHR misses 447system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 448system.cpu.dcache.ReadReq_mshr_miss_latency 1035726000 # number of ReadReq MSHR miss cycles 449system.cpu.dcache.WriteReq_mshr_miss_latency 3662471000 # number of WriteReq MSHR miss cycles 450system.cpu.dcache.demand_mshr_miss_latency 4698197000 # number of demand (read+write) MSHR miss cycles 451system.cpu.dcache.overall_mshr_miss_latency 4698197000 # number of overall MSHR miss cycles 452system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 453system.cpu.dcache.ReadReq_mshr_miss_rate 0.002079 # mshr miss rate for ReadReq accesses 454system.cpu.dcache.WriteReq_mshr_miss_rate 0.005387 # mshr miss rate for WriteReq accesses 455system.cpu.dcache.demand_mshr_miss_rate 0.003495 # mshr miss rate for demand accesses 456system.cpu.dcache.overall_mshr_miss_rate 0.003495 # mshr miss rate for overall accesses 457system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18797.205082 # average ReadReq mshr miss latency 458system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.350542 # average WriteReq mshr miss latency 459system.cpu.dcache.demand_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency 460system.cpu.dcache.overall_avg_mshr_miss_latency 28997.099177 # average overall mshr miss latency 461system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 462system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 463system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 464system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 465system.cpu.l2cache.replacements 114920 # number of replacements 466system.cpu.l2cache.tagsinuse 18304.700184 # Cycle average of tags in use 467system.cpu.l2cache.total_refs 72415 # Total number of references to valid blocks. 468system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks. 469system.cpu.l2cache.avg_refs 0.541323 # Average number of references to valid blocks. 470system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 471system.cpu.l2cache.occ_blocks::0 2370.650310 # Average occupied blocks per context 472system.cpu.l2cache.occ_blocks::1 15934.049874 # Average occupied blocks per context 473system.cpu.l2cache.occ_percent::0 0.072347 # Average percentage of cache occupancy 474system.cpu.l2cache.occ_percent::1 0.486269 # Average percentage of cache occupancy 475system.cpu.l2cache.ReadReq_hits 50510 # number of ReadReq hits 476system.cpu.l2cache.Writeback_hits 123473 # number of Writeback hits 477system.cpu.l2cache.UpgradeReq_hits 16 # number of UpgradeReq hits 478system.cpu.l2cache.ReadExReq_hits 4309 # number of ReadExReq hits 479system.cpu.l2cache.demand_hits 54819 # number of demand (read+write) hits 480system.cpu.l2cache.overall_hits 54819 # number of overall hits 481system.cpu.l2cache.ReadReq_misses 32664 # number of ReadReq misses 482system.cpu.l2cache.UpgradeReq_misses 31 # number of UpgradeReq misses 483system.cpu.l2cache.ReadExReq_misses 102598 # number of ReadExReq misses 484system.cpu.l2cache.demand_misses 135262 # number of demand (read+write) misses 485system.cpu.l2cache.overall_misses 135262 # number of overall misses 486system.cpu.l2cache.ReadReq_miss_latency 1118309000 # number of ReadReq miss cycles 487system.cpu.l2cache.ReadExReq_miss_latency 3526121000 # number of ReadExReq miss cycles 488system.cpu.l2cache.demand_miss_latency 4644430000 # number of demand (read+write) miss cycles 489system.cpu.l2cache.overall_miss_latency 4644430000 # number of overall miss cycles 490system.cpu.l2cache.ReadReq_accesses 83174 # number of ReadReq accesses(hits+misses) 491system.cpu.l2cache.Writeback_accesses 123473 # number of Writeback accesses(hits+misses) 492system.cpu.l2cache.UpgradeReq_accesses 47 # number of UpgradeReq accesses(hits+misses) 493system.cpu.l2cache.ReadExReq_accesses 106907 # number of ReadExReq accesses(hits+misses) 494system.cpu.l2cache.demand_accesses 190081 # number of demand (read+write) accesses 495system.cpu.l2cache.overall_accesses 190081 # number of overall (read+write) accesses 496system.cpu.l2cache.ReadReq_miss_rate 0.392719 # miss rate for ReadReq accesses 497system.cpu.l2cache.UpgradeReq_miss_rate 0.659574 # miss rate for UpgradeReq accesses 498system.cpu.l2cache.ReadExReq_miss_rate 0.959694 # miss rate for ReadExReq accesses 499system.cpu.l2cache.demand_miss_rate 0.711602 # miss rate for demand accesses 500system.cpu.l2cache.overall_miss_rate 0.711602 # miss rate for overall accesses 501system.cpu.l2cache.ReadReq_avg_miss_latency 34236.743816 # average ReadReq miss latency 502system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.321020 # average ReadExReq miss latency 503system.cpu.l2cache.demand_avg_miss_latency 34336.546850 # average overall miss latency 504system.cpu.l2cache.overall_avg_miss_latency 34336.546850 # average overall miss latency 505system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 506system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 507system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 508system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 509system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 510system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 511system.cpu.l2cache.fast_writes 0 # number of fast writes performed 512system.cpu.l2cache.cache_copies 0 # number of cache copies performed 513system.cpu.l2cache.writebacks 88456 # number of writebacks 514system.cpu.l2cache.ReadReq_mshr_hits 80 # number of ReadReq MSHR hits 515system.cpu.l2cache.demand_mshr_hits 80 # number of demand (read+write) MSHR hits 516system.cpu.l2cache.overall_mshr_hits 80 # number of overall MSHR hits 517system.cpu.l2cache.ReadReq_mshr_misses 32584 # number of ReadReq MSHR misses 518system.cpu.l2cache.UpgradeReq_mshr_misses 31 # number of UpgradeReq MSHR misses 519system.cpu.l2cache.ReadExReq_mshr_misses 102598 # number of ReadExReq MSHR misses 520system.cpu.l2cache.demand_mshr_misses 135182 # number of demand (read+write) MSHR misses 521system.cpu.l2cache.overall_mshr_misses 135182 # number of overall MSHR misses 522system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 523system.cpu.l2cache.ReadReq_mshr_miss_latency 1012754000 # number of ReadReq MSHR miss cycles 524system.cpu.l2cache.UpgradeReq_mshr_miss_latency 962000 # number of UpgradeReq MSHR miss cycles 525system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197891500 # number of ReadExReq MSHR miss cycles 526system.cpu.l2cache.demand_mshr_miss_latency 4210645500 # number of demand (read+write) MSHR miss cycles 527system.cpu.l2cache.overall_mshr_miss_latency 4210645500 # number of overall MSHR miss cycles 528system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 529system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391757 # mshr miss rate for ReadReq accesses 530system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.659574 # mshr miss rate for UpgradeReq accesses 531system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959694 # mshr miss rate for ReadExReq accesses 532system.cpu.l2cache.demand_mshr_miss_rate 0.711181 # mshr miss rate for demand accesses 533system.cpu.l2cache.overall_mshr_miss_rate 0.711181 # mshr miss rate for overall accesses 534system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.328259 # average ReadReq mshr miss latency 535system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31032.258065 # average UpgradeReq mshr miss latency 536system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.140724 # average ReadExReq mshr miss latency 537system.cpu.l2cache.demand_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency 538system.cpu.l2cache.overall_avg_mshr_miss_latency 31147.974582 # average overall mshr miss latency 539system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 540system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 541system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 542system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 543 544---------- End Simulation Statistics ---------- 545