stats.txt revision 10827:7f5467f2f8b8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.033331 # Number of seconds simulated 4sim_ticks 33330913000 # Number of ticks simulated 5final_tick 33330913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 123947 # Simulator instruction rate (inst/s) 8host_op_rate 158514 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58262578 # Simulator tick rate (ticks/s) 10host_mem_usage 323704 # Number of bytes of host memory used 11host_seconds 572.08 # Real time elapsed on the host 12sim_insts 70907630 # Number of instructions simulated 13sim_ops 90682585 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 583488 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2505024 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 6203200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9291712 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 583488 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 583488 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6256128 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6256128 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 9117 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 39141 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 96925 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 145183 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 97752 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 97752 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 17505911 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 75156177 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 186109513 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 278771602 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 17505911 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 17505911 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 187697469 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 187697469 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 187697469 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 17505911 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 75156177 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 186109513 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 466469070 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 145183 # Number of read requests accepted 44system.physmem.writeReqs 97752 # Number of write requests accepted 45system.physmem.readBursts 145183 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 97752 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 9284992 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue 49system.physmem.bytesWritten 6254720 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 9291712 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 6256128 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 9145 # Per bank write bursts 56system.physmem.perBankRdBursts::1 9372 # Per bank write bursts 57system.physmem.perBankRdBursts::2 9233 # Per bank write bursts 58system.physmem.perBankRdBursts::3 9500 # Per bank write bursts 59system.physmem.perBankRdBursts::4 9743 # Per bank write bursts 60system.physmem.perBankRdBursts::5 9700 # Per bank write bursts 61system.physmem.perBankRdBursts::6 9083 # Per bank write bursts 62system.physmem.perBankRdBursts::7 8995 # Per bank write bursts 63system.physmem.perBankRdBursts::8 9233 # Per bank write bursts 64system.physmem.perBankRdBursts::9 8567 # Per bank write bursts 65system.physmem.perBankRdBursts::10 8856 # Per bank write bursts 66system.physmem.perBankRdBursts::11 8704 # Per bank write bursts 67system.physmem.perBankRdBursts::12 8629 # Per bank write bursts 68system.physmem.perBankRdBursts::13 8694 # Per bank write bursts 69system.physmem.perBankRdBursts::14 8697 # Per bank write bursts 70system.physmem.perBankRdBursts::15 8927 # Per bank write bursts 71system.physmem.perBankWrBursts::0 5993 # Per bank write bursts 72system.physmem.perBankWrBursts::1 6233 # Per bank write bursts 73system.physmem.perBankWrBursts::2 6131 # Per bank write bursts 74system.physmem.perBankWrBursts::3 6188 # Per bank write bursts 75system.physmem.perBankWrBursts::4 6147 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6290 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6056 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6014 # Per bank write bursts 79system.physmem.perBankWrBursts::8 6000 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6152 # Per bank write bursts 81system.physmem.perBankWrBursts::10 6228 # Per bank write bursts 82system.physmem.perBankWrBursts::11 5920 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6078 # Per bank write bursts 84system.physmem.perBankWrBursts::13 6086 # Per bank write bursts 85system.physmem.perBankWrBursts::14 6193 # Per bank write bursts 86system.physmem.perBankWrBursts::15 6021 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 33330641500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 145183 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 97752 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 41867 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 51877 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 18150 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 9231 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6097 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 5279 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 4608 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4276 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3567 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 88 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1146 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1166 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1898 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 2645 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 3422 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4431 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5253 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5631 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5913 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6185 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6430 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 7378 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 8983 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 8099 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 7186 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6431 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 258 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 127 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 55 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 21 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 88649 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 175.273178 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 110.551570 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 239.030923 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 52157 58.84% 58.84% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 22538 25.42% 84.26% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4461 5.03% 89.29% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1758 1.98% 91.27% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1068 1.20% 92.48% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 785 0.89% 93.36% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 713 0.80% 94.17% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 748 0.84% 95.01% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 4421 4.99% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 88649 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 24.566130 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 21.054973 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 187.117675 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 5904 99.98% 99.98% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 16.550381 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 16.508750 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.243905 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 4712 79.80% 79.80% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::17 29 0.49% 80.29% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18 757 12.82% 93.11% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::19 163 2.76% 95.87% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::20 111 1.88% 97.75% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::21 62 1.05% 98.80% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::22 43 0.73% 99.53% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::23 20 0.34% 99.86% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::24 6 0.10% 99.97% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads 236system.physmem.totQLat 7425181339 # Total ticks spent queuing 237system.physmem.totMemAccLat 10145393839 # Total ticks spent from burst creation until serviced by the DRAM 238system.physmem.totBusLat 725390000 # Total ticks spent in databus transfers 239system.physmem.avgQLat 51180.62 # Average queueing delay per DRAM burst 240system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 241system.physmem.avgMemAccLat 69930.62 # Average memory access latency per DRAM burst 242system.physmem.avgRdBW 278.57 # Average DRAM read bandwidth in MiByte/s 243system.physmem.avgWrBW 187.66 # Average achieved write bandwidth in MiByte/s 244system.physmem.avgRdBWSys 278.77 # Average system read bandwidth in MiByte/s 245system.physmem.avgWrBWSys 187.70 # Average system write bandwidth in MiByte/s 246system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 247system.physmem.busUtil 3.64 # Data bus utilization in percentage 248system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads 249system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes 250system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing 251system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing 252system.physmem.readRowHits 117819 # Number of row buffer hits during reads 253system.physmem.writeRowHits 36329 # Number of row buffer hits during writes 254system.physmem.readRowHitRate 81.21 # Row buffer hit rate for reads 255system.physmem.writeRowHitRate 37.16 # Row buffer hit rate for writes 256system.physmem.avgGap 137199.83 # Average gap between requests 257system.physmem.pageHitRate 63.48 # Row buffer hit rate, read and write combined 258system.physmem_0.actEnergy 342679680 # Energy for activate commands per rank (pJ) 259system.physmem_0.preEnergy 186978000 # Energy for precharge commands per rank (pJ) 260system.physmem_0.readEnergy 582769200 # Energy for read commands per rank (pJ) 261system.physmem_0.writeEnergy 317714400 # Energy for write commands per rank (pJ) 262system.physmem_0.refreshEnergy 2176636800 # Energy for refresh commands per rank (pJ) 263system.physmem_0.actBackEnergy 11943657450 # Energy for active background per rank (pJ) 264system.physmem_0.preBackEnergy 9518358000 # Energy for precharge background per rank (pJ) 265system.physmem_0.totalEnergy 25068793530 # Total energy per rank (pJ) 266system.physmem_0.averagePower 752.242445 # Core power per rank (mW) 267system.physmem_0.memoryStateTime::IDLE 15735797307 # Time in different power states 268system.physmem_0.memoryStateTime::REF 1112800000 # Time in different power states 269system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 270system.physmem_0.memoryStateTime::ACT 16476833443 # Time in different power states 271system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 272system.physmem_1.actEnergy 327053160 # Energy for activate commands per rank (pJ) 273system.physmem_1.preEnergy 178451625 # Energy for precharge commands per rank (pJ) 274system.physmem_1.readEnergy 548121600 # Energy for read commands per rank (pJ) 275system.physmem_1.writeEnergy 315264960 # Energy for write commands per rank (pJ) 276system.physmem_1.refreshEnergy 2176636800 # Energy for refresh commands per rank (pJ) 277system.physmem_1.actBackEnergy 11265215805 # Energy for active background per rank (pJ) 278system.physmem_1.preBackEnergy 10113486000 # Energy for precharge background per rank (pJ) 279system.physmem_1.totalEnergy 24924229950 # Total energy per rank (pJ) 280system.physmem_1.averagePower 747.904367 # Core power per rank (mW) 281system.physmem_1.memoryStateTime::IDLE 16730540892 # Time in different power states 282system.physmem_1.memoryStateTime::REF 1112800000 # Time in different power states 283system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 284system.physmem_1.memoryStateTime::ACT 15482244108 # Time in different power states 285system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 286system.cpu.branchPred.lookups 17205793 # Number of BP lookups 287system.cpu.branchPred.condPredicted 11516695 # Number of conditional branches predicted 288system.cpu.branchPred.condIncorrect 648305 # Number of conditional branches incorrect 289system.cpu.branchPred.BTBLookups 9352037 # Number of BTB lookups 290system.cpu.branchPred.BTBHits 7676056 # Number of BTB hits 291system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 292system.cpu.branchPred.BTBHitPct 82.078974 # BTB Hit Percentage 293system.cpu.branchPred.usedRAS 1873350 # Number of times the RAS was used to get a target. 294system.cpu.branchPred.RASInCorrect 101557 # Number of incorrect RAS predictions. 295system.cpu_clk_domain.clock 500 # Clock period in ticks 296system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 305system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 306system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 307system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 308system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 309system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 310system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 320system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 321system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 322system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 323system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 324system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 325system.cpu.dtb.walker.walks 0 # Table walker walks requested 326system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.inst_hits 0 # ITB inst hits 334system.cpu.dtb.inst_misses 0 # ITB inst misses 335system.cpu.dtb.read_hits 0 # DTB read hits 336system.cpu.dtb.read_misses 0 # DTB read misses 337system.cpu.dtb.write_hits 0 # DTB write hits 338system.cpu.dtb.write_misses 0 # DTB write misses 339system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 0 # DTB read accesses 349system.cpu.dtb.write_accesses 0 # DTB write accesses 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses 351system.cpu.dtb.hits 0 # DTB hits 352system.cpu.dtb.misses 0 # DTB misses 353system.cpu.dtb.accesses 0 # DTB accesses 354system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 363system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 364system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 365system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 366system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 367system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 368system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 372system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 373system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 374system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 375system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 378system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 379system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 380system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 381system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 382system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 383system.cpu.itb.walker.walks 0 # Table walker walks requested 384system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.inst_hits 0 # ITB inst hits 392system.cpu.itb.inst_misses 0 # ITB inst misses 393system.cpu.itb.read_hits 0 # DTB read hits 394system.cpu.itb.read_misses 0 # DTB read misses 395system.cpu.itb.write_hits 0 # DTB write hits 396system.cpu.itb.write_misses 0 # DTB write misses 397system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 398system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 399system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 402system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu.itb.read_accesses 0 # DTB read accesses 407system.cpu.itb.write_accesses 0 # DTB write accesses 408system.cpu.itb.inst_accesses 0 # ITB inst accesses 409system.cpu.itb.hits 0 # DTB hits 410system.cpu.itb.misses 0 # DTB misses 411system.cpu.itb.accesses 0 # DTB accesses 412system.cpu.workload.num_syscalls 1946 # Number of system calls 413system.cpu.numCycles 66661827 # number of cpu cycles simulated 414system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 415system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 416system.cpu.fetch.icacheStallCycles 4979954 # Number of cycles fetch is stalled on an Icache miss 417system.cpu.fetch.Insts 88191186 # Number of instructions fetch has processed 418system.cpu.fetch.Branches 17205793 # Number of branches that fetch encountered 419system.cpu.fetch.predictedBranches 9549406 # Number of branches that fetch has predicted taken 420system.cpu.fetch.Cycles 60159688 # Number of cycles fetch has run and was not squashing or blocked 421system.cpu.fetch.SquashCycles 1322593 # Number of cycles fetch has spent squashing 422system.cpu.fetch.MiscStallCycles 6446 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 423system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps 424system.cpu.fetch.IcacheWaitRetryStallCycles 13285 # Number of stall cycles due to full MSHR 425system.cpu.fetch.CacheLines 22768352 # Number of cache lines fetched 426system.cpu.fetch.IcacheSquashes 68999 # Number of outstanding Icache misses that were squashed 427system.cpu.fetch.rateDist::samples 65820694 # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::mean 1.695691 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::stdev 1.296532 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::0 20039717 30.45% 30.45% # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::1 8265549 12.56% 43.00% # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::2 9200264 13.98% 56.98% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::3 28315164 43.02% 100.00% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::total 65820694 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.branchRate 0.258106 # Number of branch fetches per cycle 440system.cpu.fetch.rate 1.322964 # Number of inst fetches per cycle 441system.cpu.decode.IdleCycles 8562659 # Number of cycles decode is idle 442system.cpu.decode.BlockedCycles 19557917 # Number of cycles decode is blocked 443system.cpu.decode.RunCycles 31575920 # Number of cycles decode is running 444system.cpu.decode.UnblockCycles 5632021 # Number of cycles decode is unblocking 445system.cpu.decode.SquashCycles 492177 # Number of cycles decode is squashing 446system.cpu.decode.BranchResolved 3179708 # Number of times decode resolved a branch 447system.cpu.decode.BranchMispred 171007 # Number of times decode detected a branch misprediction 448system.cpu.decode.DecodedInsts 101418024 # Number of instructions handled by decode 449system.cpu.decode.SquashedInsts 3051775 # Number of squashed instructions handled by decode 450system.cpu.rename.SquashCycles 492177 # Number of cycles rename is squashing 451system.cpu.rename.IdleCycles 13320782 # Number of cycles rename is idle 452system.cpu.rename.BlockCycles 5331170 # Number of cycles rename is blocking 453system.cpu.rename.serializeStallCycles 788978 # count of cycles rename stalled for serializing inst 454system.cpu.rename.RunCycles 32236803 # Number of cycles rename is running 455system.cpu.rename.UnblockCycles 13650784 # Number of cycles rename is unblocking 456system.cpu.rename.RenamedInsts 99206458 # Number of instructions processed by rename 457system.cpu.rename.SquashedInsts 984473 # Number of squashed instructions processed by rename 458system.cpu.rename.ROBFullEvents 3857341 # Number of times rename has blocked due to ROB full 459system.cpu.rename.IQFullEvents 63915 # Number of times rename has blocked due to IQ full 460system.cpu.rename.LQFullEvents 4307533 # Number of times rename has blocked due to LQ full 461system.cpu.rename.SQFullEvents 5353775 # Number of times rename has blocked due to SQ full 462system.cpu.rename.RenamedOperands 103928524 # Number of destination operands rename has renamed 463system.cpu.rename.RenameLookups 457724306 # Number of register rename lookups that rename has made 464system.cpu.rename.int_rename_lookups 115417327 # Number of integer rename lookups 465system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups 466system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed 467system.cpu.rename.UndoneMaps 10299298 # Number of HB maps that are undone due to squashing 468system.cpu.rename.serializingInsts 18661 # count of serializing insts renamed 469system.cpu.rename.tempSerializingInsts 18655 # count of temporary serializing insts renamed 470system.cpu.rename.skidInsts 12693692 # count of insts added to the skid buffer 471system.cpu.memDep0.insertedLoads 24322711 # Number of loads inserted to the mem dependence unit. 472system.cpu.memDep0.insertedStores 21993814 # Number of stores inserted to the mem dependence unit. 473system.cpu.memDep0.conflictingLoads 1396246 # Number of conflicting loads. 474system.cpu.memDep0.conflictingStores 2340033 # Number of conflicting stores. 475system.cpu.iq.iqInstsAdded 98168548 # Number of instructions added to the IQ (excludes non-spec) 476system.cpu.iq.iqNonSpecInstsAdded 34521 # Number of non-speculative instructions added to the IQ 477system.cpu.iq.iqInstsIssued 94889336 # Number of instructions issued 478system.cpu.iq.iqSquashedInstsIssued 694958 # Number of squashed instructions issued 479system.cpu.iq.iqSquashedInstsExamined 7520484 # Number of squashed instructions iterated over during squash; mainly for profiling 480system.cpu.iq.iqSquashedOperandsExamined 20257229 # Number of squashed operands that are examined and possibly removed from graph 481system.cpu.iq.iqSquashedNonSpecRemoved 735 # Number of squashed non-spec instructions that were removed 482system.cpu.iq.issued_per_cycle::samples 65820694 # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::mean 1.441634 # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::stdev 1.150001 # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::0 17560123 26.68% 26.68% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::1 17422684 26.47% 53.15% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::2 17103546 25.99% 79.13% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::3 11678791 17.74% 96.88% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::4 2054563 3.12% 100.00% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::5 987 0.00% 100.00% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::total 65820694 # Number of insts issued each cycle 499system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 500system.cpu.iq.fu_full::IntAlu 6715459 22.40% 22.40% # attempts to use FU when none available 501system.cpu.iq.fu_full::IntMult 39 0.00% 22.40% # attempts to use FU when none available 502system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available 503system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available 504system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available 505system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available 506system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available 507system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available 508system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available 529system.cpu.iq.fu_full::MemRead 11205581 37.37% 59.77% # attempts to use FU when none available 530system.cpu.iq.fu_full::MemWrite 12062957 40.23% 100.00% # attempts to use FU when none available 531system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 532system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 533system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 534system.cpu.iq.FU_type_0::IntAlu 49498174 52.16% 52.16% # Type of FU issued 535system.cpu.iq.FU_type_0::IntMult 89865 0.09% 52.26% # Type of FU issued 536system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.26% # Type of FU issued 537system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.26% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.26% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.26% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.26% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.26% # Type of FU issued 542system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.26% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.26% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.26% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.26% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.26% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.26% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.26% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.26% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.26% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.26% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.26% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.26% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.26% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.26% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.26% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.26% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.26% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.26% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.26% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.26% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.26% # Type of FU issued 563system.cpu.iq.FU_type_0::MemRead 24060336 25.36% 77.62% # Type of FU issued 564system.cpu.iq.FU_type_0::MemWrite 21240923 22.38% 100.00% # Type of FU issued 565system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 566system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 567system.cpu.iq.FU_type_0::total 94889336 # Type of FU issued 568system.cpu.iq.rate 1.423443 # Inst issue rate 569system.cpu.iq.fu_busy_cnt 29984036 # FU busy when requested 570system.cpu.iq.fu_busy_rate 0.315990 # FU busy rate (busy events/executed inst) 571system.cpu.iq.int_inst_queue_reads 286278153 # Number of integer instruction queue reads 572system.cpu.iq.int_inst_queue_writes 105734805 # Number of integer instruction queue writes 573system.cpu.iq.int_inst_queue_wakeup_accesses 93465836 # Number of integer instruction queue wakeup accesses 574system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads 575system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes 576system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses 577system.cpu.iq.int_alu_accesses 124873254 # Number of integer alu accesses 578system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses 579system.cpu.iew.lsq.thread0.forwLoads 1363649 # Number of loads that had data forwarded from stores 580system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 581system.cpu.iew.lsq.thread0.squashedLoads 1456449 # Number of loads squashed 582system.cpu.iew.lsq.thread0.ignoredResponses 2030 # Number of memory responses ignored because the instruction is squashed 583system.cpu.iew.lsq.thread0.memOrderViolation 11752 # Number of memory ordering violations 584system.cpu.iew.lsq.thread0.squashedStores 1438076 # Number of stores squashed 585system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 586system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 587system.cpu.iew.lsq.thread0.rescheduledLoads 138616 # Number of loads that were rescheduled 588system.cpu.iew.lsq.thread0.cacheBlocked 176709 # Number of times an access to memory failed due to the cache being blocked 589system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 590system.cpu.iew.iewSquashCycles 492177 # Number of cycles IEW is squashing 591system.cpu.iew.iewBlockCycles 621288 # Number of cycles IEW is blocking 592system.cpu.iew.iewUnblockCycles 454814 # Number of cycles IEW is unblocking 593system.cpu.iew.iewDispatchedInsts 98212928 # Number of instructions dispatched to IQ 594system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 595system.cpu.iew.iewDispLoadInsts 24322711 # Number of dispatched load instructions 596system.cpu.iew.iewDispStoreInsts 21993814 # Number of dispatched store instructions 597system.cpu.iew.iewDispNonSpecInsts 18601 # Number of dispatched non-speculative instructions 598system.cpu.iew.iewIQFullEvents 1642 # Number of times the IQ has become full, causing a stall 599system.cpu.iew.iewLSQFullEvents 450257 # Number of times the LSQ has become full, causing a stall 600system.cpu.iew.memOrderViolationEvents 11752 # Number of memory order violations 601system.cpu.iew.predictedTakenIncorrect 303335 # Number of branches that were predicted taken incorrectly 602system.cpu.iew.predictedNotTakenIncorrect 221647 # Number of branches that were predicted not taken incorrectly 603system.cpu.iew.branchMispredicts 524982 # Number of branch mispredicts detected at execute 604system.cpu.iew.iewExecutedInsts 93971179 # Number of executed instructions 605system.cpu.iew.iewExecLoadInsts 23753264 # Number of load instructions executed 606system.cpu.iew.iewExecSquashedInsts 918157 # Number of squashed instructions skipped in execute 607system.cpu.iew.exec_swp 0 # number of swp insts executed 608system.cpu.iew.exec_nop 9859 # number of nop insts executed 609system.cpu.iew.exec_refs 44736876 # number of memory reference insts executed 610system.cpu.iew.exec_branches 14252919 # Number of branches executed 611system.cpu.iew.exec_stores 20983612 # Number of stores executed 612system.cpu.iew.exec_rate 1.409670 # Inst execution rate 613system.cpu.iew.wb_sent 93587571 # cumulative count of insts sent to commit 614system.cpu.iew.wb_count 93465893 # cumulative count of insts written-back 615system.cpu.iew.wb_producers 44982416 # num instructions producing a value 616system.cpu.iew.wb_consumers 76564206 # num instructions consuming a value 617system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 618system.cpu.iew.wb_rate 1.402090 # insts written-back per cycle 619system.cpu.iew.wb_fanout 0.587512 # average fanout of values written-back 620system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 621system.cpu.commit.commitSquashedInsts 6539953 # The number of squashed insts skipped by commit 622system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 623system.cpu.commit.branchMispredicts 479186 # The number of times a branch was mispredicted 624system.cpu.commit.committed_per_cycle::samples 64761460 # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::mean 1.400341 # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::stdev 2.165093 # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::0 31172018 48.13% 48.13% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::1 16800427 25.94% 74.08% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::2 4337432 6.70% 80.77% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::3 4161423 6.43% 87.20% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::4 1935218 2.99% 90.19% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::5 1264756 1.95% 92.14% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::6 739046 1.14% 93.28% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::7 579471 0.89% 94.18% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::8 3771669 5.82% 100.00% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::total 64761460 # Number of insts commited each cycle 641system.cpu.commit.committedInsts 70913182 # Number of instructions committed 642system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed 643system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 644system.cpu.commit.refs 43422000 # Number of memory references committed 645system.cpu.commit.loads 22866262 # Number of loads committed 646system.cpu.commit.membars 15920 # Number of memory barriers committed 647system.cpu.commit.branches 13741486 # Number of branches committed 648system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 649system.cpu.commit.int_insts 81528487 # Number of committed integer instructions. 650system.cpu.commit.function_calls 1679850 # Number of function calls committed. 651system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 652system.cpu.commit.op_class_0::IntAlu 47186011 52.03% 52.03% # Class of committed instruction 653system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 654system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 655system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 656system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 657system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 658system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction 659system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction 660system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 681system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 682system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 683system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 684system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction 686system.cpu.commit.bw_lim_events 3771669 # number cycles where commit BW limit reached 687system.cpu.rob.rob_reads 158192582 # The number of ROB reads 688system.cpu.rob.rob_writes 195517129 # The number of ROB writes 689system.cpu.timesIdled 23763 # Number of times that the entire CPU went into an idle state and unscheduled itself 690system.cpu.idleCycles 841133 # Total number of cycles that the CPU has spent unscheduled due to idling 691system.cpu.committedInsts 70907630 # Number of Instructions Simulated 692system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated 693system.cpu.cpi 0.940122 # CPI: Cycles Per Instruction 694system.cpu.cpi_total 0.940122 # CPI: Total CPI of All Threads 695system.cpu.ipc 1.063692 # IPC: Instructions Per Cycle 696system.cpu.ipc_total 1.063692 # IPC: Total IPC of All Threads 697system.cpu.int_regfile_reads 102266688 # number of integer regfile reads 698system.cpu.int_regfile_writes 56794481 # number of integer regfile writes 699system.cpu.fp_regfile_reads 36 # number of floating regfile reads 700system.cpu.fp_regfile_writes 21 # number of floating regfile writes 701system.cpu.cc_regfile_reads 346084159 # number of cc regfile reads 702system.cpu.cc_regfile_writes 38805382 # number of cc regfile writes 703system.cpu.misc_regfile_reads 44209334 # number of misc regfile reads 704system.cpu.misc_regfile_writes 31840 # number of misc regfile writes 705system.cpu.dcache.tags.replacements 485106 # number of replacements 706system.cpu.dcache.tags.tagsinuse 510.740457 # Cycle average of tags in use 707system.cpu.dcache.tags.total_refs 40427935 # Total number of references to valid blocks. 708system.cpu.dcache.tags.sampled_refs 485618 # Sample count of references to valid blocks. 709system.cpu.dcache.tags.avg_refs 83.250487 # Average number of references to valid blocks. 710system.cpu.dcache.tags.warmup_cycle 152807000 # Cycle when the warmup percentage was hit. 711system.cpu.dcache.tags.occ_blocks::cpu.data 510.740457 # Average occupied blocks per requestor 712system.cpu.dcache.tags.occ_percent::cpu.data 0.997540 # Average percentage of cache occupancy 713system.cpu.dcache.tags.occ_percent::total 0.997540 # Average percentage of cache occupancy 714system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 715system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 716system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id 717system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 718system.cpu.dcache.tags.tag_accesses 84615616 # Number of tag accesses 719system.cpu.dcache.tags.data_accesses 84615616 # Number of data accesses 720system.cpu.dcache.ReadReq_hits::cpu.data 21501539 # number of ReadReq hits 721system.cpu.dcache.ReadReq_hits::total 21501539 # number of ReadReq hits 722system.cpu.dcache.WriteReq_hits::cpu.data 18833357 # number of WriteReq hits 723system.cpu.dcache.WriteReq_hits::total 18833357 # number of WriteReq hits 724system.cpu.dcache.SoftPFReq_hits::cpu.data 61715 # number of SoftPFReq hits 725system.cpu.dcache.SoftPFReq_hits::total 61715 # number of SoftPFReq hits 726system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits 727system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits 728system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 729system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 730system.cpu.dcache.demand_hits::cpu.data 40334896 # number of demand (read+write) hits 731system.cpu.dcache.demand_hits::total 40334896 # number of demand (read+write) hits 732system.cpu.dcache.overall_hits::cpu.data 40396611 # number of overall hits 733system.cpu.dcache.overall_hits::total 40396611 # number of overall hits 734system.cpu.dcache.ReadReq_misses::cpu.data 552871 # number of ReadReq misses 735system.cpu.dcache.ReadReq_misses::total 552871 # number of ReadReq misses 736system.cpu.dcache.WriteReq_misses::cpu.data 1016544 # number of WriteReq misses 737system.cpu.dcache.WriteReq_misses::total 1016544 # number of WriteReq misses 738system.cpu.dcache.SoftPFReq_misses::cpu.data 67128 # number of SoftPFReq misses 739system.cpu.dcache.SoftPFReq_misses::total 67128 # number of SoftPFReq misses 740system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses 741system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses 742system.cpu.dcache.demand_misses::cpu.data 1569415 # number of demand (read+write) misses 743system.cpu.dcache.demand_misses::total 1569415 # number of demand (read+write) misses 744system.cpu.dcache.overall_misses::cpu.data 1636543 # number of overall misses 745system.cpu.dcache.overall_misses::total 1636543 # number of overall misses 746system.cpu.dcache.ReadReq_miss_latency::cpu.data 9102953011 # number of ReadReq miss cycles 747system.cpu.dcache.ReadReq_miss_latency::total 9102953011 # number of ReadReq miss cycles 748system.cpu.dcache.WriteReq_miss_latency::cpu.data 14661434456 # number of WriteReq miss cycles 749system.cpu.dcache.WriteReq_miss_latency::total 14661434456 # number of WriteReq miss cycles 750system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5113500 # number of LoadLockedReq miss cycles 751system.cpu.dcache.LoadLockedReq_miss_latency::total 5113500 # number of LoadLockedReq miss cycles 752system.cpu.dcache.demand_miss_latency::cpu.data 23764387467 # number of demand (read+write) miss cycles 753system.cpu.dcache.demand_miss_latency::total 23764387467 # number of demand (read+write) miss cycles 754system.cpu.dcache.overall_miss_latency::cpu.data 23764387467 # number of overall miss cycles 755system.cpu.dcache.overall_miss_latency::total 23764387467 # number of overall miss cycles 756system.cpu.dcache.ReadReq_accesses::cpu.data 22054410 # number of ReadReq accesses(hits+misses) 757system.cpu.dcache.ReadReq_accesses::total 22054410 # number of ReadReq accesses(hits+misses) 758system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 759system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 760system.cpu.dcache.SoftPFReq_accesses::cpu.data 128843 # number of SoftPFReq accesses(hits+misses) 761system.cpu.dcache.SoftPFReq_accesses::total 128843 # number of SoftPFReq accesses(hits+misses) 762system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) 763system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) 764system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 765system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 766system.cpu.dcache.demand_accesses::cpu.data 41904311 # number of demand (read+write) accesses 767system.cpu.dcache.demand_accesses::total 41904311 # number of demand (read+write) accesses 768system.cpu.dcache.overall_accesses::cpu.data 42033154 # number of overall (read+write) accesses 769system.cpu.dcache.overall_accesses::total 42033154 # number of overall (read+write) accesses 770system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025069 # miss rate for ReadReq accesses 771system.cpu.dcache.ReadReq_miss_rate::total 0.025069 # miss rate for ReadReq accesses 772system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051212 # miss rate for WriteReq accesses 773system.cpu.dcache.WriteReq_miss_rate::total 0.051212 # miss rate for WriteReq accesses 774system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.521006 # miss rate for SoftPFReq accesses 775system.cpu.dcache.SoftPFReq_miss_rate::total 0.521006 # miss rate for SoftPFReq accesses 776system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses 777system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses 778system.cpu.dcache.demand_miss_rate::cpu.data 0.037452 # miss rate for demand accesses 779system.cpu.dcache.demand_miss_rate::total 0.037452 # miss rate for demand accesses 780system.cpu.dcache.overall_miss_rate::cpu.data 0.038935 # miss rate for overall accesses 781system.cpu.dcache.overall_miss_rate::total 0.038935 # miss rate for overall accesses 782system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16464.876998 # average ReadReq miss latency 783system.cpu.dcache.ReadReq_avg_miss_latency::total 16464.876998 # average ReadReq miss latency 784system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14422.823268 # average WriteReq miss latency 785system.cpu.dcache.WriteReq_avg_miss_latency::total 14422.823268 # average WriteReq miss latency 786system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9348.263254 # average LoadLockedReq miss latency 787system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9348.263254 # average LoadLockedReq miss latency 788system.cpu.dcache.demand_avg_miss_latency::cpu.data 15142.194682 # average overall miss latency 789system.cpu.dcache.demand_avg_miss_latency::total 15142.194682 # average overall miss latency 790system.cpu.dcache.overall_avg_miss_latency::cpu.data 14521.089557 # average overall miss latency 791system.cpu.dcache.overall_avg_miss_latency::total 14521.089557 # average overall miss latency 792system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked 793system.cpu.dcache.blocked_cycles::no_targets 3013610 # number of cycles access was blocked 794system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 795system.cpu.dcache.blocked::no_targets 128472 # number of cycles access was blocked 796system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.250000 # average number of cycles each access was blocked 797system.cpu.dcache.avg_blocked_cycles::no_targets 23.457329 # average number of cycles each access was blocked 798system.cpu.dcache.fast_writes 0 # number of fast writes performed 799system.cpu.dcache.cache_copies 0 # number of cache copies performed 800system.cpu.dcache.writebacks::writebacks 264409 # number of writebacks 801system.cpu.dcache.writebacks::total 264409 # number of writebacks 802system.cpu.dcache.ReadReq_mshr_hits::cpu.data 253375 # number of ReadReq MSHR hits 803system.cpu.dcache.ReadReq_mshr_hits::total 253375 # number of ReadReq MSHR hits 804system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868011 # number of WriteReq MSHR hits 805system.cpu.dcache.WriteReq_mshr_hits::total 868011 # number of WriteReq MSHR hits 806system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # number of LoadLockedReq MSHR hits 807system.cpu.dcache.LoadLockedReq_mshr_hits::total 547 # number of LoadLockedReq MSHR hits 808system.cpu.dcache.demand_mshr_hits::cpu.data 1121386 # number of demand (read+write) MSHR hits 809system.cpu.dcache.demand_mshr_hits::total 1121386 # number of demand (read+write) MSHR hits 810system.cpu.dcache.overall_mshr_hits::cpu.data 1121386 # number of overall MSHR hits 811system.cpu.dcache.overall_mshr_hits::total 1121386 # number of overall MSHR hits 812system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299496 # number of ReadReq MSHR misses 813system.cpu.dcache.ReadReq_mshr_misses::total 299496 # number of ReadReq MSHR misses 814system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses 815system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses 816system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37600 # number of SoftPFReq MSHR misses 817system.cpu.dcache.SoftPFReq_mshr_misses::total 37600 # number of SoftPFReq MSHR misses 818system.cpu.dcache.demand_mshr_misses::cpu.data 448029 # number of demand (read+write) MSHR misses 819system.cpu.dcache.demand_mshr_misses::total 448029 # number of demand (read+write) MSHR misses 820system.cpu.dcache.overall_mshr_misses::cpu.data 485629 # number of overall MSHR misses 821system.cpu.dcache.overall_mshr_misses::total 485629 # number of overall MSHR misses 822system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3035888114 # number of ReadReq MSHR miss cycles 823system.cpu.dcache.ReadReq_mshr_miss_latency::total 3035888114 # number of ReadReq MSHR miss cycles 824system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279411901 # number of WriteReq MSHR miss cycles 825system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279411901 # number of WriteReq MSHR miss cycles 826system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2033283784 # number of SoftPFReq MSHR miss cycles 827system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2033283784 # number of SoftPFReq MSHR miss cycles 828system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5315300015 # number of demand (read+write) MSHR miss cycles 829system.cpu.dcache.demand_mshr_miss_latency::total 5315300015 # number of demand (read+write) MSHR miss cycles 830system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7348583799 # number of overall MSHR miss cycles 831system.cpu.dcache.overall_mshr_miss_latency::total 7348583799 # number of overall MSHR miss cycles 832system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013580 # mshr miss rate for ReadReq accesses 833system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013580 # mshr miss rate for ReadReq accesses 834system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses 835system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses 836system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291828 # mshr miss rate for SoftPFReq accesses 837system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291828 # mshr miss rate for SoftPFReq accesses 838system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010692 # mshr miss rate for demand accesses 839system.cpu.dcache.demand_mshr_miss_rate::total 0.010692 # mshr miss rate for demand accesses 840system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011553 # mshr miss rate for overall accesses 841system.cpu.dcache.overall_mshr_miss_rate::total 0.011553 # mshr miss rate for overall accesses 842system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10136.656630 # average ReadReq mshr miss latency 843system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10136.656630 # average ReadReq mshr miss latency 844system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15346.164832 # average WriteReq mshr miss latency 845system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15346.164832 # average WriteReq mshr miss latency 846system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54076.696383 # average SoftPFReq mshr miss latency 847system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54076.696383 # average SoftPFReq mshr miss latency 848system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11863.740997 # average overall mshr miss latency 849system.cpu.dcache.demand_avg_mshr_miss_latency::total 11863.740997 # average overall mshr miss latency 850system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15132.094251 # average overall mshr miss latency 851system.cpu.dcache.overall_avg_mshr_miss_latency::total 15132.094251 # average overall mshr miss latency 852system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 853system.cpu.icache.tags.replacements 322771 # number of replacements 854system.cpu.icache.tags.tagsinuse 510.304013 # Cycle average of tags in use 855system.cpu.icache.tags.total_refs 22435446 # Total number of references to valid blocks. 856system.cpu.icache.tags.sampled_refs 323283 # Sample count of references to valid blocks. 857system.cpu.icache.tags.avg_refs 69.398781 # Average number of references to valid blocks. 858system.cpu.icache.tags.warmup_cycle 1099609250 # Cycle when the warmup percentage was hit. 859system.cpu.icache.tags.occ_blocks::cpu.inst 510.304013 # Average occupied blocks per requestor 860system.cpu.icache.tags.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy 861system.cpu.icache.tags.occ_percent::total 0.996688 # Average percentage of cache occupancy 862system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 863system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id 864system.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id 865system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 866system.cpu.icache.tags.age_task_id_blocks_1024::3 354 # Occupied blocks per task id 867system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 868system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 869system.cpu.icache.tags.tag_accesses 45859770 # Number of tag accesses 870system.cpu.icache.tags.data_accesses 45859770 # Number of data accesses 871system.cpu.icache.ReadReq_hits::cpu.inst 22435446 # number of ReadReq hits 872system.cpu.icache.ReadReq_hits::total 22435446 # number of ReadReq hits 873system.cpu.icache.demand_hits::cpu.inst 22435446 # number of demand (read+write) hits 874system.cpu.icache.demand_hits::total 22435446 # number of demand (read+write) hits 875system.cpu.icache.overall_hits::cpu.inst 22435446 # number of overall hits 876system.cpu.icache.overall_hits::total 22435446 # number of overall hits 877system.cpu.icache.ReadReq_misses::cpu.inst 332792 # number of ReadReq misses 878system.cpu.icache.ReadReq_misses::total 332792 # number of ReadReq misses 879system.cpu.icache.demand_misses::cpu.inst 332792 # number of demand (read+write) misses 880system.cpu.icache.demand_misses::total 332792 # number of demand (read+write) misses 881system.cpu.icache.overall_misses::cpu.inst 332792 # number of overall misses 882system.cpu.icache.overall_misses::total 332792 # number of overall misses 883system.cpu.icache.ReadReq_miss_latency::cpu.inst 3372368098 # number of ReadReq miss cycles 884system.cpu.icache.ReadReq_miss_latency::total 3372368098 # number of ReadReq miss cycles 885system.cpu.icache.demand_miss_latency::cpu.inst 3372368098 # number of demand (read+write) miss cycles 886system.cpu.icache.demand_miss_latency::total 3372368098 # number of demand (read+write) miss cycles 887system.cpu.icache.overall_miss_latency::cpu.inst 3372368098 # number of overall miss cycles 888system.cpu.icache.overall_miss_latency::total 3372368098 # number of overall miss cycles 889system.cpu.icache.ReadReq_accesses::cpu.inst 22768238 # number of ReadReq accesses(hits+misses) 890system.cpu.icache.ReadReq_accesses::total 22768238 # number of ReadReq accesses(hits+misses) 891system.cpu.icache.demand_accesses::cpu.inst 22768238 # number of demand (read+write) accesses 892system.cpu.icache.demand_accesses::total 22768238 # number of demand (read+write) accesses 893system.cpu.icache.overall_accesses::cpu.inst 22768238 # number of overall (read+write) accesses 894system.cpu.icache.overall_accesses::total 22768238 # number of overall (read+write) accesses 895system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014617 # miss rate for ReadReq accesses 896system.cpu.icache.ReadReq_miss_rate::total 0.014617 # miss rate for ReadReq accesses 897system.cpu.icache.demand_miss_rate::cpu.inst 0.014617 # miss rate for demand accesses 898system.cpu.icache.demand_miss_rate::total 0.014617 # miss rate for demand accesses 899system.cpu.icache.overall_miss_rate::cpu.inst 0.014617 # miss rate for overall accesses 900system.cpu.icache.overall_miss_rate::total 0.014617 # miss rate for overall accesses 901system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10133.561197 # average ReadReq miss latency 902system.cpu.icache.ReadReq_avg_miss_latency::total 10133.561197 # average ReadReq miss latency 903system.cpu.icache.demand_avg_miss_latency::cpu.inst 10133.561197 # average overall miss latency 904system.cpu.icache.demand_avg_miss_latency::total 10133.561197 # average overall miss latency 905system.cpu.icache.overall_avg_miss_latency::cpu.inst 10133.561197 # average overall miss latency 906system.cpu.icache.overall_avg_miss_latency::total 10133.561197 # average overall miss latency 907system.cpu.icache.blocked_cycles::no_mshrs 259166 # number of cycles access was blocked 908system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked 909system.cpu.icache.blocked::no_mshrs 14826 # number of cycles access was blocked 910system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 911system.cpu.icache.avg_blocked_cycles::no_mshrs 17.480507 # average number of cycles each access was blocked 912system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked 913system.cpu.icache.fast_writes 0 # number of fast writes performed 914system.cpu.icache.cache_copies 0 # number of cache copies performed 915system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9498 # number of ReadReq MSHR hits 916system.cpu.icache.ReadReq_mshr_hits::total 9498 # number of ReadReq MSHR hits 917system.cpu.icache.demand_mshr_hits::cpu.inst 9498 # number of demand (read+write) MSHR hits 918system.cpu.icache.demand_mshr_hits::total 9498 # number of demand (read+write) MSHR hits 919system.cpu.icache.overall_mshr_hits::cpu.inst 9498 # number of overall MSHR hits 920system.cpu.icache.overall_mshr_hits::total 9498 # number of overall MSHR hits 921system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323294 # number of ReadReq MSHR misses 922system.cpu.icache.ReadReq_mshr_misses::total 323294 # number of ReadReq MSHR misses 923system.cpu.icache.demand_mshr_misses::cpu.inst 323294 # number of demand (read+write) MSHR misses 924system.cpu.icache.demand_mshr_misses::total 323294 # number of demand (read+write) MSHR misses 925system.cpu.icache.overall_mshr_misses::cpu.inst 323294 # number of overall MSHR misses 926system.cpu.icache.overall_mshr_misses::total 323294 # number of overall MSHR misses 927system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2922927754 # number of ReadReq MSHR miss cycles 928system.cpu.icache.ReadReq_mshr_miss_latency::total 2922927754 # number of ReadReq MSHR miss cycles 929system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2922927754 # number of demand (read+write) MSHR miss cycles 930system.cpu.icache.demand_mshr_miss_latency::total 2922927754 # number of demand (read+write) MSHR miss cycles 931system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2922927754 # number of overall MSHR miss cycles 932system.cpu.icache.overall_mshr_miss_latency::total 2922927754 # number of overall MSHR miss cycles 933system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014199 # mshr miss rate for ReadReq accesses 934system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014199 # mshr miss rate for ReadReq accesses 935system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014199 # mshr miss rate for demand accesses 936system.cpu.icache.demand_mshr_miss_rate::total 0.014199 # mshr miss rate for demand accesses 937system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014199 # mshr miss rate for overall accesses 938system.cpu.icache.overall_mshr_miss_rate::total 0.014199 # mshr miss rate for overall accesses 939system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9041.082587 # average ReadReq mshr miss latency 940system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9041.082587 # average ReadReq mshr miss latency 941system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9041.082587 # average overall mshr miss latency 942system.cpu.icache.demand_avg_mshr_miss_latency::total 9041.082587 # average overall mshr miss latency 943system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9041.082587 # average overall mshr miss latency 944system.cpu.icache.overall_avg_mshr_miss_latency::total 9041.082587 # average overall mshr miss latency 945system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 946system.cpu.l2cache.prefetcher.num_hwpf_issued 824420 # number of hwpf issued 947system.cpu.l2cache.prefetcher.pfIdentified 826170 # number of prefetch candidates identified 948system.cpu.l2cache.prefetcher.pfBufferHit 1539 # number of redundant prefetches already in prefetch queue 949system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 950system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 951system.cpu.l2cache.prefetcher.pfSpanPage 78694 # number of prefetches not generated due to page crossing 952system.cpu.l2cache.tags.replacements 129309 # number of replacements 953system.cpu.l2cache.tags.tagsinuse 16078.989093 # Cycle average of tags in use 954system.cpu.l2cache.tags.total_refs 872580 # Total number of references to valid blocks. 955system.cpu.l2cache.tags.sampled_refs 145594 # Sample count of references to valid blocks. 956system.cpu.l2cache.tags.avg_refs 5.993241 # Average number of references to valid blocks. 957system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 958system.cpu.l2cache.tags.occ_blocks::writebacks 12596.793225 # Average occupied blocks per requestor 959system.cpu.l2cache.tags.occ_blocks::cpu.inst 1430.956994 # Average occupied blocks per requestor 960system.cpu.l2cache.tags.occ_blocks::cpu.data 1951.680185 # Average occupied blocks per requestor 961system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 99.558690 # Average occupied blocks per requestor 962system.cpu.l2cache.tags.occ_percent::writebacks 0.768847 # Average percentage of cache occupancy 963system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087339 # Average percentage of cache occupancy 964system.cpu.l2cache.tags.occ_percent::cpu.data 0.119121 # Average percentage of cache occupancy 965system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006077 # Average percentage of cache occupancy 966system.cpu.l2cache.tags.occ_percent::total 0.981384 # Average percentage of cache occupancy 967system.cpu.l2cache.tags.occ_task_id_blocks::1022 24 # Occupied blocks per task id 968system.cpu.l2cache.tags.occ_task_id_blocks::1024 16261 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 970system.cpu.l2cache.tags.age_task_id_blocks_1022::3 13 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id 973system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2623 # Occupied blocks per task id 974system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11971 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1024::3 617 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1024::4 894 # Occupied blocks per task id 977system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001465 # Percentage of cache occupancy per task id 978system.cpu.l2cache.tags.occ_task_id_percent::1024 0.992493 # Percentage of cache occupancy per task id 979system.cpu.l2cache.tags.tag_accesses 17467290 # Number of tag accesses 980system.cpu.l2cache.tags.data_accesses 17467290 # Number of data accesses 981system.cpu.l2cache.ReadReq_hits::cpu.inst 314129 # number of ReadReq hits 982system.cpu.l2cache.ReadReq_hits::cpu.data 305935 # number of ReadReq hits 983system.cpu.l2cache.ReadReq_hits::total 620064 # number of ReadReq hits 984system.cpu.l2cache.Writeback_hits::writebacks 264409 # number of Writeback hits 985system.cpu.l2cache.Writeback_hits::total 264409 # number of Writeback hits 986system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 987system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 988system.cpu.l2cache.ReadExReq_hits::cpu.data 137264 # number of ReadExReq hits 989system.cpu.l2cache.ReadExReq_hits::total 137264 # number of ReadExReq hits 990system.cpu.l2cache.demand_hits::cpu.inst 314129 # number of demand (read+write) hits 991system.cpu.l2cache.demand_hits::cpu.data 443199 # number of demand (read+write) hits 992system.cpu.l2cache.demand_hits::total 757328 # number of demand (read+write) hits 993system.cpu.l2cache.overall_hits::cpu.inst 314129 # number of overall hits 994system.cpu.l2cache.overall_hits::cpu.data 443199 # number of overall hits 995system.cpu.l2cache.overall_hits::total 757328 # number of overall hits 996system.cpu.l2cache.ReadReq_misses::cpu.inst 9153 # number of ReadReq misses 997system.cpu.l2cache.ReadReq_misses::cpu.data 31112 # number of ReadReq misses 998system.cpu.l2cache.ReadReq_misses::total 40265 # number of ReadReq misses 999system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 1000system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 1001system.cpu.l2cache.ReadExReq_misses::cpu.data 11307 # number of ReadExReq misses 1002system.cpu.l2cache.ReadExReq_misses::total 11307 # number of ReadExReq misses 1003system.cpu.l2cache.demand_misses::cpu.inst 9153 # number of demand (read+write) misses 1004system.cpu.l2cache.demand_misses::cpu.data 42419 # number of demand (read+write) misses 1005system.cpu.l2cache.demand_misses::total 51572 # number of demand (read+write) misses 1006system.cpu.l2cache.overall_misses::cpu.inst 9153 # number of overall misses 1007system.cpu.l2cache.overall_misses::cpu.data 42419 # number of overall misses 1008system.cpu.l2cache.overall_misses::total 51572 # number of overall misses 1009system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 716537990 # number of ReadReq miss cycles 1010system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2723567713 # number of ReadReq miss cycles 1011system.cpu.l2cache.ReadReq_miss_latency::total 3440105703 # number of ReadReq miss cycles 1012system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1235437442 # number of ReadExReq miss cycles 1013system.cpu.l2cache.ReadExReq_miss_latency::total 1235437442 # number of ReadExReq miss cycles 1014system.cpu.l2cache.demand_miss_latency::cpu.inst 716537990 # number of demand (read+write) miss cycles 1015system.cpu.l2cache.demand_miss_latency::cpu.data 3959005155 # number of demand (read+write) miss cycles 1016system.cpu.l2cache.demand_miss_latency::total 4675543145 # number of demand (read+write) miss cycles 1017system.cpu.l2cache.overall_miss_latency::cpu.inst 716537990 # number of overall miss cycles 1018system.cpu.l2cache.overall_miss_latency::cpu.data 3959005155 # number of overall miss cycles 1019system.cpu.l2cache.overall_miss_latency::total 4675543145 # number of overall miss cycles 1020system.cpu.l2cache.ReadReq_accesses::cpu.inst 323282 # number of ReadReq accesses(hits+misses) 1021system.cpu.l2cache.ReadReq_accesses::cpu.data 337047 # number of ReadReq accesses(hits+misses) 1022system.cpu.l2cache.ReadReq_accesses::total 660329 # number of ReadReq accesses(hits+misses) 1023system.cpu.l2cache.Writeback_accesses::writebacks 264409 # number of Writeback accesses(hits+misses) 1024system.cpu.l2cache.Writeback_accesses::total 264409 # number of Writeback accesses(hits+misses) 1025system.cpu.l2cache.UpgradeReq_accesses::cpu.data 11 # number of UpgradeReq accesses(hits+misses) 1026system.cpu.l2cache.UpgradeReq_accesses::total 11 # number of UpgradeReq accesses(hits+misses) 1027system.cpu.l2cache.ReadExReq_accesses::cpu.data 148571 # number of ReadExReq accesses(hits+misses) 1028system.cpu.l2cache.ReadExReq_accesses::total 148571 # number of ReadExReq accesses(hits+misses) 1029system.cpu.l2cache.demand_accesses::cpu.inst 323282 # number of demand (read+write) accesses 1030system.cpu.l2cache.demand_accesses::cpu.data 485618 # number of demand (read+write) accesses 1031system.cpu.l2cache.demand_accesses::total 808900 # number of demand (read+write) accesses 1032system.cpu.l2cache.overall_accesses::cpu.inst 323282 # number of overall (read+write) accesses 1033system.cpu.l2cache.overall_accesses::cpu.data 485618 # number of overall (read+write) accesses 1034system.cpu.l2cache.overall_accesses::total 808900 # number of overall (read+write) accesses 1035system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.028313 # miss rate for ReadReq accesses 1036system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.092308 # miss rate for ReadReq accesses 1037system.cpu.l2cache.ReadReq_miss_rate::total 0.060977 # miss rate for ReadReq accesses 1038system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.545455 # miss rate for UpgradeReq accesses 1039system.cpu.l2cache.UpgradeReq_miss_rate::total 0.545455 # miss rate for UpgradeReq accesses 1040system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076105 # miss rate for ReadExReq accesses 1041system.cpu.l2cache.ReadExReq_miss_rate::total 0.076105 # miss rate for ReadExReq accesses 1042system.cpu.l2cache.demand_miss_rate::cpu.inst 0.028313 # miss rate for demand accesses 1043system.cpu.l2cache.demand_miss_rate::cpu.data 0.087351 # miss rate for demand accesses 1044system.cpu.l2cache.demand_miss_rate::total 0.063756 # miss rate for demand accesses 1045system.cpu.l2cache.overall_miss_rate::cpu.inst 0.028313 # miss rate for overall accesses 1046system.cpu.l2cache.overall_miss_rate::cpu.data 0.087351 # miss rate for overall accesses 1047system.cpu.l2cache.overall_miss_rate::total 0.063756 # miss rate for overall accesses 1048system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78284.495794 # average ReadReq miss latency 1049system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87540.746754 # average ReadReq miss latency 1050system.cpu.l2cache.ReadReq_avg_miss_latency::total 85436.624935 # average ReadReq miss latency 1051system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109263.061997 # average ReadExReq miss latency 1052system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109263.061997 # average ReadExReq miss latency 1053system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78284.495794 # average overall miss latency 1054system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93330.940263 # average overall miss latency 1055system.cpu.l2cache.demand_avg_miss_latency::total 90660.496878 # average overall miss latency 1056system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78284.495794 # average overall miss latency 1057system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93330.940263 # average overall miss latency 1058system.cpu.l2cache.overall_avg_miss_latency::total 90660.496878 # average overall miss latency 1059system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1060system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1061system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1062system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1063system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1064system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1065system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1066system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1067system.cpu.l2cache.writebacks::writebacks 97752 # number of writebacks 1068system.cpu.l2cache.writebacks::total 97752 # number of writebacks 1069system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 36 # number of ReadReq MSHR hits 1070system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 124 # number of ReadReq MSHR hits 1071system.cpu.l2cache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits 1072system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3154 # number of ReadExReq MSHR hits 1073system.cpu.l2cache.ReadExReq_mshr_hits::total 3154 # number of ReadExReq MSHR hits 1074system.cpu.l2cache.demand_mshr_hits::cpu.inst 36 # number of demand (read+write) MSHR hits 1075system.cpu.l2cache.demand_mshr_hits::cpu.data 3278 # number of demand (read+write) MSHR hits 1076system.cpu.l2cache.demand_mshr_hits::total 3314 # number of demand (read+write) MSHR hits 1077system.cpu.l2cache.overall_mshr_hits::cpu.inst 36 # number of overall MSHR hits 1078system.cpu.l2cache.overall_mshr_hits::cpu.data 3278 # number of overall MSHR hits 1079system.cpu.l2cache.overall_mshr_hits::total 3314 # number of overall MSHR hits 1080system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9117 # number of ReadReq MSHR misses 1081system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30988 # number of ReadReq MSHR misses 1082system.cpu.l2cache.ReadReq_mshr_misses::total 40105 # number of ReadReq MSHR misses 1083system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112705 # number of HardPFReq MSHR misses 1084system.cpu.l2cache.HardPFReq_mshr_misses::total 112705 # number of HardPFReq MSHR misses 1085system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 1086system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 1087system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8153 # number of ReadExReq MSHR misses 1088system.cpu.l2cache.ReadExReq_mshr_misses::total 8153 # number of ReadExReq MSHR misses 1089system.cpu.l2cache.demand_mshr_misses::cpu.inst 9117 # number of demand (read+write) MSHR misses 1090system.cpu.l2cache.demand_mshr_misses::cpu.data 39141 # number of demand (read+write) MSHR misses 1091system.cpu.l2cache.demand_mshr_misses::total 48258 # number of demand (read+write) MSHR misses 1092system.cpu.l2cache.overall_mshr_misses::cpu.inst 9117 # number of overall MSHR misses 1093system.cpu.l2cache.overall_mshr_misses::cpu.data 39141 # number of overall MSHR misses 1094system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112705 # number of overall MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::total 160963 # number of overall MSHR misses 1096system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 636175260 # number of ReadReq MSHR miss cycles 1097system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2451921294 # number of ReadReq MSHR miss cycles 1098system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3088096554 # number of ReadReq MSHR miss cycles 1099system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10874977234 # number of HardPFReq MSHR miss cycles 1100system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10874977234 # number of HardPFReq MSHR miss cycles 1101system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 82006 # number of UpgradeReq MSHR miss cycles 1102system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 82006 # number of UpgradeReq MSHR miss cycles 1103system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 605818037 # number of ReadExReq MSHR miss cycles 1104system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 605818037 # number of ReadExReq MSHR miss cycles 1105system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 636175260 # number of demand (read+write) MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3057739331 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::total 3693914591 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 636175260 # number of overall MSHR miss cycles 1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3057739331 # number of overall MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10874977234 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::total 14568891825 # number of overall MSHR miss cycles 1112system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028201 # mshr miss rate for ReadReq accesses 1113system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.091940 # mshr miss rate for ReadReq accesses 1114system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.060735 # mshr miss rate for ReadReq accesses 1115system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1116system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1117system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses 1118system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses 1119system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.054876 # mshr miss rate for ReadExReq accesses 1120system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.054876 # mshr miss rate for ReadExReq accesses 1121system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028201 # mshr miss rate for demand accesses 1122system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080600 # mshr miss rate for demand accesses 1123system.cpu.l2cache.demand_mshr_miss_rate::total 0.059659 # mshr miss rate for demand accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028201 # mshr miss rate for overall accesses 1125system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080600 # mshr miss rate for overall accesses 1126system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1127system.cpu.l2cache.overall_mshr_miss_rate::total 0.198990 # mshr miss rate for overall accesses 1128system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69779.012833 # average ReadReq mshr miss latency 1129system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79124.864270 # average ReadReq mshr miss latency 1130system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77000.288094 # average ReadReq mshr miss latency 1131system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919 # average HardPFReq mshr miss latency 1132system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96490.636919 # average HardPFReq mshr miss latency 1133system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13667.666667 # average UpgradeReq mshr miss latency 1134system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13667.666667 # average UpgradeReq mshr miss latency 1135system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74306.149516 # average ReadExReq mshr miss latency 1136system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74306.149516 # average ReadExReq mshr miss latency 1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69779.012833 # average overall mshr miss latency 1138system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78121.134641 # average overall mshr miss latency 1139system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76545.123938 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69779.012833 # average overall mshr miss latency 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78121.134641 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919 # average overall mshr miss latency 1143system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90510.811957 # average overall mshr miss latency 1144system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1145system.cpu.toL2Bus.trans_dist::ReadReq 660341 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::ReadResp 660341 # Transaction distribution 1147system.cpu.toL2Bus.trans_dist::Writeback 264409 # Transaction distribution 1148system.cpu.toL2Bus.trans_dist::HardPFReq 151292 # Transaction distribution 1149system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::ReadExReq 148571 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::ReadExResp 148571 # Transaction distribution 1153system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646576 # Packet count per connected master and slave (bytes) 1154system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1235667 # Packet count per connected master and slave (bytes) 1155system.cpu.toL2Bus.pkt_count::total 1882243 # Packet count per connected master and slave (bytes) 1156system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20690048 # Cumulative packet size per connected master and slave (bytes) 1157system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48001728 # Cumulative packet size per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_size::total 68691776 # Cumulative packet size per connected master and slave (bytes) 1159system.cpu.toL2Bus.snoops 151304 # Total snoops (count) 1160system.cpu.toL2Bus.snoop_fanout::samples 1224624 # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::mean 1.123542 # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::stdev 0.329058 # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::1 1073332 87.65% 87.65% # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::2 151292 12.35% 100.00% # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::total 1224624 # Request fanout histogram 1171system.cpu.toL2Bus.reqLayer0.occupancy 801075000 # Layer occupancy (ticks) 1172system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) 1173system.cpu.toL2Bus.respLayer0.occupancy 486570693 # Layer occupancy (ticks) 1174system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 1175system.cpu.toL2Bus.respLayer1.occupancy 734618165 # Layer occupancy (ticks) 1176system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) 1177system.membus.trans_dist::ReadReq 137030 # Transaction distribution 1178system.membus.trans_dist::ReadResp 137030 # Transaction distribution 1179system.membus.trans_dist::Writeback 97752 # Transaction distribution 1180system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1181system.membus.trans_dist::UpgradeResp 6 # Transaction distribution 1182system.membus.trans_dist::ReadExReq 8153 # Transaction distribution 1183system.membus.trans_dist::ReadExResp 8153 # Transaction distribution 1184system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388130 # Packet count per connected master and slave (bytes) 1185system.membus.pkt_count::total 388130 # Packet count per connected master and slave (bytes) 1186system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15547840 # Cumulative packet size per connected master and slave (bytes) 1187system.membus.pkt_size::total 15547840 # Cumulative packet size per connected master and slave (bytes) 1188system.membus.snoops 0 # Total snoops (count) 1189system.membus.snoop_fanout::samples 242941 # Request fanout histogram 1190system.membus.snoop_fanout::mean 0 # Request fanout histogram 1191system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1192system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1193system.membus.snoop_fanout::0 242941 100.00% 100.00% # Request fanout histogram 1194system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1195system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1196system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1197system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1198system.membus.snoop_fanout::total 242941 # Request fanout histogram 1199system.membus.reqLayer0.occupancy 691321050 # Layer occupancy (ticks) 1200system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) 1201system.membus.respLayer1.occupancy 757153835 # Layer occupancy (ticks) 1202system.membus.respLayer1.utilization 2.3 # Layer utilization (%) 1203 1204---------- End Simulation Statistics ---------- 1205