config.ini revision 8911:4da2ea94319f
12SN/A[root] 21762SN/Atype=Root 32SN/Achildren=system 42SN/Afull_system=false 52SN/Atime_sync_enable=false 62SN/Atime_sync_period=100000000000 72SN/Atime_sync_spin_threshold=100000000 82SN/A 92SN/A[system] 102SN/Atype=System 112SN/Achildren=cpu membus physmem 122SN/Aboot_osflags=a 132SN/Ainit_param=0 142SN/Akernel= 152SN/Aload_addr_mask=1099511627775 162SN/Amem_mode=atomic 172SN/Amemories=system.physmem 182SN/Anum_work_ids=16 192SN/Aphysmem=system.physmem 202SN/Areadfile= 212SN/Asymbolfile= 222SN/Awork_begin_ckpt_count=0 232SN/Awork_begin_cpu_id_exit=-1 242SN/Awork_begin_exit_count=0 252SN/Awork_cpus_ckpt_count=0 262SN/Awork_end_ckpt_count=0 272665Ssaidi@eecs.umich.eduwork_end_exit_count=0 282665Ssaidi@eecs.umich.eduwork_item_id=-1 292665Ssaidi@eecs.umich.edusystem_port=system.membus.slave[0] 302SN/A 312SN/A[system.cpu] 321717SN/Atype=DerivO3CPU 331717SN/Achildren=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 342SN/ABTBEntries=4096 352SN/ABTBTagSize=16 362SN/ALFSTSize=1024 37707SN/ALQEntries=32 381858SN/ALSQCheckLoads=true 3956SN/ALSQDepCheckShift=4 402856Srdreslin@umich.eduRASSize=16 412109SN/ASQEntries=32 422SN/ASSITSize=1024 433520Sgblack@eecs.umich.eduactivity=0 443520Sgblack@eecs.umich.edubackComSize=5 453520Sgblack@eecs.umich.educachePorts=200 463520Sgblack@eecs.umich.educhecker=Null 472190SN/AchoiceCtrBits=2 482315SN/AchoicePredictorSize=8192 492680Sktlim@umich.educlock=500 502SN/AcommitToDecodeDelay=1 512856Srdreslin@umich.educommitToFetchDelay=1 522SN/AcommitToIEWDelay=1 532356SN/AcommitToRenameDelay=1 542356SN/AcommitWidth=8 552356SN/Acpu_id=0 562356SN/AdecodeToFetchDelay=1 572356SN/AdecodeToRenameDelay=1 582356SN/AdecodeWidth=8 592356SN/Adefer_registration=false 602356SN/AdispatchWidth=8 613126Sktlim@umich.edudo_checkpoint_insts=true 622356SN/Ado_quiesce=true 632356SN/Ado_statistics_insts=true 642356SN/Adtb=system.cpu.dtb 652356SN/AfetchToDecodeDelay=1 662356SN/AfetchTrapLatency=1 672356SN/AfetchWidth=8 682856Srdreslin@umich.eduforwardComSize=5 692SN/AfuPool=system.cpu.fuPool 701634SN/Afunction_trace=false 711634SN/Afunction_trace_start=0 721695SN/AglobalCtrBits=2 731634SN/AglobalHistoryBits=13 741634SN/AglobalPredictorSize=8192 752359SN/AiewToCommitDelay=1 761695SN/AiewToDecodeDelay=1 771695SN/AiewToFetchDelay=1 781695SN/AiewToRenameDelay=1 791634SN/AinstShiftAmt=2 803495Sktlim@umich.eduinterrupts=system.cpu.interrupts 813495Sktlim@umich.eduissueToExecuteDelay=1 823495Sktlim@umich.eduissueWidth=8 833495Sktlim@umich.eduitb=system.cpu.itb 843495Sktlim@umich.edulocalCtrBits=2 853495Sktlim@umich.edulocalHistoryBits=11 863495Sktlim@umich.edulocalHistoryTableSize=2048 873495Sktlim@umich.edulocalPredictorSize=2048 883495Sktlim@umich.edumax_insts_all_threads=0 893495Sktlim@umich.edumax_insts_any_thread=0 903495Sktlim@umich.edumax_loads_all_threads=0 913495Sktlim@umich.edumax_loads_any_thread=0 923495Sktlim@umich.eduneedsTSO=false 933495Sktlim@umich.edunumIQEntries=64 941858SN/AnumPhysFloatRegs=256 952SN/AnumPhysIntRegs=256 963520Sgblack@eecs.umich.edunumROBEntries=192 973520Sgblack@eecs.umich.edunumRobs=1 983520Sgblack@eecs.umich.edunumThreads=1 992SN/Aphase=0 1002SN/ApredType=tournament 1012SN/Aprofile=0 1022SN/Aprogress_interval=0 1032SN/ArenameToDecodeDelay=1 1041133SN/ArenameToFetchDelay=1 1052SN/ArenameToIEWDelay=2 1063521Sgblack@eecs.umich.edurenameToROBDelay=1 1073521Sgblack@eecs.umich.edurenameWidth=8 1081917SN/AsmtCommitPolicy=RoundRobin 1091917SN/AsmtFetchPolicy=SingleThread 1101917SN/AsmtIQPolicy=Partitioned 1111917SN/AsmtIQThreshold=100 1121917SN/AsmtLSQPolicy=Partitioned 1131917SN/AsmtLSQThreshold=100 1141917SN/AsmtNumFetchingThreads=1 1151917SN/AsmtROBPolicy=Partitioned 1161917SN/AsmtROBThreshold=100 1171917SN/AsquashWidth=8 1181917SN/Astore_set_clear_period=250000 1191917SN/Asystem=system 1202SN/Atracer=system.cpu.tracer 1212SN/AtrapLatency=13 1222SN/AwbDepth=1 1232680Sktlim@umich.eduwbWidth=8 1242SN/Aworkload=system.cpu.workload 1252SN/Adcache_port=system.cpu.dcache.cpu_side 126393SN/Aicache_port=system.cpu.icache.cpu_side 127393SN/A 128393SN/A[system.cpu.dcache] 129393SN/Atype=BaseCache 130393SN/Aaddr_ranges=0:18446744073709551615 131393SN/Aassoc=2 132393SN/Ablock_size=64 133393SN/Aforward_snoops=true 134393SN/Ahash_delay=1 135393SN/Ais_top_level=true 136393SN/Alatency=1000 137393SN/Amax_miss_count=0 138393SN/Amshrs=10 139393SN/Aprefetch_on_access=false 1402SN/Aprefetcher=Null 1412SN/AprioritizeRequests=false 1421400SN/Arepl=Null 1431400SN/Asize=262144 1441400SN/Asubblock_size=0 1451400SN/Asystem=system 1461400SN/Atgts_per_mshr=20 1471400SN/Atrace_addr=0 1481400SN/Atwo_queue=false 1491400SN/Awrite_buffers=8 1501400SN/Acpu_side=system.cpu.dcache_port 1511695SN/Amem_side=system.cpu.toL2Bus.slave[1] 1521400SN/A 1531400SN/A[system.cpu.dtb] 1542378SN/Atype=ArmTLB 1553170Sstever@eecs.umich.educhildren=walker 1563661Srdreslin@umich.edusize=64 1571858SN/Awalker=system.cpu.dtb.walker 1581917SN/A 1593617Sbinkertn@umich.edu[system.cpu.dtb.walker] 1603617Sbinkertn@umich.edutype=ArmTableWalker 1613617Sbinkertn@umich.edumax_backoff=100000 1623617Sbinkertn@umich.edumin_backoff=0 1631400SN/Asys=system 1642356SN/Aport=system.cpu.toL2Bus.slave[3] 1652315SN/A 1661917SN/A[system.cpu.fuPool] 1671917SN/Atype=FUPool 1681400SN/Achildren=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 1692SN/AFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 1701400SN/A 1712SN/A[system.cpu.fuPool.FUList0] 1721400SN/Atype=FUDesc 1731191SN/Achildren=opList 1742SN/Acount=6 1751129SN/AopList=system.cpu.fuPool.FUList0.opList 1761917SN/A 1772SN/A[system.cpu.fuPool.FUList0.opList] 1782SN/Atype=OpDesc 1792103SN/AissueLat=1 1802103SN/AopClass=IntAlu 1812680Sktlim@umich.eduopLat=1 182180SN/A 1831492SN/A[system.cpu.fuPool.FUList1] 1841492SN/Atype=FUDesc 1852798Sktlim@umich.educhildren=opList0 opList1 186180SN/Acount=2 187180SN/AopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 188180SN/A 189180SN/A[system.cpu.fuPool.FUList1.opList0] 190180SN/Atype=OpDesc 191124SN/AissueLat=1 192124SN/AopClass=IntMult 193124SN/AopLat=3 194124SN/A 1952SN/A[system.cpu.fuPool.FUList1.opList1] 1962SN/Atype=OpDesc 197124SN/AissueLat=19 198124SN/AopClass=IntDiv 199124SN/AopLat=20 200124SN/A 201124SN/A[system.cpu.fuPool.FUList2] 202503SN/Atype=FUDesc 2032SN/Achildren=opList0 opList1 opList2 204124SN/Acount=4 205124SN/AopList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 206124SN/A 207124SN/A[system.cpu.fuPool.FUList2.opList0] 208124SN/Atype=OpDesc 209124SN/AissueLat=1 210124SN/AopClass=FloatAdd 2112SN/AopLat=2 212921SN/A 2133661Srdreslin@umich.edu[system.cpu.fuPool.FUList2.opList1] 2143661Srdreslin@umich.edutype=OpDesc 2152378SN/AissueLat=1 216921SN/AopClass=FloatCmp 217921SN/AopLat=2 218921SN/A 219921SN/A[system.cpu.fuPool.FUList2.opList2] 220921SN/Atype=OpDesc 221921SN/AissueLat=1 222921SN/AopClass=FloatCvt 223921SN/AopLat=2 224921SN/A 225921SN/A[system.cpu.fuPool.FUList3] 226921SN/Atype=FUDesc 227921SN/Achildren=opList0 opList1 opList2 228921SN/Acount=2 2292SN/AopList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 2302SN/A 231124SN/A[system.cpu.fuPool.FUList3.opList0] 232124SN/Atype=OpDesc 233124SN/AissueLat=1 234124SN/AopClass=FloatMult 2352SN/AopLat=4 2362SN/A 237707SN/A[system.cpu.fuPool.FUList3.opList1] 238707SN/Atype=OpDesc 2391191SN/AissueLat=12 2401191SN/AopClass=FloatDiv 2411191SN/AopLat=12 2421191SN/A 2431191SN/A[system.cpu.fuPool.FUList3.opList2] 2441191SN/Atype=OpDesc 2451191SN/AissueLat=24 2461191SN/AopClass=FloatSqrt 2471191SN/AopLat=24 2481191SN/A 2491191SN/A[system.cpu.fuPool.FUList4] 2501191SN/Atype=FUDesc 2511191SN/Achildren=opList 2521191SN/Acount=0 2531191SN/AopList=system.cpu.fuPool.FUList4.opList 2541191SN/A 2551191SN/A[system.cpu.fuPool.FUList4.opList] 2562SN/Atype=OpDesc 2572SN/AissueLat=1 2582SN/AopClass=MemRead 2592SN/AopLat=1 2602SN/A 261707SN/A[system.cpu.fuPool.FUList5] 262707SN/Atype=FUDesc 263707SN/Achildren=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 264707SN/Acount=4 265707SN/AopList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 266707SN/A 267707SN/A[system.cpu.fuPool.FUList5.opList00] 268707SN/Atype=OpDesc 269707SN/AissueLat=1 270707SN/AopClass=SimdAdd 271707SN/AopLat=1 272707SN/A 273707SN/A[system.cpu.fuPool.FUList5.opList01] 274729SN/Atype=OpDesc 2752SN/AissueLat=1 2762SN/AopClass=SimdAddAcc 2771717SN/AopLat=1 278 279[system.cpu.fuPool.FUList5.opList02] 280type=OpDesc 281issueLat=1 282opClass=SimdAlu 283opLat=1 284 285[system.cpu.fuPool.FUList5.opList03] 286type=OpDesc 287issueLat=1 288opClass=SimdCmp 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList04] 292type=OpDesc 293issueLat=1 294opClass=SimdCvt 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList05] 298type=OpDesc 299issueLat=1 300opClass=SimdMisc 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList06] 304type=OpDesc 305issueLat=1 306opClass=SimdMult 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList07] 310type=OpDesc 311issueLat=1 312opClass=SimdMultAcc 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList08] 316type=OpDesc 317issueLat=1 318opClass=SimdShift 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList09] 322type=OpDesc 323issueLat=1 324opClass=SimdShiftAcc 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList10] 328type=OpDesc 329issueLat=1 330opClass=SimdSqrt 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList11] 334type=OpDesc 335issueLat=1 336opClass=SimdFloatAdd 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList12] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatAlu 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList13] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatCmp 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList14] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatCvt 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList15] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatDiv 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList16] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatMisc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList17] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMult 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList18] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatMultAcc 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList19] 382type=OpDesc 383issueLat=1 384opClass=SimdFloatSqrt 385opLat=1 386 387[system.cpu.fuPool.FUList6] 388type=FUDesc 389children=opList 390count=0 391opList=system.cpu.fuPool.FUList6.opList 392 393[system.cpu.fuPool.FUList6.opList] 394type=OpDesc 395issueLat=1 396opClass=MemWrite 397opLat=1 398 399[system.cpu.fuPool.FUList7] 400type=FUDesc 401children=opList0 opList1 402count=4 403opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 404 405[system.cpu.fuPool.FUList7.opList0] 406type=OpDesc 407issueLat=1 408opClass=MemRead 409opLat=1 410 411[system.cpu.fuPool.FUList7.opList1] 412type=OpDesc 413issueLat=1 414opClass=MemWrite 415opLat=1 416 417[system.cpu.fuPool.FUList8] 418type=FUDesc 419children=opList 420count=1 421opList=system.cpu.fuPool.FUList8.opList 422 423[system.cpu.fuPool.FUList8.opList] 424type=OpDesc 425issueLat=3 426opClass=IprAccess 427opLat=3 428 429[system.cpu.icache] 430type=BaseCache 431addr_ranges=0:18446744073709551615 432assoc=2 433block_size=64 434forward_snoops=true 435hash_delay=1 436is_top_level=true 437latency=1000 438max_miss_count=0 439mshrs=10 440prefetch_on_access=false 441prefetcher=Null 442prioritizeRequests=false 443repl=Null 444size=131072 445subblock_size=0 446system=system 447tgts_per_mshr=20 448trace_addr=0 449two_queue=false 450write_buffers=8 451cpu_side=system.cpu.icache_port 452mem_side=system.cpu.toL2Bus.slave[0] 453 454[system.cpu.interrupts] 455type=ArmInterrupts 456 457[system.cpu.itb] 458type=ArmTLB 459children=walker 460size=64 461walker=system.cpu.itb.walker 462 463[system.cpu.itb.walker] 464type=ArmTableWalker 465max_backoff=100000 466min_backoff=0 467sys=system 468port=system.cpu.toL2Bus.slave[2] 469 470[system.cpu.l2cache] 471type=BaseCache 472addr_ranges=0:18446744073709551615 473assoc=2 474block_size=64 475forward_snoops=true 476hash_delay=1 477is_top_level=false 478latency=1000 479max_miss_count=0 480mshrs=10 481prefetch_on_access=false 482prefetcher=Null 483prioritizeRequests=false 484repl=Null 485size=2097152 486subblock_size=0 487system=system 488tgts_per_mshr=5 489trace_addr=0 490two_queue=false 491write_buffers=8 492cpu_side=system.cpu.toL2Bus.master[0] 493mem_side=system.membus.slave[1] 494 495[system.cpu.toL2Bus] 496type=Bus 497block_size=64 498bus_id=0 499clock=1000 500header_cycles=1 501use_default_range=false 502width=64 503master=system.cpu.l2cache.cpu_side 504slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 505 506[system.cpu.tracer] 507type=ExeTracer 508 509[system.cpu.workload] 510type=LiveProcess 511cmd=vortex lendian.raw 512cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing 513egid=100 514env= 515errout=cerr 516euid=100 517executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex 518gid=100 519input=cin 520max_stack_size=67108864 521output=cout 522pid=100 523ppid=99 524simpoint=0 525system=system 526uid=100 527 528[system.membus] 529type=Bus 530block_size=64 531bus_id=0 532clock=1000 533header_cycles=1 534use_default_range=false 535width=64 536master=system.physmem.port[0] 537slave=system.system_port system.cpu.l2cache.mem_side 538 539[system.physmem] 540type=PhysicalMemory 541file= 542latency=30000 543latency_var=0 544null=false 545range=0:134217727 546zero=false 547port=system.membus.master[0] 548 549