config.ini revision 11680:b4d943429dc6
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=16 61LSQCheckLoads=true 62LSQDepCheckShift=0 63SQEntries=16 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=2 79decodeWidth=3 80default_p_state=UNDEFINED 81dispatchWidth=6 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dstage2_mmu=system.cpu.dstage2_mmu 86dtb=system.cpu.dtb 87eventq_index=0 88fetchBufferSize=16 89fetchQueueSize=32 90fetchToDecodeDelay=3 91fetchTrapLatency=1 92fetchWidth=3 93forwardComSize=5 94fuPool=system.cpu.fuPool 95function_trace=false 96function_trace_start=0 97iewToCommitDelay=1 98iewToDecodeDelay=1 99iewToFetchDelay=1 100iewToRenameDelay=1 101interrupts=system.cpu.interrupts 102isa=system.cpu.isa 103issueToExecuteDelay=1 104issueWidth=8 105istage2_mmu=system.cpu.istage2_mmu 106itb=system.cpu.itb 107max_insts_all_threads=0 108max_insts_any_thread=0 109max_loads_all_threads=0 110max_loads_any_thread=0 111needsTSO=false 112numIQEntries=32 113numPhysCCRegs=640 114numPhysFloatRegs=192 115numPhysIntRegs=128 116numROBEntries=40 117numRobs=1 118numThreads=1 119p_state_clk_gate_bins=20 120p_state_clk_gate_max=1000000000000 121p_state_clk_gate_min=1000 122power_model=Null 123profile=0 124progress_interval=0 125renameToDecodeDelay=1 126renameToFetchDelay=1 127renameToIEWDelay=1 128renameToROBDelay=1 129renameWidth=3 130simpoint_start_insts= 131smtCommitPolicy=RoundRobin 132smtFetchPolicy=SingleThread 133smtIQPolicy=Partitioned 134smtIQThreshold=100 135smtLSQPolicy=Partitioned 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false 144system=system 145tracer=system.cpu.tracer 146trapLatency=13 147wbWidth=8 148workload=system.cpu.workload 149dcache_port=system.cpu.dcache.cpu_side 150icache_port=system.cpu.icache.cpu_side 151 152[system.cpu.branchPred] 153type=BiModeBP 154BTBEntries=2048 155BTBTagSize=18 156RASSize=16 157choiceCtrBits=2 158choicePredictorSize=8192 159eventq_index=0 160globalCtrBits=2 161globalPredictorSize=8192 162indirectHashGHR=true 163indirectHashTargets=true 164indirectPathLength=3 165indirectSets=256 166indirectTagSize=16 167indirectWays=2 168instShiftAmt=2 169numThreads=1 170useIndirect=true 171 172[system.cpu.dcache] 173type=Cache 174children=tags 175addr_ranges=0:18446744073709551615:0:0:0:0 176assoc=2 177clk_domain=system.cpu_clk_domain 178clusivity=mostly_incl 179default_p_state=UNDEFINED 180demand_mshr_reserve=1 181eventq_index=0 182hit_latency=2 183is_read_only=false 184max_miss_count=0 185mshrs=6 186p_state_clk_gate_bins=20 187p_state_clk_gate_max=1000000000000 188p_state_clk_gate_min=1000 189power_model=Null 190prefetch_on_access=false 191prefetcher=Null 192response_latency=2 193sequential_access=false 194size=32768 195system=system 196tags=system.cpu.dcache.tags 197tgts_per_mshr=8 198write_buffers=16 199writeback_clean=true 200cpu_side=system.cpu.dcache_port 201mem_side=system.cpu.toL2Bus.slave[1] 202 203[system.cpu.dcache.tags] 204type=LRU 205assoc=2 206block_size=64 207clk_domain=system.cpu_clk_domain 208default_p_state=UNDEFINED 209eventq_index=0 210hit_latency=2 211p_state_clk_gate_bins=20 212p_state_clk_gate_max=1000000000000 213p_state_clk_gate_min=1000 214power_model=Null 215sequential_access=false 216size=32768 217 218[system.cpu.dstage2_mmu] 219type=ArmStage2MMU 220children=stage2_tlb 221eventq_index=0 222stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 223sys=system 224tlb=system.cpu.dtb 225 226[system.cpu.dstage2_mmu.stage2_tlb] 227type=ArmTLB 228children=walker 229eventq_index=0 230is_stage2=true 231size=32 232walker=system.cpu.dstage2_mmu.stage2_tlb.walker 233 234[system.cpu.dstage2_mmu.stage2_tlb.walker] 235type=ArmTableWalker 236clk_domain=system.cpu_clk_domain 237default_p_state=UNDEFINED 238eventq_index=0 239is_stage2=true 240num_squash_per_cycle=2 241p_state_clk_gate_bins=20 242p_state_clk_gate_max=1000000000000 243p_state_clk_gate_min=1000 244power_model=Null 245sys=system 246 247[system.cpu.dtb] 248type=ArmTLB 249children=walker 250eventq_index=0 251is_stage2=false 252size=64 253walker=system.cpu.dtb.walker 254 255[system.cpu.dtb.walker] 256type=ArmTableWalker 257clk_domain=system.cpu_clk_domain 258default_p_state=UNDEFINED 259eventq_index=0 260is_stage2=false 261num_squash_per_cycle=2 262p_state_clk_gate_bins=20 263p_state_clk_gate_max=1000000000000 264p_state_clk_gate_min=1000 265power_model=Null 266sys=system 267port=system.cpu.toL2Bus.slave[3] 268 269[system.cpu.fuPool] 270type=FUPool 271children=FUList0 FUList1 FUList2 FUList3 FUList4 272FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 273eventq_index=0 274 275[system.cpu.fuPool.FUList0] 276type=FUDesc 277children=opList 278count=2 279eventq_index=0 280opList=system.cpu.fuPool.FUList0.opList 281 282[system.cpu.fuPool.FUList0.opList] 283type=OpDesc 284eventq_index=0 285opClass=IntAlu 286opLat=1 287pipelined=true 288 289[system.cpu.fuPool.FUList1] 290type=FUDesc 291children=opList0 opList1 opList2 292count=1 293eventq_index=0 294opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 295 296[system.cpu.fuPool.FUList1.opList0] 297type=OpDesc 298eventq_index=0 299opClass=IntMult 300opLat=3 301pipelined=true 302 303[system.cpu.fuPool.FUList1.opList1] 304type=OpDesc 305eventq_index=0 306opClass=IntDiv 307opLat=12 308pipelined=false 309 310[system.cpu.fuPool.FUList1.opList2] 311type=OpDesc 312eventq_index=0 313opClass=IprAccess 314opLat=3 315pipelined=true 316 317[system.cpu.fuPool.FUList2] 318type=FUDesc 319children=opList 320count=1 321eventq_index=0 322opList=system.cpu.fuPool.FUList2.opList 323 324[system.cpu.fuPool.FUList2.opList] 325type=OpDesc 326eventq_index=0 327opClass=MemRead 328opLat=2 329pipelined=true 330 331[system.cpu.fuPool.FUList3] 332type=FUDesc 333children=opList 334count=1 335eventq_index=0 336opList=system.cpu.fuPool.FUList3.opList 337 338[system.cpu.fuPool.FUList3.opList] 339type=OpDesc 340eventq_index=0 341opClass=MemWrite 342opLat=2 343pipelined=true 344 345[system.cpu.fuPool.FUList4] 346type=FUDesc 347children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 348count=2 349eventq_index=0 350opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 351 352[system.cpu.fuPool.FUList4.opList00] 353type=OpDesc 354eventq_index=0 355opClass=SimdAdd 356opLat=4 357pipelined=true 358 359[system.cpu.fuPool.FUList4.opList01] 360type=OpDesc 361eventq_index=0 362opClass=SimdAddAcc 363opLat=4 364pipelined=true 365 366[system.cpu.fuPool.FUList4.opList02] 367type=OpDesc 368eventq_index=0 369opClass=SimdAlu 370opLat=4 371pipelined=true 372 373[system.cpu.fuPool.FUList4.opList03] 374type=OpDesc 375eventq_index=0 376opClass=SimdCmp 377opLat=4 378pipelined=true 379 380[system.cpu.fuPool.FUList4.opList04] 381type=OpDesc 382eventq_index=0 383opClass=SimdCvt 384opLat=3 385pipelined=true 386 387[system.cpu.fuPool.FUList4.opList05] 388type=OpDesc 389eventq_index=0 390opClass=SimdMisc 391opLat=3 392pipelined=true 393 394[system.cpu.fuPool.FUList4.opList06] 395type=OpDesc 396eventq_index=0 397opClass=SimdMult 398opLat=5 399pipelined=true 400 401[system.cpu.fuPool.FUList4.opList07] 402type=OpDesc 403eventq_index=0 404opClass=SimdMultAcc 405opLat=5 406pipelined=true 407 408[system.cpu.fuPool.FUList4.opList08] 409type=OpDesc 410eventq_index=0 411opClass=SimdShift 412opLat=3 413pipelined=true 414 415[system.cpu.fuPool.FUList4.opList09] 416type=OpDesc 417eventq_index=0 418opClass=SimdShiftAcc 419opLat=3 420pipelined=true 421 422[system.cpu.fuPool.FUList4.opList10] 423type=OpDesc 424eventq_index=0 425opClass=SimdSqrt 426opLat=9 427pipelined=true 428 429[system.cpu.fuPool.FUList4.opList11] 430type=OpDesc 431eventq_index=0 432opClass=SimdFloatAdd 433opLat=5 434pipelined=true 435 436[system.cpu.fuPool.FUList4.opList12] 437type=OpDesc 438eventq_index=0 439opClass=SimdFloatAlu 440opLat=5 441pipelined=true 442 443[system.cpu.fuPool.FUList4.opList13] 444type=OpDesc 445eventq_index=0 446opClass=SimdFloatCmp 447opLat=3 448pipelined=true 449 450[system.cpu.fuPool.FUList4.opList14] 451type=OpDesc 452eventq_index=0 453opClass=SimdFloatCvt 454opLat=3 455pipelined=true 456 457[system.cpu.fuPool.FUList4.opList15] 458type=OpDesc 459eventq_index=0 460opClass=SimdFloatDiv 461opLat=3 462pipelined=true 463 464[system.cpu.fuPool.FUList4.opList16] 465type=OpDesc 466eventq_index=0 467opClass=SimdFloatMisc 468opLat=3 469pipelined=true 470 471[system.cpu.fuPool.FUList4.opList17] 472type=OpDesc 473eventq_index=0 474opClass=SimdFloatMult 475opLat=3 476pipelined=true 477 478[system.cpu.fuPool.FUList4.opList18] 479type=OpDesc 480eventq_index=0 481opClass=SimdFloatMultAcc 482opLat=1 483pipelined=true 484 485[system.cpu.fuPool.FUList4.opList19] 486type=OpDesc 487eventq_index=0 488opClass=SimdFloatSqrt 489opLat=9 490pipelined=true 491 492[system.cpu.fuPool.FUList4.opList20] 493type=OpDesc 494eventq_index=0 495opClass=FloatAdd 496opLat=5 497pipelined=true 498 499[system.cpu.fuPool.FUList4.opList21] 500type=OpDesc 501eventq_index=0 502opClass=FloatCmp 503opLat=5 504pipelined=true 505 506[system.cpu.fuPool.FUList4.opList22] 507type=OpDesc 508eventq_index=0 509opClass=FloatCvt 510opLat=5 511pipelined=true 512 513[system.cpu.fuPool.FUList4.opList23] 514type=OpDesc 515eventq_index=0 516opClass=FloatDiv 517opLat=9 518pipelined=false 519 520[system.cpu.fuPool.FUList4.opList24] 521type=OpDesc 522eventq_index=0 523opClass=FloatSqrt 524opLat=33 525pipelined=false 526 527[system.cpu.fuPool.FUList4.opList25] 528type=OpDesc 529eventq_index=0 530opClass=FloatMult 531opLat=4 532pipelined=true 533 534[system.cpu.icache] 535type=Cache 536children=tags 537addr_ranges=0:18446744073709551615:0:0:0:0 538assoc=2 539clk_domain=system.cpu_clk_domain 540clusivity=mostly_incl 541default_p_state=UNDEFINED 542demand_mshr_reserve=1 543eventq_index=0 544hit_latency=1 545is_read_only=true 546max_miss_count=0 547mshrs=2 548p_state_clk_gate_bins=20 549p_state_clk_gate_max=1000000000000 550p_state_clk_gate_min=1000 551power_model=Null 552prefetch_on_access=false 553prefetcher=Null 554response_latency=1 555sequential_access=false 556size=32768 557system=system 558tags=system.cpu.icache.tags 559tgts_per_mshr=8 560write_buffers=8 561writeback_clean=true 562cpu_side=system.cpu.icache_port 563mem_side=system.cpu.toL2Bus.slave[0] 564 565[system.cpu.icache.tags] 566type=LRU 567assoc=2 568block_size=64 569clk_domain=system.cpu_clk_domain 570default_p_state=UNDEFINED 571eventq_index=0 572hit_latency=1 573p_state_clk_gate_bins=20 574p_state_clk_gate_max=1000000000000 575p_state_clk_gate_min=1000 576power_model=Null 577sequential_access=false 578size=32768 579 580[system.cpu.interrupts] 581type=ArmInterrupts 582eventq_index=0 583 584[system.cpu.isa] 585type=ArmISA 586decoderFlavour=Generic 587eventq_index=0 588fpsid=1090793632 589id_aa64afr0_el1=0 590id_aa64afr1_el1=0 591id_aa64dfr0_el1=1052678 592id_aa64dfr1_el1=0 593id_aa64isar0_el1=0 594id_aa64isar1_el1=0 595id_aa64mmfr0_el1=15728642 596id_aa64mmfr1_el1=0 597id_aa64pfr0_el1=34 598id_aa64pfr1_el1=0 599id_isar0=34607377 600id_isar1=34677009 601id_isar2=555950401 602id_isar3=17899825 603id_isar4=268501314 604id_isar5=0 605id_mmfr0=270536963 606id_mmfr1=0 607id_mmfr2=19070976 608id_mmfr3=34611729 609id_pfr0=49 610id_pfr1=4113 611midr=1091551472 612pmu=Null 613system=system 614 615[system.cpu.istage2_mmu] 616type=ArmStage2MMU 617children=stage2_tlb 618eventq_index=0 619stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 620sys=system 621tlb=system.cpu.itb 622 623[system.cpu.istage2_mmu.stage2_tlb] 624type=ArmTLB 625children=walker 626eventq_index=0 627is_stage2=true 628size=32 629walker=system.cpu.istage2_mmu.stage2_tlb.walker 630 631[system.cpu.istage2_mmu.stage2_tlb.walker] 632type=ArmTableWalker 633clk_domain=system.cpu_clk_domain 634default_p_state=UNDEFINED 635eventq_index=0 636is_stage2=true 637num_squash_per_cycle=2 638p_state_clk_gate_bins=20 639p_state_clk_gate_max=1000000000000 640p_state_clk_gate_min=1000 641power_model=Null 642sys=system 643 644[system.cpu.itb] 645type=ArmTLB 646children=walker 647eventq_index=0 648is_stage2=false 649size=64 650walker=system.cpu.itb.walker 651 652[system.cpu.itb.walker] 653type=ArmTableWalker 654clk_domain=system.cpu_clk_domain 655default_p_state=UNDEFINED 656eventq_index=0 657is_stage2=false 658num_squash_per_cycle=2 659p_state_clk_gate_bins=20 660p_state_clk_gate_max=1000000000000 661p_state_clk_gate_min=1000 662power_model=Null 663sys=system 664port=system.cpu.toL2Bus.slave[2] 665 666[system.cpu.l2cache] 667type=Cache 668children=prefetcher tags 669addr_ranges=0:18446744073709551615:0:0:0:0 670assoc=16 671clk_domain=system.cpu_clk_domain 672clusivity=mostly_excl 673default_p_state=UNDEFINED 674demand_mshr_reserve=1 675eventq_index=0 676hit_latency=12 677is_read_only=false 678max_miss_count=0 679mshrs=16 680p_state_clk_gate_bins=20 681p_state_clk_gate_max=1000000000000 682p_state_clk_gate_min=1000 683power_model=Null 684prefetch_on_access=true 685prefetcher=system.cpu.l2cache.prefetcher 686response_latency=12 687sequential_access=false 688size=1048576 689system=system 690tags=system.cpu.l2cache.tags 691tgts_per_mshr=8 692write_buffers=8 693writeback_clean=false 694cpu_side=system.cpu.toL2Bus.master[0] 695mem_side=system.membus.slave[1] 696 697[system.cpu.l2cache.prefetcher] 698type=StridePrefetcher 699cache_snoop=false 700clk_domain=system.cpu_clk_domain 701default_p_state=UNDEFINED 702degree=8 703eventq_index=0 704latency=1 705max_conf=7 706min_conf=0 707on_data=true 708on_inst=true 709on_miss=false 710on_read=true 711on_write=true 712p_state_clk_gate_bins=20 713p_state_clk_gate_max=1000000000000 714p_state_clk_gate_min=1000 715power_model=Null 716queue_filter=true 717queue_size=32 718queue_squash=true 719start_conf=4 720sys=system 721table_assoc=4 722table_sets=16 723tag_prefetch=true 724thresh_conf=4 725use_master_id=true 726 727[system.cpu.l2cache.tags] 728type=RandomRepl 729assoc=16 730block_size=64 731clk_domain=system.cpu_clk_domain 732default_p_state=UNDEFINED 733eventq_index=0 734hit_latency=12 735p_state_clk_gate_bins=20 736p_state_clk_gate_max=1000000000000 737p_state_clk_gate_min=1000 738power_model=Null 739sequential_access=false 740size=1048576 741 742[system.cpu.toL2Bus] 743type=CoherentXBar 744children=snoop_filter 745clk_domain=system.cpu_clk_domain 746default_p_state=UNDEFINED 747eventq_index=0 748forward_latency=0 749frontend_latency=1 750p_state_clk_gate_bins=20 751p_state_clk_gate_max=1000000000000 752p_state_clk_gate_min=1000 753point_of_coherency=false 754power_model=Null 755response_latency=1 756snoop_filter=system.cpu.toL2Bus.snoop_filter 757snoop_response_latency=1 758system=system 759use_default_range=false 760width=32 761master=system.cpu.l2cache.cpu_side 762slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 763 764[system.cpu.toL2Bus.snoop_filter] 765type=SnoopFilter 766eventq_index=0 767lookup_latency=0 768max_capacity=8388608 769system=system 770 771[system.cpu.tracer] 772type=ExeTracer 773eventq_index=0 774 775[system.cpu.workload] 776type=LiveProcess 777cmd=vortex lendian.raw 778cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing 779drivers= 780egid=100 781env= 782errout=cerr 783euid=100 784eventq_index=0 785executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex 786gid=100 787input=cin 788kvmInSE=false 789max_stack_size=67108864 790output=cout 791pid=100 792ppid=99 793simpoint=0 794system=system 795uid=100 796useArchPT=false 797 798[system.cpu_clk_domain] 799type=SrcClockDomain 800clock=500 801domain_id=-1 802eventq_index=0 803init_perf_level=0 804voltage_domain=system.voltage_domain 805 806[system.dvfs_handler] 807type=DVFSHandler 808domains= 809enable=false 810eventq_index=0 811sys_clk_domain=system.clk_domain 812transition_latency=100000000 813 814[system.membus] 815type=CoherentXBar 816children=snoop_filter 817clk_domain=system.clk_domain 818default_p_state=UNDEFINED 819eventq_index=0 820forward_latency=4 821frontend_latency=3 822p_state_clk_gate_bins=20 823p_state_clk_gate_max=1000000000000 824p_state_clk_gate_min=1000 825point_of_coherency=true 826power_model=Null 827response_latency=2 828snoop_filter=system.membus.snoop_filter 829snoop_response_latency=4 830system=system 831use_default_range=false 832width=16 833master=system.physmem.port 834slave=system.system_port system.cpu.l2cache.mem_side 835 836[system.membus.snoop_filter] 837type=SnoopFilter 838eventq_index=0 839lookup_latency=1 840max_capacity=8388608 841system=system 842 843[system.physmem] 844type=DRAMCtrl 845IDD0=0.055000 846IDD02=0.000000 847IDD2N=0.032000 848IDD2N2=0.000000 849IDD2P0=0.000000 850IDD2P02=0.000000 851IDD2P1=0.032000 852IDD2P12=0.000000 853IDD3N=0.038000 854IDD3N2=0.000000 855IDD3P0=0.000000 856IDD3P02=0.000000 857IDD3P1=0.038000 858IDD3P12=0.000000 859IDD4R=0.157000 860IDD4R2=0.000000 861IDD4W=0.125000 862IDD4W2=0.000000 863IDD5=0.235000 864IDD52=0.000000 865IDD6=0.020000 866IDD62=0.000000 867VDD=1.500000 868VDD2=0.000000 869activation_limit=4 870addr_mapping=RoRaBaCoCh 871bank_groups_per_rank=0 872banks_per_rank=8 873burst_length=8 874channels=1 875clk_domain=system.clk_domain 876conf_table_reported=true 877default_p_state=UNDEFINED 878device_bus_width=8 879device_rowbuffer_size=1024 880device_size=536870912 881devices_per_rank=8 882dll=true 883eventq_index=0 884in_addr_map=true 885kvm_map=true 886max_accesses_per_row=16 887mem_sched_policy=frfcfs 888min_writes_per_switch=16 889null=false 890p_state_clk_gate_bins=20 891p_state_clk_gate_max=1000000000000 892p_state_clk_gate_min=1000 893page_policy=open_adaptive 894power_model=Null 895range=0:134217727:0:0:0:0 896ranks_per_channel=2 897read_buffer_size=32 898static_backend_latency=10000 899static_frontend_latency=10000 900tBURST=5000 901tCCD_L=0 902tCK=1250 903tCL=13750 904tCS=2500 905tRAS=35000 906tRCD=13750 907tREFI=7800000 908tRFC=260000 909tRP=13750 910tRRD=6000 911tRRD_L=0 912tRTP=7500 913tRTW=2500 914tWR=15000 915tWTR=7500 916tXAW=30000 917tXP=6000 918tXPDLL=0 919tXS=270000 920tXSDLL=0 921write_buffer_size=64 922write_high_thresh_perc=85 923write_low_thresh_perc=50 924port=system.membus.master[0] 925 926[system.voltage_domain] 927type=VoltageDomain 928eventq_index=0 929voltage=1.000000 930 931