stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.945613 # Number of seconds simulated 4sim_ticks 945613131000 # Number of ticks simulated 5final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2997522 # Simulator instruction rate (inst/s) 8host_tick_rate 1503443037 # Simulator tick rate (ticks/s) 9host_mem_usage 215364 # Number of bytes of host memory used 10host_seconds 628.97 # Real time elapsed on the host 11sim_insts 1885336367 # Number of instructions simulated 12system.physmem.bytes_read 8025491315 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 5561086040 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 1123958396 # Number of bytes written to this memory 15system.physmem.num_reads 2010616909 # Number of read requests responded to by this memory 16system.physmem.num_writes 276945663 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 8487076852 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 5880931491 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 1188602780 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 9675679632 # Total bandwidth to/from this memory (bytes/s) 22system.cpu.dtb.inst_hits 0 # ITB inst hits 23system.cpu.dtb.inst_misses 0 # ITB inst misses 24system.cpu.dtb.read_hits 0 # DTB read hits 25system.cpu.dtb.read_misses 0 # DTB read misses 26system.cpu.dtb.write_hits 0 # DTB write hits 27system.cpu.dtb.write_misses 0 # DTB write misses 28system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 29system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 33system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 34system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 35system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 36system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37system.cpu.dtb.read_accesses 0 # DTB read accesses 38system.cpu.dtb.write_accesses 0 # DTB write accesses 39system.cpu.dtb.inst_accesses 0 # ITB inst accesses 40system.cpu.dtb.hits 0 # DTB hits 41system.cpu.dtb.misses 0 # DTB misses 42system.cpu.dtb.accesses 0 # DTB accesses 43system.cpu.itb.inst_hits 0 # ITB inst hits 44system.cpu.itb.inst_misses 0 # ITB inst misses 45system.cpu.itb.read_hits 0 # DTB read hits 46system.cpu.itb.read_misses 0 # DTB read misses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 50system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 51system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 52system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 53system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 54system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 56system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 57system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 58system.cpu.itb.read_accesses 0 # DTB read accesses 59system.cpu.itb.write_accesses 0 # DTB write accesses 60system.cpu.itb.inst_accesses 0 # ITB inst accesses 61system.cpu.itb.hits 0 # DTB hits 62system.cpu.itb.misses 0 # DTB misses 63system.cpu.itb.accesses 0 # DTB accesses 64system.cpu.workload.num_syscalls 1411 # Number of system calls 65system.cpu.numCycles 1891226263 # number of cpu cycles simulated 66system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 67system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 68system.cpu.num_insts 1885336367 # Number of instructions executed 69system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses 70system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses 71system.cpu.num_func_calls 80344203 # number of times a function call or return occured 72system.cpu.num_conditional_control_insts 223625914 # number of instructions that are conditional controls 73system.cpu.num_int_insts 1653698876 # number of integer instructions 74system.cpu.num_fp_insts 52289415 # number of float instructions 75system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read 76system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written 77system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read 78system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written 79system.cpu.num_mem_refs 908382480 # number of memory refs 80system.cpu.num_load_insts 631387182 # Number of load instructions 81system.cpu.num_store_insts 276995298 # Number of store instructions 82system.cpu.num_idle_cycles 0 # Number of idle cycles 83system.cpu.num_busy_cycles 1891226263 # Number of busy cycles 84system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 85system.cpu.idle_fraction 0 # Percentage of idle cycles 86 87---------- End Simulation Statistics ---------- 88