stats.txt revision 8893:e29c604a2582
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.736384 # Number of seconds simulated 4sim_ticks 736384204000 # Number of ticks simulated 5final_tick 736384204000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 107029 # Simulator instruction rate (inst/s) 8host_op_rate 145759 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56931535 # Simulator tick rate (ticks/s) 10host_mem_usage 233236 # Number of bytes of host memory used 11host_seconds 12934.56 # Real time elapsed on the host 12sim_insts 1384379033 # Number of instructions simulated 13sim_ops 1885333786 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 94833536 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 209216 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 4230336 # Number of bytes written to this memory 17system.physmem.num_reads 1481774 # Number of read requests responded to by this memory 18system.physmem.num_writes 66099 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 128782686 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 284113 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 5744740 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 134527427 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.dtb.inst_hits 0 # ITB inst hits 25system.cpu.dtb.inst_misses 0 # ITB inst misses 26system.cpu.dtb.read_hits 0 # DTB read hits 27system.cpu.dtb.read_misses 0 # DTB read misses 28system.cpu.dtb.write_hits 0 # DTB write hits 29system.cpu.dtb.write_misses 0 # DTB write misses 30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 36system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 37system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 38system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39system.cpu.dtb.read_accesses 0 # DTB read accesses 40system.cpu.dtb.write_accesses 0 # DTB write accesses 41system.cpu.dtb.inst_accesses 0 # ITB inst accesses 42system.cpu.dtb.hits 0 # DTB hits 43system.cpu.dtb.misses 0 # DTB misses 44system.cpu.dtb.accesses 0 # DTB accesses 45system.cpu.itb.inst_hits 0 # ITB inst hits 46system.cpu.itb.inst_misses 0 # ITB inst misses 47system.cpu.itb.read_hits 0 # DTB read hits 48system.cpu.itb.read_misses 0 # DTB read misses 49system.cpu.itb.write_hits 0 # DTB write hits 50system.cpu.itb.write_misses 0 # DTB write misses 51system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 52system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 53system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 54system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 55system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 56system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60system.cpu.itb.read_accesses 0 # DTB read accesses 61system.cpu.itb.write_accesses 0 # DTB write accesses 62system.cpu.itb.inst_accesses 0 # ITB inst accesses 63system.cpu.itb.hits 0 # DTB hits 64system.cpu.itb.misses 0 # DTB misses 65system.cpu.itb.accesses 0 # DTB accesses 66system.cpu.workload.num_syscalls 1411 # Number of system calls 67system.cpu.numCycles 1472768409 # number of cpu cycles simulated 68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 70system.cpu.BPredUnit.lookups 522739689 # Number of BP lookups 71system.cpu.BPredUnit.condPredicted 397666770 # Number of conditional branches predicted 72system.cpu.BPredUnit.condIncorrect 35592388 # Number of conditional branches incorrect 73system.cpu.BPredUnit.BTBLookups 329507474 # Number of BTB lookups 74system.cpu.BPredUnit.BTBHits 283194756 # Number of BTB hits 75system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 76system.cpu.BPredUnit.usedRAS 59112231 # Number of times the RAS was used to get a target. 77system.cpu.BPredUnit.RASInCorrect 2837995 # Number of incorrect RAS predictions. 78system.cpu.fetch.icacheStallCycles 446610303 # Number of cycles fetch is stalled on an Icache miss 79system.cpu.fetch.Insts 2608281266 # Number of instructions fetch has processed 80system.cpu.fetch.Branches 522739689 # Number of branches that fetch encountered 81system.cpu.fetch.predictedBranches 342306987 # Number of branches that fetch has predicted taken 82system.cpu.fetch.Cycles 709905843 # Number of cycles fetch has run and was not squashing or blocked 83system.cpu.fetch.SquashCycles 224599686 # Number of cycles fetch has spent squashing 84system.cpu.fetch.BlockedCycles 101691904 # Number of cycles fetch has spent blocked 85system.cpu.fetch.MiscStallCycles 2256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 86system.cpu.fetch.PendingTrapStallCycles 28872 # Number of stall cycles due to pending traps 87system.cpu.fetch.CacheLines 415462379 # Number of cache lines fetched 88system.cpu.fetch.IcacheSquashes 10233497 # Number of outstanding Icache misses that were squashed 89system.cpu.fetch.rateDist::samples 1441668699 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::mean 2.553094 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::stdev 3.169508 # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::0 731812218 50.76% 50.76% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::1 54028478 3.75% 54.51% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::2 112774395 7.82% 62.33% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::3 69112712 4.79% 67.13% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::4 82239849 5.70% 72.83% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::5 54732676 3.80% 76.63% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::6 35582945 2.47% 79.09% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::7 33403067 2.32% 81.41% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::8 267982359 18.59% 100.00% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::total 1441668699 # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.branchRate 0.354937 # Number of branch fetches per cycle 107system.cpu.fetch.rate 1.771006 # Number of inst fetches per cycle 108system.cpu.decode.IdleCycles 492629108 # Number of cycles decode is idle 109system.cpu.decode.BlockedCycles 81861101 # Number of cycles decode is blocked 110system.cpu.decode.RunCycles 672684141 # Number of cycles decode is running 111system.cpu.decode.UnblockCycles 11080003 # Number of cycles decode is unblocking 112system.cpu.decode.SquashCycles 183414346 # Number of cycles decode is squashing 113system.cpu.decode.BranchResolved 82040809 # Number of times decode resolved a branch 114system.cpu.decode.BranchMispred 15532 # Number of times decode detected a branch misprediction 115system.cpu.decode.DecodedInsts 3552890515 # Number of instructions handled by decode 116system.cpu.decode.SquashedInsts 32736 # Number of squashed instructions handled by decode 117system.cpu.rename.SquashCycles 183414346 # Number of cycles rename is squashing 118system.cpu.rename.IdleCycles 530589836 # Number of cycles rename is idle 119system.cpu.rename.BlockCycles 29829797 # Number of cycles rename is blocking 120system.cpu.rename.serializeStallCycles 3588754 # count of cycles rename stalled for serializing inst 121system.cpu.rename.RunCycles 644081795 # Number of cycles rename is running 122system.cpu.rename.UnblockCycles 50164171 # Number of cycles rename is unblocking 123system.cpu.rename.RenamedInsts 3435316942 # Number of instructions processed by rename 124system.cpu.rename.ROBFullEvents 112 # Number of times rename has blocked due to ROB full 125system.cpu.rename.IQFullEvents 4205507 # Number of times rename has blocked due to IQ full 126system.cpu.rename.LSQFullEvents 40993124 # Number of times rename has blocked due to LSQ full 127system.cpu.rename.FullRegisterEvents 37 # Number of times there has been no free registers 128system.cpu.rename.RenamedOperands 3332970891 # Number of destination operands rename has renamed 129system.cpu.rename.RenameLookups 16270156364 # Number of register rename lookups that rename has made 130system.cpu.rename.int_rename_lookups 15618651087 # Number of integer rename lookups 131system.cpu.rename.fp_rename_lookups 651505277 # Number of floating rename lookups 132system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed 133system.cpu.rename.UndoneMaps 1339817292 # Number of HB maps that are undone due to squashing 134system.cpu.rename.serializingInsts 273156 # count of serializing insts renamed 135system.cpu.rename.tempSerializingInsts 268372 # count of temporary serializing insts renamed 136system.cpu.rename.skidInsts 142469911 # count of insts added to the skid buffer 137system.cpu.memDep0.insertedLoads 1057917040 # Number of loads inserted to the mem dependence unit. 138system.cpu.memDep0.insertedStores 579962844 # Number of stores inserted to the mem dependence unit. 139system.cpu.memDep0.conflictingLoads 32519670 # Number of conflicting loads. 140system.cpu.memDep0.conflictingStores 39211966 # Number of conflicting stores. 141system.cpu.iq.iqInstsAdded 3198933227 # Number of instructions added to the IQ (excludes non-spec) 142system.cpu.iq.iqNonSpecInstsAdded 269334 # Number of non-speculative instructions added to the IQ 143system.cpu.iq.iqInstsIssued 2725360235 # Number of instructions issued 144system.cpu.iq.iqSquashedInstsIssued 26814777 # Number of squashed instructions issued 145system.cpu.iq.iqSquashedInstsExamined 1313459573 # Number of squashed instructions iterated over during squash; mainly for profiling 146system.cpu.iq.iqSquashedOperandsExamined 3048227605 # Number of squashed operands that are examined and possibly removed from graph 147system.cpu.iq.iqSquashedNonSpecRemoved 58004 # Number of squashed non-spec instructions that were removed 148system.cpu.iq.issued_per_cycle::samples 1441668699 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::mean 1.890421 # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::stdev 1.914096 # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::0 524357405 36.37% 36.37% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::1 197522511 13.70% 50.07% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::2 215009168 14.91% 64.99% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::3 179008270 12.42% 77.40% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::4 156604882 10.86% 88.27% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::5 103164450 7.16% 95.42% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::6 49203607 3.41% 98.83% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::7 11056090 0.77% 99.60% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::8 5742316 0.40% 100.00% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::total 1441668699 # Number of insts issued each cycle 165system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 166system.cpu.iq.fu_full::IntAlu 2118699 2.21% 2.21% # attempts to use FU when none available 167system.cpu.iq.fu_full::IntMult 23832 0.02% 2.23% # attempts to use FU when none available 168system.cpu.iq.fu_full::IntDiv 0 0.00% 2.23% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.23% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.23% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.23% # attempts to use FU when none available 172system.cpu.iq.fu_full::FloatMult 0 0.00% 2.23% # attempts to use FU when none available 173system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.23% # attempts to use FU when none available 174system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.23% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.23% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.23% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.23% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.23% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.23% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.23% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdMult 0 0.00% 2.23% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.23% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdShift 0 0.00% 2.23% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.23% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.23% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.23% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.23% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.23% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.23% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.23% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.23% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.23% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.23% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.23% # attempts to use FU when none available 195system.cpu.iq.fu_full::MemRead 56614089 59.02% 61.26% # attempts to use FU when none available 196system.cpu.iq.fu_full::MemWrite 37163288 38.74% 100.00% # attempts to use FU when none available 197system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 198system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 199system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 200system.cpu.iq.FU_type_0::IntAlu 1266333715 46.46% 46.46% # Type of FU issued 201system.cpu.iq.FU_type_0::IntMult 11230148 0.41% 46.88% # Type of FU issued 202system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued 206system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued 207system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued 208system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatCmp 6876563 0.25% 47.18% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatCvt 5503497 0.20% 47.38% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatDiv 38 0.00% 47.38% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatMisc 23211520 0.85% 48.23% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.23% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.23% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.23% # Type of FU issued 229system.cpu.iq.FU_type_0::MemRead 900219934 33.03% 81.26% # Type of FU issued 230system.cpu.iq.FU_type_0::MemWrite 510609530 18.74% 100.00% # Type of FU issued 231system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 232system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 233system.cpu.iq.FU_type_0::total 2725360235 # Type of FU issued 234system.cpu.iq.rate 1.850502 # Inst issue rate 235system.cpu.iq.fu_busy_cnt 95919908 # FU busy when requested 236system.cpu.iq.fu_busy_rate 0.035195 # FU busy rate (busy events/executed inst) 237system.cpu.iq.int_inst_queue_reads 6880679936 # Number of integer instruction queue reads 238system.cpu.iq.int_inst_queue_writes 4410033557 # Number of integer instruction queue writes 239system.cpu.iq.int_inst_queue_wakeup_accesses 2496172626 # Number of integer instruction queue wakeup accesses 240system.cpu.iq.fp_inst_queue_reads 134443918 # Number of floating instruction queue reads 241system.cpu.iq.fp_inst_queue_writes 102684223 # Number of floating instruction queue writes 242system.cpu.iq.fp_inst_queue_wakeup_accesses 60255652 # Number of floating instruction queue wakeup accesses 243system.cpu.iq.int_alu_accesses 2752299483 # Number of integer alu accesses 244system.cpu.iq.fp_alu_accesses 68980660 # Number of floating point alu accesses 245system.cpu.iew.lsq.thread0.forwLoads 71230775 # Number of loads that had data forwarded from stores 246system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 247system.cpu.iew.lsq.thread0.squashedLoads 426528171 # Number of loads squashed 248system.cpu.iew.lsq.thread0.ignoredResponses 281369 # Number of memory responses ignored because the instruction is squashed 249system.cpu.iew.lsq.thread0.memOrderViolation 1323673 # Number of memory ordering violations 250system.cpu.iew.lsq.thread0.squashedStores 302965860 # Number of stores squashed 251system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 252system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 253system.cpu.iew.lsq.thread0.rescheduledLoads 92 # Number of loads that were rescheduled 254system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked 255system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 256system.cpu.iew.iewSquashCycles 183414346 # Number of cycles IEW is squashing 257system.cpu.iew.iewBlockCycles 16249953 # Number of cycles IEW is blocking 258system.cpu.iew.iewUnblockCycles 1608700 # Number of cycles IEW is unblocking 259system.cpu.iew.iewDispatchedInsts 3199274316 # Number of instructions dispatched to IQ 260system.cpu.iew.iewDispSquashedInsts 7370103 # Number of squashed instructions skipped by dispatch 261system.cpu.iew.iewDispLoadInsts 1057917040 # Number of dispatched load instructions 262system.cpu.iew.iewDispStoreInsts 579962844 # Number of dispatched store instructions 263system.cpu.iew.iewDispNonSpecInsts 258370 # Number of dispatched non-speculative instructions 264system.cpu.iew.iewIQFullEvents 1607775 # Number of times the IQ has become full, causing a stall 265system.cpu.iew.iewLSQFullEvents 215 # Number of times the LSQ has become full, causing a stall 266system.cpu.iew.memOrderViolationEvents 1323673 # Number of memory order violations 267system.cpu.iew.predictedTakenIncorrect 37204877 # Number of branches that were predicted taken incorrectly 268system.cpu.iew.predictedNotTakenIncorrect 8928711 # Number of branches that were predicted not taken incorrectly 269system.cpu.iew.branchMispredicts 46133588 # Number of branch mispredicts detected at execute 270system.cpu.iew.iewExecutedInsts 2624820303 # Number of executed instructions 271system.cpu.iew.iewExecLoadInsts 845791055 # Number of load instructions executed 272system.cpu.iew.iewExecSquashedInsts 100539932 # Number of squashed instructions skipped in execute 273system.cpu.iew.exec_swp 0 # number of swp insts executed 274system.cpu.iew.exec_nop 71755 # number of nop insts executed 275system.cpu.iew.exec_refs 1327328363 # number of memory reference insts executed 276system.cpu.iew.exec_branches 362158100 # Number of branches executed 277system.cpu.iew.exec_stores 481537308 # Number of stores executed 278system.cpu.iew.exec_rate 1.782236 # Inst execution rate 279system.cpu.iew.wb_sent 2584846968 # cumulative count of insts sent to commit 280system.cpu.iew.wb_count 2556428278 # cumulative count of insts written-back 281system.cpu.iew.wb_producers 1474733618 # num instructions producing a value 282system.cpu.iew.wb_consumers 2760579704 # num instructions consuming a value 283system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 284system.cpu.iew.wb_rate 1.735798 # insts written-back per cycle 285system.cpu.iew.wb_fanout 0.534212 # average fanout of values written-back 286system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 287system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions 288system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions 289system.cpu.commit.commitSquashedInsts 1313929852 # The number of squashed insts skipped by commit 290system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards 291system.cpu.commit.branchMispredicts 41115032 # The number of times a branch was mispredicted 292system.cpu.commit.committed_per_cycle::samples 1258254355 # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::mean 1.498381 # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::stdev 2.211057 # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::0 578553729 45.98% 45.98% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::1 316892144 25.19% 71.17% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::2 101707631 8.08% 79.25% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::3 79187361 6.29% 85.54% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::4 52970249 4.21% 89.75% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::5 24190672 1.92% 91.67% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::6 17058373 1.36% 93.03% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::7 9262849 0.74% 93.77% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::8 78431347 6.23% 100.00% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::total 1258254355 # Number of insts commited each cycle 309system.cpu.commit.committedInsts 1384390049 # Number of instructions committed 310system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed 311system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 312system.cpu.commit.refs 908385853 # Number of memory references committed 313system.cpu.commit.loads 631388869 # Number of loads committed 314system.cpu.commit.membars 9986 # Number of memory barriers committed 315system.cpu.commit.branches 291350232 # Number of branches committed 316system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. 317system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions. 318system.cpu.commit.function_calls 41577833 # Number of function calls committed. 319system.cpu.commit.bw_lim_events 78431347 # number cycles where commit BW limit reached 320system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 321system.cpu.rob.rob_reads 4379079317 # The number of ROB reads 322system.cpu.rob.rob_writes 6581974646 # The number of ROB writes 323system.cpu.timesIdled 1328714 # Number of times that the entire CPU went into an idle state and unscheduled itself 324system.cpu.idleCycles 31099710 # Total number of cycles that the CPU has spent unscheduled due to idling 325system.cpu.committedInsts 1384379033 # Number of Instructions Simulated 326system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated 327system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated 328system.cpu.cpi 1.063848 # CPI: Cycles Per Instruction 329system.cpu.cpi_total 1.063848 # CPI: Total CPI of All Threads 330system.cpu.ipc 0.939984 # IPC: Instructions Per Cycle 331system.cpu.ipc_total 0.939984 # IPC: Total IPC of All Threads 332system.cpu.int_regfile_reads 12935043618 # number of integer regfile reads 333system.cpu.int_regfile_writes 2425775909 # number of integer regfile writes 334system.cpu.fp_regfile_reads 71439411 # number of floating regfile reads 335system.cpu.fp_regfile_writes 51051626 # number of floating regfile writes 336system.cpu.misc_regfile_reads 4084910091 # number of misc regfile reads 337system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes 338system.cpu.icache.replacements 28501 # number of replacements 339system.cpu.icache.tagsinuse 1662.292931 # Cycle average of tags in use 340system.cpu.icache.total_refs 415426412 # Total number of references to valid blocks. 341system.cpu.icache.sampled_refs 30198 # Sample count of references to valid blocks. 342system.cpu.icache.avg_refs 13756.752500 # Average number of references to valid blocks. 343system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 344system.cpu.icache.occ_blocks::cpu.inst 1662.292931 # Average occupied blocks per requestor 345system.cpu.icache.occ_percent::cpu.inst 0.811666 # Average percentage of cache occupancy 346system.cpu.icache.occ_percent::total 0.811666 # Average percentage of cache occupancy 347system.cpu.icache.ReadReq_hits::cpu.inst 415426419 # number of ReadReq hits 348system.cpu.icache.ReadReq_hits::total 415426419 # number of ReadReq hits 349system.cpu.icache.demand_hits::cpu.inst 415426419 # number of demand (read+write) hits 350system.cpu.icache.demand_hits::total 415426419 # number of demand (read+write) hits 351system.cpu.icache.overall_hits::cpu.inst 415426419 # number of overall hits 352system.cpu.icache.overall_hits::total 415426419 # number of overall hits 353system.cpu.icache.ReadReq_misses::cpu.inst 35960 # number of ReadReq misses 354system.cpu.icache.ReadReq_misses::total 35960 # number of ReadReq misses 355system.cpu.icache.demand_misses::cpu.inst 35960 # number of demand (read+write) misses 356system.cpu.icache.demand_misses::total 35960 # number of demand (read+write) misses 357system.cpu.icache.overall_misses::cpu.inst 35960 # number of overall misses 358system.cpu.icache.overall_misses::total 35960 # number of overall misses 359system.cpu.icache.ReadReq_miss_latency::cpu.inst 314726500 # number of ReadReq miss cycles 360system.cpu.icache.ReadReq_miss_latency::total 314726500 # number of ReadReq miss cycles 361system.cpu.icache.demand_miss_latency::cpu.inst 314726500 # number of demand (read+write) miss cycles 362system.cpu.icache.demand_miss_latency::total 314726500 # number of demand (read+write) miss cycles 363system.cpu.icache.overall_miss_latency::cpu.inst 314726500 # number of overall miss cycles 364system.cpu.icache.overall_miss_latency::total 314726500 # number of overall miss cycles 365system.cpu.icache.ReadReq_accesses::cpu.inst 415462379 # number of ReadReq accesses(hits+misses) 366system.cpu.icache.ReadReq_accesses::total 415462379 # number of ReadReq accesses(hits+misses) 367system.cpu.icache.demand_accesses::cpu.inst 415462379 # number of demand (read+write) accesses 368system.cpu.icache.demand_accesses::total 415462379 # number of demand (read+write) accesses 369system.cpu.icache.overall_accesses::cpu.inst 415462379 # number of overall (read+write) accesses 370system.cpu.icache.overall_accesses::total 415462379 # number of overall (read+write) accesses 371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses 372system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses 373system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses 374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8752.127364 # average ReadReq miss latency 375system.cpu.icache.demand_avg_miss_latency::cpu.inst 8752.127364 # average overall miss latency 376system.cpu.icache.overall_avg_miss_latency::cpu.inst 8752.127364 # average overall miss latency 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 381system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 382system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 383system.cpu.icache.fast_writes 0 # number of fast writes performed 384system.cpu.icache.cache_copies 0 # number of cache copies performed 385system.cpu.icache.ReadReq_mshr_hits::cpu.inst 780 # number of ReadReq MSHR hits 386system.cpu.icache.ReadReq_mshr_hits::total 780 # number of ReadReq MSHR hits 387system.cpu.icache.demand_mshr_hits::cpu.inst 780 # number of demand (read+write) MSHR hits 388system.cpu.icache.demand_mshr_hits::total 780 # number of demand (read+write) MSHR hits 389system.cpu.icache.overall_mshr_hits::cpu.inst 780 # number of overall MSHR hits 390system.cpu.icache.overall_mshr_hits::total 780 # number of overall MSHR hits 391system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35180 # number of ReadReq MSHR misses 392system.cpu.icache.ReadReq_mshr_misses::total 35180 # number of ReadReq MSHR misses 393system.cpu.icache.demand_mshr_misses::cpu.inst 35180 # number of demand (read+write) MSHR misses 394system.cpu.icache.demand_mshr_misses::total 35180 # number of demand (read+write) MSHR misses 395system.cpu.icache.overall_mshr_misses::cpu.inst 35180 # number of overall MSHR misses 396system.cpu.icache.overall_mshr_misses::total 35180 # number of overall MSHR misses 397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 188682500 # number of ReadReq MSHR miss cycles 398system.cpu.icache.ReadReq_mshr_miss_latency::total 188682500 # number of ReadReq MSHR miss cycles 399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 188682500 # number of demand (read+write) MSHR miss cycles 400system.cpu.icache.demand_mshr_miss_latency::total 188682500 # number of demand (read+write) MSHR miss cycles 401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 188682500 # number of overall MSHR miss cycles 402system.cpu.icache.overall_mshr_miss_latency::total 188682500 # number of overall MSHR miss cycles 403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses 404system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses 405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses 406system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5363.345651 # average ReadReq mshr miss latency 407system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5363.345651 # average overall mshr miss latency 408system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5363.345651 # average overall mshr miss latency 409system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 410system.cpu.dcache.replacements 1532334 # number of replacements 411system.cpu.dcache.tagsinuse 4094.808393 # Cycle average of tags in use 412system.cpu.dcache.total_refs 1033081236 # Total number of references to valid blocks. 413system.cpu.dcache.sampled_refs 1536430 # Sample count of references to valid blocks. 414system.cpu.dcache.avg_refs 672.390695 # Average number of references to valid blocks. 415system.cpu.dcache.warmup_cycle 312649000 # Cycle when the warmup percentage was hit. 416system.cpu.dcache.occ_blocks::cpu.data 4094.808393 # Average occupied blocks per requestor 417system.cpu.dcache.occ_percent::cpu.data 0.999709 # Average percentage of cache occupancy 418system.cpu.dcache.occ_percent::total 0.999709 # Average percentage of cache occupancy 419system.cpu.dcache.ReadReq_hits::cpu.data 756924525 # number of ReadReq hits 420system.cpu.dcache.ReadReq_hits::total 756924525 # number of ReadReq hits 421system.cpu.dcache.WriteReq_hits::cpu.data 276114347 # number of WriteReq hits 422system.cpu.dcache.WriteReq_hits::total 276114347 # number of WriteReq hits 423system.cpu.dcache.LoadLockedReq_hits::cpu.data 12957 # number of LoadLockedReq hits 424system.cpu.dcache.LoadLockedReq_hits::total 12957 # number of LoadLockedReq hits 425system.cpu.dcache.StoreCondReq_hits::cpu.data 11669 # number of StoreCondReq hits 426system.cpu.dcache.StoreCondReq_hits::total 11669 # number of StoreCondReq hits 427system.cpu.dcache.demand_hits::cpu.data 1033038872 # number of demand (read+write) hits 428system.cpu.dcache.demand_hits::total 1033038872 # number of demand (read+write) hits 429system.cpu.dcache.overall_hits::cpu.data 1033038872 # number of overall hits 430system.cpu.dcache.overall_hits::total 1033038872 # number of overall hits 431system.cpu.dcache.ReadReq_misses::cpu.data 2432909 # number of ReadReq misses 432system.cpu.dcache.ReadReq_misses::total 2432909 # number of ReadReq misses 433system.cpu.dcache.WriteReq_misses::cpu.data 821331 # number of WriteReq misses 434system.cpu.dcache.WriteReq_misses::total 821331 # number of WriteReq misses 435system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 436system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 437system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses 438system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses 439system.cpu.dcache.demand_misses::cpu.data 3254240 # number of demand (read+write) misses 440system.cpu.dcache.demand_misses::total 3254240 # number of demand (read+write) misses 441system.cpu.dcache.overall_misses::cpu.data 3254240 # number of overall misses 442system.cpu.dcache.overall_misses::total 3254240 # number of overall misses 443system.cpu.dcache.ReadReq_miss_latency::cpu.data 81657017500 # number of ReadReq miss cycles 444system.cpu.dcache.ReadReq_miss_latency::total 81657017500 # number of ReadReq miss cycles 445system.cpu.dcache.WriteReq_miss_latency::cpu.data 28588903000 # number of WriteReq miss cycles 446system.cpu.dcache.WriteReq_miss_latency::total 28588903000 # number of WriteReq miss cycles 447system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 108000 # number of LoadLockedReq miss cycles 448system.cpu.dcache.LoadLockedReq_miss_latency::total 108000 # number of LoadLockedReq miss cycles 449system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 16500 # number of StoreCondReq miss cycles 450system.cpu.dcache.StoreCondReq_miss_latency::total 16500 # number of StoreCondReq miss cycles 451system.cpu.dcache.demand_miss_latency::cpu.data 110245920500 # number of demand (read+write) miss cycles 452system.cpu.dcache.demand_miss_latency::total 110245920500 # number of demand (read+write) miss cycles 453system.cpu.dcache.overall_miss_latency::cpu.data 110245920500 # number of overall miss cycles 454system.cpu.dcache.overall_miss_latency::total 110245920500 # number of overall miss cycles 455system.cpu.dcache.ReadReq_accesses::cpu.data 759357434 # number of ReadReq accesses(hits+misses) 456system.cpu.dcache.ReadReq_accesses::total 759357434 # number of ReadReq accesses(hits+misses) 457system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) 458system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 459system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12960 # number of LoadLockedReq accesses(hits+misses) 460system.cpu.dcache.LoadLockedReq_accesses::total 12960 # number of LoadLockedReq accesses(hits+misses) 461system.cpu.dcache.StoreCondReq_accesses::cpu.data 11672 # number of StoreCondReq accesses(hits+misses) 462system.cpu.dcache.StoreCondReq_accesses::total 11672 # number of StoreCondReq accesses(hits+misses) 463system.cpu.dcache.demand_accesses::cpu.data 1036293112 # number of demand (read+write) accesses 464system.cpu.dcache.demand_accesses::total 1036293112 # number of demand (read+write) accesses 465system.cpu.dcache.overall_accesses::cpu.data 1036293112 # number of overall (read+write) accesses 466system.cpu.dcache.overall_accesses::total 1036293112 # number of overall (read+write) accesses 467system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003204 # miss rate for ReadReq accesses 468system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002966 # miss rate for WriteReq accesses 469system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000231 # miss rate for LoadLockedReq accesses 470system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000257 # miss rate for StoreCondReq accesses 471system.cpu.dcache.demand_miss_rate::cpu.data 0.003140 # miss rate for demand accesses 472system.cpu.dcache.overall_miss_rate::cpu.data 0.003140 # miss rate for overall accesses 473system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33563.531353 # average ReadReq miss latency 474system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34808.016500 # average WriteReq miss latency 475system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36000 # average LoadLockedReq miss latency 476system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 5500 # average StoreCondReq miss latency 477system.cpu.dcache.demand_avg_miss_latency::cpu.data 33877.624422 # average overall miss latency 478system.cpu.dcache.overall_avg_miss_latency::cpu.data 33877.624422 # average overall miss latency 479system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 480system.cpu.dcache.blocked_cycles::no_targets 80000 # number of cycles access was blocked 481system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 482system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 483system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 484system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked 485system.cpu.dcache.fast_writes 0 # number of fast writes performed 486system.cpu.dcache.cache_copies 0 # number of cache copies performed 487system.cpu.dcache.writebacks::writebacks 106562 # number of writebacks 488system.cpu.dcache.writebacks::total 106562 # number of writebacks 489system.cpu.dcache.ReadReq_mshr_hits::cpu.data 969189 # number of ReadReq MSHR hits 490system.cpu.dcache.ReadReq_mshr_hits::total 969189 # number of ReadReq MSHR hits 491system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743643 # number of WriteReq MSHR hits 492system.cpu.dcache.WriteReq_mshr_hits::total 743643 # number of WriteReq MSHR hits 493system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 494system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 495system.cpu.dcache.demand_mshr_hits::cpu.data 1712832 # number of demand (read+write) MSHR hits 496system.cpu.dcache.demand_mshr_hits::total 1712832 # number of demand (read+write) MSHR hits 497system.cpu.dcache.overall_mshr_hits::cpu.data 1712832 # number of overall MSHR hits 498system.cpu.dcache.overall_mshr_hits::total 1712832 # number of overall MSHR hits 499system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463720 # number of ReadReq MSHR misses 500system.cpu.dcache.ReadReq_mshr_misses::total 1463720 # number of ReadReq MSHR misses 501system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77688 # number of WriteReq MSHR misses 502system.cpu.dcache.WriteReq_mshr_misses::total 77688 # number of WriteReq MSHR misses 503system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses 504system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses 505system.cpu.dcache.demand_mshr_misses::cpu.data 1541408 # number of demand (read+write) MSHR misses 506system.cpu.dcache.demand_mshr_misses::total 1541408 # number of demand (read+write) MSHR misses 507system.cpu.dcache.overall_mshr_misses::cpu.data 1541408 # number of overall MSHR misses 508system.cpu.dcache.overall_mshr_misses::total 1541408 # number of overall MSHR misses 509system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029308500 # number of ReadReq MSHR miss cycles 510system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029308500 # number of ReadReq MSHR miss cycles 511system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2504136000 # number of WriteReq MSHR miss cycles 512system.cpu.dcache.WriteReq_mshr_miss_latency::total 2504136000 # number of WriteReq MSHR miss cycles 513system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 7500 # number of StoreCondReq MSHR miss cycles 514system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 7500 # number of StoreCondReq MSHR miss cycles 515system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52533444500 # number of demand (read+write) MSHR miss cycles 516system.cpu.dcache.demand_mshr_miss_latency::total 52533444500 # number of demand (read+write) MSHR miss cycles 517system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52533444500 # number of overall MSHR miss cycles 518system.cpu.dcache.overall_mshr_miss_latency::total 52533444500 # number of overall MSHR miss cycles 519system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses 520system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000281 # mshr miss rate for WriteReq accesses 521system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000257 # mshr miss rate for StoreCondReq accesses 522system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for demand accesses 523system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for overall accesses 524system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34179.562006 # average ReadReq mshr miss latency 525system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32233.240655 # average WriteReq mshr miss latency 526system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 2500 # average StoreCondReq mshr miss latency 527system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34081.466101 # average overall mshr miss latency 528system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34081.466101 # average overall mshr miss latency 529system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 530system.cpu.l2cache.replacements 1480213 # number of replacements 531system.cpu.l2cache.tagsinuse 31972.758917 # Cycle average of tags in use 532system.cpu.l2cache.total_refs 86473 # Total number of references to valid blocks. 533system.cpu.l2cache.sampled_refs 1512931 # Sample count of references to valid blocks. 534system.cpu.l2cache.avg_refs 0.057156 # Average number of references to valid blocks. 535system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 536system.cpu.l2cache.occ_blocks::writebacks 2964.503438 # Average occupied blocks per requestor 537system.cpu.l2cache.occ_blocks::cpu.inst 60.794216 # Average occupied blocks per requestor 538system.cpu.l2cache.occ_blocks::cpu.data 28947.461262 # Average occupied blocks per requestor 539system.cpu.l2cache.occ_percent::writebacks 0.090469 # Average percentage of cache occupancy 540system.cpu.l2cache.occ_percent::cpu.inst 0.001855 # Average percentage of cache occupancy 541system.cpu.l2cache.occ_percent::cpu.data 0.883406 # Average percentage of cache occupancy 542system.cpu.l2cache.occ_percent::total 0.975731 # Average percentage of cache occupancy 543system.cpu.l2cache.ReadReq_hits::cpu.inst 26928 # number of ReadReq hits 544system.cpu.l2cache.ReadReq_hits::cpu.data 51269 # number of ReadReq hits 545system.cpu.l2cache.ReadReq_hits::total 78197 # number of ReadReq hits 546system.cpu.l2cache.Writeback_hits::writebacks 106562 # number of Writeback hits 547system.cpu.l2cache.Writeback_hits::total 106562 # number of Writeback hits 548system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 549system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 550system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 551system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 552system.cpu.l2cache.ReadExReq_hits::cpu.data 6630 # number of ReadExReq hits 553system.cpu.l2cache.ReadExReq_hits::total 6630 # number of ReadExReq hits 554system.cpu.l2cache.demand_hits::cpu.inst 26928 # number of demand (read+write) hits 555system.cpu.l2cache.demand_hits::cpu.data 57899 # number of demand (read+write) hits 556system.cpu.l2cache.demand_hits::total 84827 # number of demand (read+write) hits 557system.cpu.l2cache.overall_hits::cpu.inst 26928 # number of overall hits 558system.cpu.l2cache.overall_hits::cpu.data 57899 # number of overall hits 559system.cpu.l2cache.overall_hits::total 84827 # number of overall hits 560system.cpu.l2cache.ReadReq_misses::cpu.inst 3274 # number of ReadReq misses 561system.cpu.l2cache.ReadReq_misses::cpu.data 1412451 # number of ReadReq misses 562system.cpu.l2cache.ReadReq_misses::total 1415725 # number of ReadReq misses 563system.cpu.l2cache.UpgradeReq_misses::cpu.data 4973 # number of UpgradeReq misses 564system.cpu.l2cache.UpgradeReq_misses::total 4973 # number of UpgradeReq misses 565system.cpu.l2cache.ReadExReq_misses::cpu.data 66080 # number of ReadExReq misses 566system.cpu.l2cache.ReadExReq_misses::total 66080 # number of ReadExReq misses 567system.cpu.l2cache.demand_misses::cpu.inst 3274 # number of demand (read+write) misses 568system.cpu.l2cache.demand_misses::cpu.data 1478531 # number of demand (read+write) misses 569system.cpu.l2cache.demand_misses::total 1481805 # number of demand (read+write) misses 570system.cpu.l2cache.overall_misses::cpu.inst 3274 # number of overall misses 571system.cpu.l2cache.overall_misses::cpu.data 1478531 # number of overall misses 572system.cpu.l2cache.overall_misses::total 1481805 # number of overall misses 573system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 112237000 # number of ReadReq miss cycles 574system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48455418000 # number of ReadReq miss cycles 575system.cpu.l2cache.ReadReq_miss_latency::total 48567655000 # number of ReadReq miss cycles 576system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252377500 # number of ReadExReq miss cycles 577system.cpu.l2cache.ReadExReq_miss_latency::total 2252377500 # number of ReadExReq miss cycles 578system.cpu.l2cache.demand_miss_latency::cpu.inst 112237000 # number of demand (read+write) miss cycles 579system.cpu.l2cache.demand_miss_latency::cpu.data 50707795500 # number of demand (read+write) miss cycles 580system.cpu.l2cache.demand_miss_latency::total 50820032500 # number of demand (read+write) miss cycles 581system.cpu.l2cache.overall_miss_latency::cpu.inst 112237000 # number of overall miss cycles 582system.cpu.l2cache.overall_miss_latency::cpu.data 50707795500 # number of overall miss cycles 583system.cpu.l2cache.overall_miss_latency::total 50820032500 # number of overall miss cycles 584system.cpu.l2cache.ReadReq_accesses::cpu.inst 30202 # number of ReadReq accesses(hits+misses) 585system.cpu.l2cache.ReadReq_accesses::cpu.data 1463720 # number of ReadReq accesses(hits+misses) 586system.cpu.l2cache.ReadReq_accesses::total 1493922 # number of ReadReq accesses(hits+misses) 587system.cpu.l2cache.Writeback_accesses::writebacks 106562 # number of Writeback accesses(hits+misses) 588system.cpu.l2cache.Writeback_accesses::total 106562 # number of Writeback accesses(hits+misses) 589system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4978 # number of UpgradeReq accesses(hits+misses) 590system.cpu.l2cache.UpgradeReq_accesses::total 4978 # number of UpgradeReq accesses(hits+misses) 591system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses) 592system.cpu.l2cache.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) 593system.cpu.l2cache.ReadExReq_accesses::cpu.data 72710 # number of ReadExReq accesses(hits+misses) 594system.cpu.l2cache.ReadExReq_accesses::total 72710 # number of ReadExReq accesses(hits+misses) 595system.cpu.l2cache.demand_accesses::cpu.inst 30202 # number of demand (read+write) accesses 596system.cpu.l2cache.demand_accesses::cpu.data 1536430 # number of demand (read+write) accesses 597system.cpu.l2cache.demand_accesses::total 1566632 # number of demand (read+write) accesses 598system.cpu.l2cache.overall_accesses::cpu.inst 30202 # number of overall (read+write) accesses 599system.cpu.l2cache.overall_accesses::cpu.data 1536430 # number of overall (read+write) accesses 600system.cpu.l2cache.overall_accesses::total 1566632 # number of overall (read+write) accesses 601system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108403 # miss rate for ReadReq accesses 602system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964973 # miss rate for ReadReq accesses 603system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.998996 # miss rate for UpgradeReq accesses 604system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908816 # miss rate for ReadExReq accesses 605system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108403 # miss rate for demand accesses 606system.cpu.l2cache.demand_miss_rate::cpu.data 0.962316 # miss rate for demand accesses 607system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108403 # miss rate for overall accesses 608system.cpu.l2cache.overall_miss_rate::cpu.data 0.962316 # miss rate for overall accesses 609system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34281.307269 # average ReadReq miss latency 610system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34305.910789 # average ReadReq miss latency 611system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.615920 # average ReadExReq miss latency 612system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34281.307269 # average overall miss latency 613system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.065148 # average overall miss latency 614system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34281.307269 # average overall miss latency 615system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.065148 # average overall miss latency 616system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 617system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 618system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 619system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 620system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 621system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 622system.cpu.l2cache.fast_writes 0 # number of fast writes performed 623system.cpu.l2cache.cache_copies 0 # number of cache copies performed 624system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks 625system.cpu.l2cache.writebacks::total 66099 # number of writebacks 626system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 627system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits 628system.cpu.l2cache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits 629system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 630system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits 631system.cpu.l2cache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits 632system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 633system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits 634system.cpu.l2cache.overall_mshr_hits::total 31 # number of overall MSHR hits 635system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3269 # number of ReadReq MSHR misses 636system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412425 # number of ReadReq MSHR misses 637system.cpu.l2cache.ReadReq_mshr_misses::total 1415694 # number of ReadReq MSHR misses 638system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4973 # number of UpgradeReq MSHR misses 639system.cpu.l2cache.UpgradeReq_mshr_misses::total 4973 # number of UpgradeReq MSHR misses 640system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses 641system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses 642system.cpu.l2cache.demand_mshr_misses::cpu.inst 3269 # number of demand (read+write) MSHR misses 643system.cpu.l2cache.demand_mshr_misses::cpu.data 1478505 # number of demand (read+write) MSHR misses 644system.cpu.l2cache.demand_mshr_misses::total 1481774 # number of demand (read+write) MSHR misses 645system.cpu.l2cache.overall_mshr_misses::cpu.inst 3269 # number of overall MSHR misses 646system.cpu.l2cache.overall_mshr_misses::cpu.data 1478505 # number of overall MSHR misses 647system.cpu.l2cache.overall_mshr_misses::total 1481774 # number of overall MSHR misses 648system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101602500 # number of ReadReq MSHR miss cycles 649system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43882479500 # number of ReadReq MSHR miss cycles 650system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43984082000 # number of ReadReq MSHR miss cycles 651system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 154163000 # number of UpgradeReq MSHR miss cycles 652system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 154163000 # number of UpgradeReq MSHR miss cycles 653system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048540000 # number of ReadExReq MSHR miss cycles 654system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048540000 # number of ReadExReq MSHR miss cycles 655system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101602500 # number of demand (read+write) MSHR miss cycles 656system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931019500 # number of demand (read+write) MSHR miss cycles 657system.cpu.l2cache.demand_mshr_miss_latency::total 46032622000 # number of demand (read+write) MSHR miss cycles 658system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101602500 # number of overall MSHR miss cycles 659system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931019500 # number of overall MSHR miss cycles 660system.cpu.l2cache.overall_mshr_miss_latency::total 46032622000 # number of overall MSHR miss cycles 661system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for ReadReq accesses 662system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964956 # mshr miss rate for ReadReq accesses 663system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998996 # mshr miss rate for UpgradeReq accesses 664system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908816 # mshr miss rate for ReadExReq accesses 665system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for demand accesses 666system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962299 # mshr miss rate for demand accesses 667system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for overall accesses 668system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962299 # mshr miss rate for overall accesses 669system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.605690 # average ReadReq mshr miss latency 670system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.891800 # average ReadReq mshr miss latency 671system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 672system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.907990 # average ReadExReq mshr miss latency 673system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency 674system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency 675system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency 676system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency 677system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 678 679---------- End Simulation Statistics ---------- 680