stats.txt revision 10892:bd37e25fb3b7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.410927 # Number of seconds simulated 4sim_ticks 410926760000 # Number of ticks simulated 5final_tick 410926760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 92513 # Simulator instruction rate (inst/s) 8host_op_rate 113896 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59339858 # Simulator tick rate (ticks/s) 10host_mem_usage 320156 # Number of bytes of host memory used 11host_seconds 6924.97 # Real time elapsed on the host 12sim_insts 640649299 # Number of instructions simulated 13sim_ops 788724958 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 227008 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7012480 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 12950080 # Number of bytes read from this memory 19system.physmem.bytes_read::total 20189568 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 227008 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 227008 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4245632 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4245632 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 3547 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 109570 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 202345 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 315462 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 66338 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 66338 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 552429 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 17065036 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 31514326 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 49131792 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 552429 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 552429 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 10331846 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 10331846 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 10331846 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 552429 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 17065036 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 31514326 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 59463638 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 315462 # Number of read requests accepted 44system.physmem.writeReqs 66338 # Number of write requests accepted 45system.physmem.readBursts 315462 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 66338 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 20169664 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue 49system.physmem.bytesWritten 4239360 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 20189568 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 4245632 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 69 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 19798 # Per bank write bursts 56system.physmem.perBankRdBursts::1 19540 # Per bank write bursts 57system.physmem.perBankRdBursts::2 19718 # Per bank write bursts 58system.physmem.perBankRdBursts::3 19803 # Per bank write bursts 59system.physmem.perBankRdBursts::4 19742 # Per bank write bursts 60system.physmem.perBankRdBursts::5 20227 # Per bank write bursts 61system.physmem.perBankRdBursts::6 19591 # Per bank write bursts 62system.physmem.perBankRdBursts::7 19445 # Per bank write bursts 63system.physmem.perBankRdBursts::8 19492 # Per bank write bursts 64system.physmem.perBankRdBursts::9 19431 # Per bank write bursts 65system.physmem.perBankRdBursts::10 19416 # Per bank write bursts 66system.physmem.perBankRdBursts::11 19789 # Per bank write bursts 67system.physmem.perBankRdBursts::12 19620 # Per bank write bursts 68system.physmem.perBankRdBursts::13 20020 # Per bank write bursts 69system.physmem.perBankRdBursts::14 19553 # Per bank write bursts 70system.physmem.perBankRdBursts::15 19966 # Per bank write bursts 71system.physmem.perBankWrBursts::0 4272 # Per bank write bursts 72system.physmem.perBankWrBursts::1 4105 # Per bank write bursts 73system.physmem.perBankWrBursts::2 4143 # Per bank write bursts 74system.physmem.perBankWrBursts::3 4154 # Per bank write bursts 75system.physmem.perBankWrBursts::4 4243 # Per bank write bursts 76system.physmem.perBankWrBursts::5 4228 # Per bank write bursts 77system.physmem.perBankWrBursts::6 4173 # Per bank write bursts 78system.physmem.perBankWrBursts::7 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 80system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 83system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 84system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 85system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 86system.physmem.perBankWrBursts::15 4151 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 410926705500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 315462 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 66338 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 125674 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 115954 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 14051 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 6709 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6515 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 7602 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 8811 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 9422 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 8719 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 4043 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 2949 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 2148 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1569 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 985 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 601 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 630 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 952 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 1710 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2550 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 3275 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 3782 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 4094 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 4378 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 4658 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 4986 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 5149 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 5206 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 5156 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 4978 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 4222 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 4108 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 4056 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 115 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 98 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 88 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 90 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 104 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 74 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 69 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 75 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 60 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 62 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 57 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 57 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 50 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 6 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 136743 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 178.487469 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 128.645908 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 198.261259 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 54158 39.61% 39.61% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 57478 42.03% 81.64% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 14696 10.75% 92.39% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1431 1.05% 93.43% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1373 1.00% 94.44% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 1481 1.08% 95.52% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1196 0.87% 96.39% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1150 0.84% 97.24% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 3780 2.76% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 136743 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 4027 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 66.735038 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 34.718214 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 464.978559 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 3992 99.13% 99.13% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.50% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::1024-1535 4 0.10% 99.60% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::1536-2047 3 0.07% 99.68% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::2048-2559 4 0.10% 99.78% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.80% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::3584-4095 1 0.02% 99.83% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::4608-5119 2 0.05% 99.88% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::5120-5631 1 0.02% 99.90% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::8192-8703 1 0.02% 99.93% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::13824-14335 1 0.02% 99.95% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::14848-15359 2 0.05% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 4027 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 4027 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 16.448969 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 16.407245 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 1.299266 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16 3382 83.98% 83.98% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::17 3 0.07% 84.06% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::18 453 11.25% 95.31% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::19 103 2.56% 97.86% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20 20 0.50% 98.36% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::21 19 0.47% 98.83% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::22 10 0.25% 99.08% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::23 11 0.27% 99.35% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::24 8 0.20% 99.55% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::25 5 0.12% 99.68% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::26 3 0.07% 99.75% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::27 1 0.02% 99.78% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::28 1 0.02% 99.80% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::29 1 0.02% 99.83% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::30 4 0.10% 99.93% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::31 1 0.02% 99.95% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::32 2 0.05% 100.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::total 4027 # Writes before turning the bus around for reads 253system.physmem.totQLat 8985315314 # Total ticks spent queuing 254system.physmem.totMemAccLat 14894396564 # Total ticks spent from burst creation until serviced by the DRAM 255system.physmem.totBusLat 1575755000 # Total ticks spent in databus transfers 256system.physmem.avgQLat 28511.14 # Average queueing delay per DRAM burst 257system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 258system.physmem.avgMemAccLat 47261.14 # Average memory access latency per DRAM burst 259system.physmem.avgRdBW 49.08 # Average DRAM read bandwidth in MiByte/s 260system.physmem.avgWrBW 10.32 # Average achieved write bandwidth in MiByte/s 261system.physmem.avgRdBWSys 49.13 # Average system read bandwidth in MiByte/s 262system.physmem.avgWrBWSys 10.33 # Average system write bandwidth in MiByte/s 263system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 264system.physmem.busUtil 0.46 # Data bus utilization in percentage 265system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads 266system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes 267system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing 268system.physmem.avgWrQLen 25.12 # Average write queue length when enqueuing 269system.physmem.readRowHits 218304 # Number of row buffer hits during reads 270system.physmem.writeRowHits 26331 # Number of row buffer hits during writes 271system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads 272system.physmem.writeRowHitRate 39.73 # Row buffer hit rate for writes 273system.physmem.avgGap 1076287.86 # Average gap between requests 274system.physmem.pageHitRate 64.14 # Row buffer hit rate, read and write combined 275system.physmem_0.actEnergy 518260680 # Energy for activate commands per rank (pJ) 276system.physmem_0.preEnergy 282781125 # Energy for precharge commands per rank (pJ) 277system.physmem_0.readEnergy 1231058400 # Energy for read commands per rank (pJ) 278system.physmem_0.writeEnergy 216522720 # Energy for write commands per rank (pJ) 279system.physmem_0.refreshEnergy 26839254000 # Energy for refresh commands per rank (pJ) 280system.physmem_0.actBackEnergy 96516777600 # Energy for active background per rank (pJ) 281system.physmem_0.preBackEnergy 161887922250 # Energy for precharge background per rank (pJ) 282system.physmem_0.totalEnergy 287492576775 # Total energy per rank (pJ) 283system.physmem_0.averagePower 699.632177 # Core power per rank (mW) 284system.physmem_0.memoryStateTime::IDLE 268678979341 # Time in different power states 285system.physmem_0.memoryStateTime::REF 13721500000 # Time in different power states 286system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 287system.physmem_0.memoryStateTime::ACT 128519138159 # Time in different power states 288system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 289system.physmem_1.actEnergy 515334960 # Energy for activate commands per rank (pJ) 290system.physmem_1.preEnergy 281184750 # Energy for precharge commands per rank (pJ) 291system.physmem_1.readEnergy 1226448600 # Energy for read commands per rank (pJ) 292system.physmem_1.writeEnergy 212712480 # Energy for write commands per rank (pJ) 293system.physmem_1.refreshEnergy 26839254000 # Energy for refresh commands per rank (pJ) 294system.physmem_1.actBackEnergy 96027774030 # Energy for active background per rank (pJ) 295system.physmem_1.preBackEnergy 162316872750 # Energy for precharge background per rank (pJ) 296system.physmem_1.totalEnergy 287419581570 # Total energy per rank (pJ) 297system.physmem_1.averagePower 699.454538 # Core power per rank (mW) 298system.physmem_1.memoryStateTime::IDLE 269400106911 # Time in different power states 299system.physmem_1.memoryStateTime::REF 13721500000 # Time in different power states 300system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 301system.physmem_1.memoryStateTime::ACT 127799659089 # Time in different power states 302system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 303system.cpu.branchPred.lookups 233961600 # Number of BP lookups 304system.cpu.branchPred.condPredicted 161823435 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 15514478 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 121576875 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 108260850 # Number of BTB hits 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 309system.cpu.branchPred.BTBHitPct 89.047239 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 25036809 # Number of times the RAS was used to get a target. 311system.cpu.branchPred.RASInCorrect 1300056 # Number of incorrect RAS predictions. 312system.cpu_clk_domain.clock 500 # Clock period in ticks 313system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 322system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 323system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 324system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 325system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 326system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 327system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 328system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 329system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 330system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 331system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 332system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 333system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 334system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 335system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 336system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 337system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 338system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 339system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 340system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 341system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 342system.cpu.dtb.walker.walks 0 # Table walker walks requested 343system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.inst_hits 0 # ITB inst hits 351system.cpu.dtb.inst_misses 0 # ITB inst misses 352system.cpu.dtb.read_hits 0 # DTB read hits 353system.cpu.dtb.read_misses 0 # DTB read misses 354system.cpu.dtb.write_hits 0 # DTB write hits 355system.cpu.dtb.write_misses 0 # DTB write misses 356system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 357system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 358system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 359system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 360system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 361system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 362system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 363system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 364system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 365system.cpu.dtb.read_accesses 0 # DTB read accesses 366system.cpu.dtb.write_accesses 0 # DTB write accesses 367system.cpu.dtb.inst_accesses 0 # ITB inst accesses 368system.cpu.dtb.hits 0 # DTB hits 369system.cpu.dtb.misses 0 # DTB misses 370system.cpu.dtb.accesses 0 # DTB accesses 371system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 380system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 381system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 382system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 383system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 384system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 385system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 386system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 387system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 388system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 389system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 390system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 391system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 392system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 393system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 394system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 395system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 396system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 397system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 398system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 399system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 400system.cpu.itb.walker.walks 0 # Table walker walks requested 401system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.inst_hits 0 # ITB inst hits 409system.cpu.itb.inst_misses 0 # ITB inst misses 410system.cpu.itb.read_hits 0 # DTB read hits 411system.cpu.itb.read_misses 0 # DTB read misses 412system.cpu.itb.write_hits 0 # DTB write hits 413system.cpu.itb.write_misses 0 # DTB write misses 414system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 415system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 416system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 417system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 418system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 419system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 420system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 421system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 422system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 423system.cpu.itb.read_accesses 0 # DTB read accesses 424system.cpu.itb.write_accesses 0 # DTB write accesses 425system.cpu.itb.inst_accesses 0 # ITB inst accesses 426system.cpu.itb.hits 0 # DTB hits 427system.cpu.itb.misses 0 # DTB misses 428system.cpu.itb.accesses 0 # DTB accesses 429system.cpu.workload.num_syscalls 673 # Number of system calls 430system.cpu.numCycles 821853521 # number of cpu cycles simulated 431system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 432system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 433system.cpu.fetch.icacheStallCycles 85352108 # Number of cycles fetch is stalled on an Icache miss 434system.cpu.fetch.Insts 1200709266 # Number of instructions fetch has processed 435system.cpu.fetch.Branches 233961600 # Number of branches that fetch encountered 436system.cpu.fetch.predictedBranches 133297659 # Number of branches that fetch has predicted taken 437system.cpu.fetch.Cycles 720636600 # Number of cycles fetch has run and was not squashing or blocked 438system.cpu.fetch.SquashCycles 31063377 # Number of cycles fetch has spent squashing 439system.cpu.fetch.MiscStallCycles 2846 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 440system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps 441system.cpu.fetch.IcacheWaitRetryStallCycles 3322 # Number of stall cycles due to full MSHR 442system.cpu.fetch.CacheLines 370706156 # Number of cache lines fetched 443system.cpu.fetch.IcacheSquashes 652600 # Number of outstanding Icache misses that were squashed 444system.cpu.fetch.rateDist::samples 821526595 # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::mean 1.826688 # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::stdev 1.166658 # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::0 139803220 17.02% 17.02% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::1 223204281 27.17% 44.19% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::2 98088574 11.94% 56.13% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::3 360430520 43.87% 100.00% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::total 821526595 # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.branchRate 0.284676 # Number of branch fetches per cycle 457system.cpu.fetch.rate 1.460977 # Number of inst fetches per cycle 458system.cpu.decode.IdleCycles 121268240 # Number of cycles decode is idle 459system.cpu.decode.BlockedCycles 161448420 # Number of cycles decode is blocked 460system.cpu.decode.RunCycles 484660246 # Number of cycles decode is running 461system.cpu.decode.UnblockCycles 38631680 # Number of cycles decode is unblocking 462system.cpu.decode.SquashCycles 15518009 # Number of cycles decode is squashing 463system.cpu.decode.BranchResolved 25181996 # Number of times decode resolved a branch 464system.cpu.decode.BranchMispred 13829 # Number of times decode detected a branch misprediction 465system.cpu.decode.DecodedInsts 1248138563 # Number of instructions handled by decode 466system.cpu.decode.SquashedInsts 39966565 # Number of squashed instructions handled by decode 467system.cpu.rename.SquashCycles 15518009 # Number of cycles rename is squashing 468system.cpu.rename.IdleCycles 178275276 # Number of cycles rename is idle 469system.cpu.rename.BlockCycles 80711720 # Number of cycles rename is blocking 470system.cpu.rename.serializeStallCycles 210548 # count of cycles rename stalled for serializing inst 471system.cpu.rename.RunCycles 464319817 # Number of cycles rename is running 472system.cpu.rename.UnblockCycles 82491225 # Number of cycles rename is unblocking 473system.cpu.rename.RenamedInsts 1190650018 # Number of instructions processed by rename 474system.cpu.rename.SquashedInsts 25545971 # Number of squashed instructions processed by rename 475system.cpu.rename.ROBFullEvents 24926226 # Number of times rename has blocked due to ROB full 476system.cpu.rename.IQFullEvents 2267555 # Number of times rename has blocked due to IQ full 477system.cpu.rename.LQFullEvents 41530027 # Number of times rename has blocked due to LQ full 478system.cpu.rename.SQFullEvents 1673344 # Number of times rename has blocked due to SQ full 479system.cpu.rename.RenamedOperands 1225393242 # Number of destination operands rename has renamed 480system.cpu.rename.RenameLookups 5812447453 # Number of register rename lookups that rename has made 481system.cpu.rename.int_rename_lookups 1358179782 # Number of integer rename lookups 482system.cpu.rename.fp_rename_lookups 40876479 # Number of floating rename lookups 483system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed 484system.cpu.rename.UndoneMaps 350615012 # Number of HB maps that are undone due to squashing 485system.cpu.rename.serializingInsts 7270 # count of serializing insts renamed 486system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed 487system.cpu.rename.skidInsts 108779302 # count of insts added to the skid buffer 488system.cpu.memDep0.insertedLoads 366116842 # Number of loads inserted to the mem dependence unit. 489system.cpu.memDep0.insertedStores 236096763 # Number of stores inserted to the mem dependence unit. 490system.cpu.memDep0.conflictingLoads 1776884 # Number of conflicting loads. 491system.cpu.memDep0.conflictingStores 5334939 # Number of conflicting stores. 492system.cpu.iq.iqInstsAdded 1168558899 # Number of instructions added to the IQ (excludes non-spec) 493system.cpu.iq.iqNonSpecInstsAdded 12359 # Number of non-speculative instructions added to the IQ 494system.cpu.iq.iqInstsIssued 1017090766 # Number of instructions issued 495system.cpu.iq.iqSquashedInstsIssued 18380245 # Number of squashed instructions issued 496system.cpu.iq.iqSquashedInstsExamined 379846300 # Number of squashed instructions iterated over during squash; mainly for profiling 497system.cpu.iq.iqSquashedOperandsExamined 1032153355 # Number of squashed operands that are examined and possibly removed from graph 498system.cpu.iq.iqSquashedNonSpecRemoved 205 # Number of squashed non-spec instructions that were removed 499system.cpu.iq.issued_per_cycle::samples 821526595 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::mean 1.238050 # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::stdev 1.084805 # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::0 263868507 32.12% 32.12% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::1 227113166 27.65% 59.76% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::2 217783209 26.51% 86.27% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::3 96635677 11.76% 98.04% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::4 16126029 1.96% 100.00% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::total 821526595 # Number of insts issued each cycle 516system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 517system.cpu.iq.fu_full::IntAlu 63875827 18.90% 18.90% # attempts to use FU when none available 518system.cpu.iq.fu_full::IntMult 18143 0.01% 18.91% # attempts to use FU when none available 519system.cpu.iq.fu_full::IntDiv 0 0.00% 18.91% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.91% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.91% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.91% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatMult 0 0.00% 18.91% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.91% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.91% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.91% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.91% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.91% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.91% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.91% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.91% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdMult 0 0.00% 18.91% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.91% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdShift 0 0.00% 18.91% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.91% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.91% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.91% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.91% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.91% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.09% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.09% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available 546system.cpu.iq.fu_full::MemRead 157407577 46.57% 65.67% # attempts to use FU when none available 547system.cpu.iq.fu_full::MemWrite 116033793 34.33% 100.00% # attempts to use FU when none available 548system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 549system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 550system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 551system.cpu.iq.FU_type_0::IntAlu 456370958 44.87% 44.87% # Type of FU issued 552system.cpu.iq.FU_type_0::IntMult 5195826 0.51% 45.38% # Type of FU issued 553system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatMisc 11478994 1.13% 47.14% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued 580system.cpu.iq.FU_type_0::MemRead 322082825 31.67% 78.80% # Type of FU issued 581system.cpu.iq.FU_type_0::MemWrite 215586812 21.20% 100.00% # Type of FU issued 582system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 583system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 584system.cpu.iq.FU_type_0::total 1017090766 # Type of FU issued 585system.cpu.iq.rate 1.237557 # Inst issue rate 586system.cpu.iq.fu_busy_cnt 337972229 # FU busy when requested 587system.cpu.iq.fu_busy_rate 0.332293 # FU busy rate (busy events/executed inst) 588system.cpu.iq.int_inst_queue_reads 3150183586 # Number of integer instruction queue reads 589system.cpu.iq.int_inst_queue_writes 1504870139 # Number of integer instruction queue writes 590system.cpu.iq.int_inst_queue_wakeup_accesses 934273978 # Number of integer instruction queue wakeup accesses 591system.cpu.iq.fp_inst_queue_reads 61877015 # Number of floating instruction queue reads 592system.cpu.iq.fp_inst_queue_writes 43565815 # Number of floating instruction queue writes 593system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses 594system.cpu.iq.int_alu_accesses 1321252671 # Number of integer alu accesses 595system.cpu.iq.fp_alu_accesses 33810324 # Number of floating point alu accesses 596system.cpu.iew.lsq.thread0.forwLoads 9960626 # Number of loads that had data forwarded from stores 597system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 598system.cpu.iew.lsq.thread0.squashedLoads 113875904 # Number of loads squashed 599system.cpu.iew.lsq.thread0.ignoredResponses 1099 # Number of memory responses ignored because the instruction is squashed 600system.cpu.iew.lsq.thread0.memOrderViolation 18399 # Number of memory ordering violations 601system.cpu.iew.lsq.thread0.squashedStores 107116267 # Number of stores squashed 602system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 603system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 604system.cpu.iew.lsq.thread0.rescheduledLoads 2065816 # Number of loads that were rescheduled 605system.cpu.iew.lsq.thread0.cacheBlocked 20694 # Number of times an access to memory failed due to the cache being blocked 606system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 607system.cpu.iew.iewSquashCycles 15518009 # Number of cycles IEW is squashing 608system.cpu.iew.iewBlockCycles 35327000 # Number of cycles IEW is blocking 609system.cpu.iew.iewUnblockCycles 41213 # Number of cycles IEW is unblocking 610system.cpu.iew.iewDispatchedInsts 1168576814 # Number of instructions dispatched to IQ 611system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 612system.cpu.iew.iewDispLoadInsts 366116842 # Number of dispatched load instructions 613system.cpu.iew.iewDispStoreInsts 236096763 # Number of dispatched store instructions 614system.cpu.iew.iewDispNonSpecInsts 6619 # Number of dispatched non-speculative instructions 615system.cpu.iew.iewIQFullEvents 114 # Number of times the IQ has become full, causing a stall 616system.cpu.iew.iewLSQFullEvents 44806 # Number of times the LSQ has become full, causing a stall 617system.cpu.iew.memOrderViolationEvents 18399 # Number of memory order violations 618system.cpu.iew.predictedTakenIncorrect 15437241 # Number of branches that were predicted taken incorrectly 619system.cpu.iew.predictedNotTakenIncorrect 3784654 # Number of branches that were predicted not taken incorrectly 620system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute 621system.cpu.iew.iewExecutedInsts 974751722 # Number of executed instructions 622system.cpu.iew.iewExecLoadInsts 303298002 # Number of load instructions executed 623system.cpu.iew.iewExecSquashedInsts 42339044 # Number of squashed instructions skipped in execute 624system.cpu.iew.exec_swp 0 # number of swp insts executed 625system.cpu.iew.exec_nop 5556 # number of nop insts executed 626system.cpu.iew.exec_refs 497764632 # number of memory reference insts executed 627system.cpu.iew.exec_branches 150613642 # Number of branches executed 628system.cpu.iew.exec_stores 194466630 # Number of stores executed 629system.cpu.iew.exec_rate 1.186041 # Inst execution rate 630system.cpu.iew.wb_sent 963724701 # cumulative count of insts sent to commit 631system.cpu.iew.wb_count 960426422 # cumulative count of insts written-back 632system.cpu.iew.wb_producers 536047355 # num instructions producing a value 633system.cpu.iew.wb_consumers 893284415 # num instructions consuming a value 634system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 635system.cpu.iew.wb_rate 1.168610 # insts written-back per cycle 636system.cpu.iew.wb_fanout 0.600086 # average fanout of values written-back 637system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 638system.cpu.commit.commitSquashedInsts 357420349 # The number of squashed insts skipped by commit 639system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards 640system.cpu.commit.branchMispredicts 15500799 # The number of times a branch was mispredicted 641system.cpu.commit.committed_per_cycle::samples 770704967 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::mean 1.023388 # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::stdev 1.776993 # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::0 432077450 56.06% 56.06% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::1 174390434 22.63% 78.69% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::2 72936884 9.46% 88.15% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::3 32898197 4.27% 92.42% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::4 8538905 1.11% 93.53% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::5 14258273 1.85% 95.38% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::6 7269904 0.94% 96.32% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::7 5974492 0.78% 97.10% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::8 22360428 2.90% 100.00% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::total 770704967 # Number of insts commited each cycle 658system.cpu.commit.committedInsts 640654411 # Number of instructions committed 659system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed 660system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 661system.cpu.commit.refs 381221434 # Number of memory references committed 662system.cpu.commit.loads 252240938 # Number of loads committed 663system.cpu.commit.membars 5740 # Number of memory barriers committed 664system.cpu.commit.branches 137364860 # Number of branches committed 665system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. 666system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. 667system.cpu.commit.function_calls 19275340 # Number of function calls committed. 668system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 669system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction 670system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 671system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 677system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 697system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 698system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 699system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction 700system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 701system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 702system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction 703system.cpu.commit.bw_lim_events 22360428 # number cycles where commit BW limit reached 704system.cpu.rob.rob_reads 1894486207 # The number of ROB reads 705system.cpu.rob.rob_writes 2343126387 # The number of ROB writes 706system.cpu.timesIdled 647317 # Number of times that the entire CPU went into an idle state and unscheduled itself 707system.cpu.idleCycles 326926 # Total number of cycles that the CPU has spent unscheduled due to idling 708system.cpu.committedInsts 640649299 # Number of Instructions Simulated 709system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated 710system.cpu.cpi 1.282845 # CPI: Cycles Per Instruction 711system.cpu.cpi_total 1.282845 # CPI: Total CPI of All Threads 712system.cpu.ipc 0.779518 # IPC: Instructions Per Cycle 713system.cpu.ipc_total 0.779518 # IPC: Total IPC of All Threads 714system.cpu.int_regfile_reads 995802121 # number of integer regfile reads 715system.cpu.int_regfile_writes 567908278 # number of integer regfile writes 716system.cpu.fp_regfile_reads 31889840 # number of floating regfile reads 717system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes 718system.cpu.cc_regfile_reads 3794438886 # number of cc regfile reads 719system.cpu.cc_regfile_writes 384898194 # number of cc regfile writes 720system.cpu.misc_regfile_reads 715817246 # number of misc regfile reads 721system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes 722system.cpu.dcache.tags.replacements 2756184 # number of replacements 723system.cpu.dcache.tags.tagsinuse 511.933712 # Cycle average of tags in use 724system.cpu.dcache.tags.total_refs 414215984 # Total number of references to valid blocks. 725system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. 726system.cpu.dcache.tags.avg_refs 150.258129 # Average number of references to valid blocks. 727system.cpu.dcache.tags.warmup_cycle 256316000 # Cycle when the warmup percentage was hit. 728system.cpu.dcache.tags.occ_blocks::cpu.data 511.933712 # Average occupied blocks per requestor 729system.cpu.dcache.tags.occ_percent::cpu.data 0.999871 # Average percentage of cache occupancy 730system.cpu.dcache.tags.occ_percent::total 0.999871 # Average percentage of cache occupancy 731system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 732system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 733system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id 734system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id 735system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id 736system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 737system.cpu.dcache.tags.tag_accesses 839346446 # Number of tag accesses 738system.cpu.dcache.tags.data_accesses 839346446 # Number of data accesses 739system.cpu.dcache.ReadReq_hits::cpu.data 286293586 # number of ReadReq hits 740system.cpu.dcache.ReadReq_hits::total 286293586 # number of ReadReq hits 741system.cpu.dcache.WriteReq_hits::cpu.data 127907704 # number of WriteReq hits 742system.cpu.dcache.WriteReq_hits::total 127907704 # number of WriteReq hits 743system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits 744system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits 745system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits 746system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits 747system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 748system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 749system.cpu.dcache.demand_hits::cpu.data 414201290 # number of demand (read+write) hits 750system.cpu.dcache.demand_hits::total 414201290 # number of demand (read+write) hits 751system.cpu.dcache.overall_hits::cpu.data 414204447 # number of overall hits 752system.cpu.dcache.overall_hits::total 414204447 # number of overall hits 753system.cpu.dcache.ReadReq_misses::cpu.data 3034530 # number of ReadReq misses 754system.cpu.dcache.ReadReq_misses::total 3034530 # number of ReadReq misses 755system.cpu.dcache.WriteReq_misses::cpu.data 1043773 # number of WriteReq misses 756system.cpu.dcache.WriteReq_misses::total 1043773 # number of WriteReq misses 757system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses 758system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses 759system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 760system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 761system.cpu.dcache.demand_misses::cpu.data 4078303 # number of demand (read+write) misses 762system.cpu.dcache.demand_misses::total 4078303 # number of demand (read+write) misses 763system.cpu.dcache.overall_misses::cpu.data 4078949 # number of overall misses 764system.cpu.dcache.overall_misses::total 4078949 # number of overall misses 765system.cpu.dcache.ReadReq_miss_latency::cpu.data 35233063500 # number of ReadReq miss cycles 766system.cpu.dcache.ReadReq_miss_latency::total 35233063500 # number of ReadReq miss cycles 767system.cpu.dcache.WriteReq_miss_latency::cpu.data 9908998850 # number of WriteReq miss cycles 768system.cpu.dcache.WriteReq_miss_latency::total 9908998850 # number of WriteReq miss cycles 769system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles 770system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles 771system.cpu.dcache.demand_miss_latency::cpu.data 45142062350 # number of demand (read+write) miss cycles 772system.cpu.dcache.demand_miss_latency::total 45142062350 # number of demand (read+write) miss cycles 773system.cpu.dcache.overall_miss_latency::cpu.data 45142062350 # number of overall miss cycles 774system.cpu.dcache.overall_miss_latency::total 45142062350 # number of overall miss cycles 775system.cpu.dcache.ReadReq_accesses::cpu.data 289328116 # number of ReadReq accesses(hits+misses) 776system.cpu.dcache.ReadReq_accesses::total 289328116 # number of ReadReq accesses(hits+misses) 777system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 778system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 779system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) 780system.cpu.dcache.SoftPFReq_accesses::total 3803 # number of SoftPFReq accesses(hits+misses) 781system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) 782system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) 783system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 784system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 785system.cpu.dcache.demand_accesses::cpu.data 418279593 # number of demand (read+write) accesses 786system.cpu.dcache.demand_accesses::total 418279593 # number of demand (read+write) accesses 787system.cpu.dcache.overall_accesses::cpu.data 418283396 # number of overall (read+write) accesses 788system.cpu.dcache.overall_accesses::total 418283396 # number of overall (read+write) accesses 789system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010488 # miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_miss_rate::total 0.010488 # miss rate for ReadReq accesses 791system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008094 # miss rate for WriteReq accesses 792system.cpu.dcache.WriteReq_miss_rate::total 0.008094 # miss rate for WriteReq accesses 793system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses 794system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses 795system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses 796system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses 797system.cpu.dcache.demand_miss_rate::cpu.data 0.009750 # miss rate for demand accesses 798system.cpu.dcache.demand_miss_rate::total 0.009750 # miss rate for demand accesses 799system.cpu.dcache.overall_miss_rate::cpu.data 0.009752 # miss rate for overall accesses 800system.cpu.dcache.overall_miss_rate::total 0.009752 # miss rate for overall accesses 801system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11610.715168 # average ReadReq miss latency 802system.cpu.dcache.ReadReq_avg_miss_latency::total 11610.715168 # average ReadReq miss latency 803system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9493.442396 # average WriteReq miss latency 804system.cpu.dcache.WriteReq_avg_miss_latency::total 9493.442396 # average WriteReq miss latency 805system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency 806system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency 807system.cpu.dcache.demand_avg_miss_latency::cpu.data 11068.834844 # average overall miss latency 808system.cpu.dcache.demand_avg_miss_latency::total 11068.834844 # average overall miss latency 809system.cpu.dcache.overall_avg_miss_latency::cpu.data 11067.081827 # average overall miss latency 810system.cpu.dcache.overall_avg_miss_latency::total 11067.081827 # average overall miss latency 811system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 812system.cpu.dcache.blocked_cycles::no_targets 326278 # number of cycles access was blocked 813system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 814system.cpu.dcache.blocked::no_targets 4869 # number of cycles access was blocked 815system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 816system.cpu.dcache.avg_blocked_cycles::no_targets 67.011296 # average number of cycles each access was blocked 817system.cpu.dcache.fast_writes 0 # number of fast writes performed 818system.cpu.dcache.cache_copies 0 # number of cache copies performed 819system.cpu.dcache.writebacks::writebacks 735190 # number of writebacks 820system.cpu.dcache.writebacks::total 735190 # number of writebacks 821system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999322 # number of ReadReq MSHR hits 822system.cpu.dcache.ReadReq_mshr_hits::total 999322 # number of ReadReq MSHR hits 823system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322910 # number of WriteReq MSHR hits 824system.cpu.dcache.WriteReq_mshr_hits::total 322910 # number of WriteReq MSHR hits 825system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 826system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 827system.cpu.dcache.demand_mshr_hits::cpu.data 1322232 # number of demand (read+write) MSHR hits 828system.cpu.dcache.demand_mshr_hits::total 1322232 # number of demand (read+write) MSHR hits 829system.cpu.dcache.overall_mshr_hits::cpu.data 1322232 # number of overall MSHR hits 830system.cpu.dcache.overall_mshr_hits::total 1322232 # number of overall MSHR hits 831system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035208 # number of ReadReq MSHR misses 832system.cpu.dcache.ReadReq_mshr_misses::total 2035208 # number of ReadReq MSHR misses 833system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720863 # number of WriteReq MSHR misses 834system.cpu.dcache.WriteReq_mshr_misses::total 720863 # number of WriteReq MSHR misses 835system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses 836system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses 837system.cpu.dcache.demand_mshr_misses::cpu.data 2756071 # number of demand (read+write) MSHR misses 838system.cpu.dcache.demand_mshr_misses::total 2756071 # number of demand (read+write) MSHR misses 839system.cpu.dcache.overall_mshr_misses::cpu.data 2756712 # number of overall MSHR misses 840system.cpu.dcache.overall_mshr_misses::total 2756712 # number of overall MSHR misses 841system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24098858500 # number of ReadReq MSHR miss cycles 842system.cpu.dcache.ReadReq_mshr_miss_latency::total 24098858500 # number of ReadReq MSHR miss cycles 843system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5945182850 # number of WriteReq MSHR miss cycles 844system.cpu.dcache.WriteReq_mshr_miss_latency::total 5945182850 # number of WriteReq MSHR miss cycles 845system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6199500 # number of SoftPFReq MSHR miss cycles 846system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6199500 # number of SoftPFReq MSHR miss cycles 847system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30044041350 # number of demand (read+write) MSHR miss cycles 848system.cpu.dcache.demand_mshr_miss_latency::total 30044041350 # number of demand (read+write) MSHR miss cycles 849system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30050240850 # number of overall MSHR miss cycles 850system.cpu.dcache.overall_mshr_miss_latency::total 30050240850 # number of overall MSHR miss cycles 851system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses 852system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses 853system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses 854system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses 855system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses 856system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses 857system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses 858system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses 859system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses 860system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses 861system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.980627 # average ReadReq mshr miss latency 862system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.980627 # average ReadReq mshr miss latency 863system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8247.313082 # average WriteReq mshr miss latency 864system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8247.313082 # average WriteReq mshr miss latency 865system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9671.606864 # average SoftPFReq mshr miss latency 866system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9671.606864 # average SoftPFReq mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10901.040412 # average overall mshr miss latency 868system.cpu.dcache.demand_avg_mshr_miss_latency::total 10901.040412 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10900.754540 # average overall mshr miss latency 870system.cpu.dcache.overall_avg_mshr_miss_latency::total 10900.754540 # average overall mshr miss latency 871system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 872system.cpu.icache.tags.replacements 5169094 # number of replacements 873system.cpu.icache.tags.tagsinuse 511.159465 # Cycle average of tags in use 874system.cpu.icache.tags.total_refs 365531814 # Total number of references to valid blocks. 875system.cpu.icache.tags.sampled_refs 5169604 # Sample count of references to valid blocks. 876system.cpu.icache.tags.avg_refs 70.707894 # Average number of references to valid blocks. 877system.cpu.icache.tags.warmup_cycle 246618500 # Cycle when the warmup percentage was hit. 878system.cpu.icache.tags.occ_blocks::cpu.inst 511.159465 # Average occupied blocks per requestor 879system.cpu.icache.tags.occ_percent::cpu.inst 0.998358 # Average percentage of cache occupancy 880system.cpu.icache.tags.occ_percent::total 0.998358 # Average percentage of cache occupancy 881system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 882system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 883system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 884system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 885system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id 886system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 887system.cpu.icache.tags.tag_accesses 746581864 # Number of tag accesses 888system.cpu.icache.tags.data_accesses 746581864 # Number of data accesses 889system.cpu.icache.ReadReq_hits::cpu.inst 365531869 # number of ReadReq hits 890system.cpu.icache.ReadReq_hits::total 365531869 # number of ReadReq hits 891system.cpu.icache.demand_hits::cpu.inst 365531869 # number of demand (read+write) hits 892system.cpu.icache.demand_hits::total 365531869 # number of demand (read+write) hits 893system.cpu.icache.overall_hits::cpu.inst 365531869 # number of overall hits 894system.cpu.icache.overall_hits::total 365531869 # number of overall hits 895system.cpu.icache.ReadReq_misses::cpu.inst 5174253 # number of ReadReq misses 896system.cpu.icache.ReadReq_misses::total 5174253 # number of ReadReq misses 897system.cpu.icache.demand_misses::cpu.inst 5174253 # number of demand (read+write) misses 898system.cpu.icache.demand_misses::total 5174253 # number of demand (read+write) misses 899system.cpu.icache.overall_misses::cpu.inst 5174253 # number of overall misses 900system.cpu.icache.overall_misses::total 5174253 # number of overall misses 901system.cpu.icache.ReadReq_miss_latency::cpu.inst 41642635922 # number of ReadReq miss cycles 902system.cpu.icache.ReadReq_miss_latency::total 41642635922 # number of ReadReq miss cycles 903system.cpu.icache.demand_miss_latency::cpu.inst 41642635922 # number of demand (read+write) miss cycles 904system.cpu.icache.demand_miss_latency::total 41642635922 # number of demand (read+write) miss cycles 905system.cpu.icache.overall_miss_latency::cpu.inst 41642635922 # number of overall miss cycles 906system.cpu.icache.overall_miss_latency::total 41642635922 # number of overall miss cycles 907system.cpu.icache.ReadReq_accesses::cpu.inst 370706122 # number of ReadReq accesses(hits+misses) 908system.cpu.icache.ReadReq_accesses::total 370706122 # number of ReadReq accesses(hits+misses) 909system.cpu.icache.demand_accesses::cpu.inst 370706122 # number of demand (read+write) accesses 910system.cpu.icache.demand_accesses::total 370706122 # number of demand (read+write) accesses 911system.cpu.icache.overall_accesses::cpu.inst 370706122 # number of overall (read+write) accesses 912system.cpu.icache.overall_accesses::total 370706122 # number of overall (read+write) accesses 913system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013958 # miss rate for ReadReq accesses 914system.cpu.icache.ReadReq_miss_rate::total 0.013958 # miss rate for ReadReq accesses 915system.cpu.icache.demand_miss_rate::cpu.inst 0.013958 # miss rate for demand accesses 916system.cpu.icache.demand_miss_rate::total 0.013958 # miss rate for demand accesses 917system.cpu.icache.overall_miss_rate::cpu.inst 0.013958 # miss rate for overall accesses 918system.cpu.icache.overall_miss_rate::total 0.013958 # miss rate for overall accesses 919system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8048.047887 # average ReadReq miss latency 920system.cpu.icache.ReadReq_avg_miss_latency::total 8048.047887 # average ReadReq miss latency 921system.cpu.icache.demand_avg_miss_latency::cpu.inst 8048.047887 # average overall miss latency 922system.cpu.icache.demand_avg_miss_latency::total 8048.047887 # average overall miss latency 923system.cpu.icache.overall_avg_miss_latency::cpu.inst 8048.047887 # average overall miss latency 924system.cpu.icache.overall_avg_miss_latency::total 8048.047887 # average overall miss latency 925system.cpu.icache.blocked_cycles::no_mshrs 80330 # number of cycles access was blocked 926system.cpu.icache.blocked_cycles::no_targets 136 # number of cycles access was blocked 927system.cpu.icache.blocked::no_mshrs 3828 # number of cycles access was blocked 928system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 929system.cpu.icache.avg_blocked_cycles::no_mshrs 20.984848 # average number of cycles each access was blocked 930system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # average number of cycles each access was blocked 931system.cpu.icache.fast_writes 0 # number of fast writes performed 932system.cpu.icache.cache_copies 0 # number of cache copies performed 933system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4632 # number of ReadReq MSHR hits 934system.cpu.icache.ReadReq_mshr_hits::total 4632 # number of ReadReq MSHR hits 935system.cpu.icache.demand_mshr_hits::cpu.inst 4632 # number of demand (read+write) MSHR hits 936system.cpu.icache.demand_mshr_hits::total 4632 # number of demand (read+write) MSHR hits 937system.cpu.icache.overall_mshr_hits::cpu.inst 4632 # number of overall MSHR hits 938system.cpu.icache.overall_mshr_hits::total 4632 # number of overall MSHR hits 939system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169621 # number of ReadReq MSHR misses 940system.cpu.icache.ReadReq_mshr_misses::total 5169621 # number of ReadReq MSHR misses 941system.cpu.icache.demand_mshr_misses::cpu.inst 5169621 # number of demand (read+write) MSHR misses 942system.cpu.icache.demand_mshr_misses::total 5169621 # number of demand (read+write) MSHR misses 943system.cpu.icache.overall_mshr_misses::cpu.inst 5169621 # number of overall MSHR misses 944system.cpu.icache.overall_mshr_misses::total 5169621 # number of overall MSHR misses 945system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39011263436 # number of ReadReq MSHR miss cycles 946system.cpu.icache.ReadReq_mshr_miss_latency::total 39011263436 # number of ReadReq MSHR miss cycles 947system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39011263436 # number of demand (read+write) MSHR miss cycles 948system.cpu.icache.demand_mshr_miss_latency::total 39011263436 # number of demand (read+write) MSHR miss cycles 949system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39011263436 # number of overall MSHR miss cycles 950system.cpu.icache.overall_mshr_miss_latency::total 39011263436 # number of overall MSHR miss cycles 951system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for ReadReq accesses 952system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013945 # mshr miss rate for ReadReq accesses 953system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for demand accesses 954system.cpu.icache.demand_mshr_miss_rate::total 0.013945 # mshr miss rate for demand accesses 955system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for overall accesses 956system.cpu.icache.overall_mshr_miss_rate::total 0.013945 # mshr miss rate for overall accesses 957system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7546.252121 # average ReadReq mshr miss latency 958system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7546.252121 # average ReadReq mshr miss latency 959system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7546.252121 # average overall mshr miss latency 960system.cpu.icache.demand_avg_mshr_miss_latency::total 7546.252121 # average overall mshr miss latency 961system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7546.252121 # average overall mshr miss latency 962system.cpu.icache.overall_avg_mshr_miss_latency::total 7546.252121 # average overall mshr miss latency 963system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 964system.cpu.l2cache.prefetcher.num_hwpf_issued 1349196 # number of hwpf issued 965system.cpu.l2cache.prefetcher.pfIdentified 1355261 # number of prefetch candidates identified 966system.cpu.l2cache.prefetcher.pfBufferHit 5306 # number of redundant prefetches already in prefetch queue 967system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 968system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 969system.cpu.l2cache.prefetcher.pfSpanPage 4789987 # number of prefetches not generated due to page crossing 970system.cpu.l2cache.tags.replacements 299157 # number of replacements 971system.cpu.l2cache.tags.tagsinuse 16361.680261 # Cycle average of tags in use 972system.cpu.l2cache.tags.total_refs 14361629 # Total number of references to valid blocks. 973system.cpu.l2cache.tags.sampled_refs 315521 # Sample count of references to valid blocks. 974system.cpu.l2cache.tags.avg_refs 45.517189 # Average number of references to valid blocks. 975system.cpu.l2cache.tags.warmup_cycle 13425317000 # Cycle when the warmup percentage was hit. 976system.cpu.l2cache.tags.occ_blocks::writebacks 727.702373 # Average occupied blocks per requestor 977system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.736374 # Average occupied blocks per requestor 978system.cpu.l2cache.tags.occ_blocks::cpu.data 8790.707540 # Average occupied blocks per requestor 979system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6712.533973 # Average occupied blocks per requestor 980system.cpu.l2cache.tags.occ_percent::writebacks 0.044415 # Average percentage of cache occupancy 981system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007980 # Average percentage of cache occupancy 982system.cpu.l2cache.tags.occ_percent::cpu.data 0.536542 # Average percentage of cache occupancy 983system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.409701 # Average percentage of cache occupancy 984system.cpu.l2cache.tags.occ_percent::total 0.998638 # Average percentage of cache occupancy 985system.cpu.l2cache.tags.occ_task_id_blocks::1022 6576 # Occupied blocks per task id 986system.cpu.l2cache.tags.occ_task_id_blocks::1024 9788 # Occupied blocks per task id 987system.cpu.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 988system.cpu.l2cache.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1456 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4956 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2112 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7189 # Occupied blocks per task id 996system.cpu.l2cache.tags.occ_task_id_percent::1022 0.401367 # Percentage of cache occupancy per task id 997system.cpu.l2cache.tags.occ_task_id_percent::1024 0.597412 # Percentage of cache occupancy per task id 998system.cpu.l2cache.tags.tag_accesses 244356801 # Number of tag accesses 999system.cpu.l2cache.tags.data_accesses 244356801 # Number of data accesses 1000system.cpu.l2cache.Writeback_hits::writebacks 735190 # number of Writeback hits 1001system.cpu.l2cache.Writeback_hits::total 735190 # number of Writeback hits 1002system.cpu.l2cache.ReadExReq_hits::cpu.data 718237 # number of ReadExReq hits 1003system.cpu.l2cache.ReadExReq_hits::total 718237 # number of ReadExReq hits 1004system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5166046 # number of ReadCleanReq hits 1005system.cpu.l2cache.ReadCleanReq_hits::total 5166046 # number of ReadCleanReq hits 1006system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1926561 # number of ReadSharedReq hits 1007system.cpu.l2cache.ReadSharedReq_hits::total 1926561 # number of ReadSharedReq hits 1008system.cpu.l2cache.demand_hits::cpu.inst 5166046 # number of demand (read+write) hits 1009system.cpu.l2cache.demand_hits::cpu.data 2644798 # number of demand (read+write) hits 1010system.cpu.l2cache.demand_hits::total 7810844 # number of demand (read+write) hits 1011system.cpu.l2cache.overall_hits::cpu.inst 5166046 # number of overall hits 1012system.cpu.l2cache.overall_hits::cpu.data 2644798 # number of overall hits 1013system.cpu.l2cache.overall_hits::total 7810844 # number of overall hits 1014system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses 1015system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses 1016system.cpu.l2cache.ReadExReq_misses::cpu.data 2610 # number of ReadExReq misses 1017system.cpu.l2cache.ReadExReq_misses::total 2610 # number of ReadExReq misses 1018system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3560 # number of ReadCleanReq misses 1019system.cpu.l2cache.ReadCleanReq_misses::total 3560 # number of ReadCleanReq misses 1020system.cpu.l2cache.ReadSharedReq_misses::cpu.data 109288 # number of ReadSharedReq misses 1021system.cpu.l2cache.ReadSharedReq_misses::total 109288 # number of ReadSharedReq misses 1022system.cpu.l2cache.demand_misses::cpu.inst 3560 # number of demand (read+write) misses 1023system.cpu.l2cache.demand_misses::cpu.data 111898 # number of demand (read+write) misses 1024system.cpu.l2cache.demand_misses::total 115458 # number of demand (read+write) misses 1025system.cpu.l2cache.overall_misses::cpu.inst 3560 # number of overall misses 1026system.cpu.l2cache.overall_misses::cpu.data 111898 # number of overall misses 1027system.cpu.l2cache.overall_misses::total 115458 # number of overall misses 1028system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles 1029system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles 1030system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 191923500 # number of ReadExReq miss cycles 1031system.cpu.l2cache.ReadExReq_miss_latency::total 191923500 # number of ReadExReq miss cycles 1032system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262140500 # number of ReadCleanReq miss cycles 1033system.cpu.l2cache.ReadCleanReq_miss_latency::total 262140500 # number of ReadCleanReq miss cycles 1034system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8522681500 # number of ReadSharedReq miss cycles 1035system.cpu.l2cache.ReadSharedReq_miss_latency::total 8522681500 # number of ReadSharedReq miss cycles 1036system.cpu.l2cache.demand_miss_latency::cpu.inst 262140500 # number of demand (read+write) miss cycles 1037system.cpu.l2cache.demand_miss_latency::cpu.data 8714605000 # number of demand (read+write) miss cycles 1038system.cpu.l2cache.demand_miss_latency::total 8976745500 # number of demand (read+write) miss cycles 1039system.cpu.l2cache.overall_miss_latency::cpu.inst 262140500 # number of overall miss cycles 1040system.cpu.l2cache.overall_miss_latency::cpu.data 8714605000 # number of overall miss cycles 1041system.cpu.l2cache.overall_miss_latency::total 8976745500 # number of overall miss cycles 1042system.cpu.l2cache.Writeback_accesses::writebacks 735190 # number of Writeback accesses(hits+misses) 1043system.cpu.l2cache.Writeback_accesses::total 735190 # number of Writeback accesses(hits+misses) 1044system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 1045system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 1046system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) 1047system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) 1048system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5169606 # number of ReadCleanReq accesses(hits+misses) 1049system.cpu.l2cache.ReadCleanReq_accesses::total 5169606 # number of ReadCleanReq accesses(hits+misses) 1050system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2035849 # number of ReadSharedReq accesses(hits+misses) 1051system.cpu.l2cache.ReadSharedReq_accesses::total 2035849 # number of ReadSharedReq accesses(hits+misses) 1052system.cpu.l2cache.demand_accesses::cpu.inst 5169606 # number of demand (read+write) accesses 1053system.cpu.l2cache.demand_accesses::cpu.data 2756696 # number of demand (read+write) accesses 1054system.cpu.l2cache.demand_accesses::total 7926302 # number of demand (read+write) accesses 1055system.cpu.l2cache.overall_accesses::cpu.inst 5169606 # number of overall (read+write) accesses 1056system.cpu.l2cache.overall_accesses::cpu.data 2756696 # number of overall (read+write) accesses 1057system.cpu.l2cache.overall_accesses::total 7926302 # number of overall (read+write) accesses 1058system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1059system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1060system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003621 # miss rate for ReadExReq accesses 1061system.cpu.l2cache.ReadExReq_miss_rate::total 0.003621 # miss rate for ReadExReq accesses 1062system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadCleanReq accesses 1063system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.000689 # miss rate for ReadCleanReq accesses 1064system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.053682 # miss rate for ReadSharedReq accesses 1065system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.053682 # miss rate for ReadSharedReq accesses 1066system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses 1067system.cpu.l2cache.demand_miss_rate::cpu.data 0.040591 # miss rate for demand accesses 1068system.cpu.l2cache.demand_miss_rate::total 0.014566 # miss rate for demand accesses 1069system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses 1070system.cpu.l2cache.overall_miss_rate::cpu.data 0.040591 # miss rate for overall accesses 1071system.cpu.l2cache.overall_miss_rate::total 0.014566 # miss rate for overall accesses 1072system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1437.500000 # average UpgradeReq miss latency 1073system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1437.500000 # average UpgradeReq miss latency 1074system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73533.908046 # average ReadExReq miss latency 1075system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73533.908046 # average ReadExReq miss latency 1076system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73634.971910 # average ReadCleanReq miss latency 1077system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73634.971910 # average ReadCleanReq miss latency 1078system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77983.689884 # average ReadSharedReq miss latency 1079system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77983.689884 # average ReadSharedReq miss latency 1080system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73634.971910 # average overall miss latency 1081system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77879.899551 # average overall miss latency 1082system.cpu.l2cache.demand_avg_miss_latency::total 77749.012628 # average overall miss latency 1083system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73634.971910 # average overall miss latency 1084system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77879.899551 # average overall miss latency 1085system.cpu.l2cache.overall_avg_miss_latency::total 77749.012628 # average overall miss latency 1086system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1087system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1088system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1089system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1090system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1091system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1092system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1093system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1094system.cpu.l2cache.writebacks::writebacks 66338 # number of writebacks 1095system.cpu.l2cache.writebacks::total 66338 # number of writebacks 1096system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1216 # number of ReadExReq MSHR hits 1097system.cpu.l2cache.ReadExReq_mshr_hits::total 1216 # number of ReadExReq MSHR hits 1098system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 1099system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 1100system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 1112 # number of ReadSharedReq MSHR hits 1101system.cpu.l2cache.ReadSharedReq_mshr_hits::total 1112 # number of ReadSharedReq MSHR hits 1102system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits 1103system.cpu.l2cache.demand_mshr_hits::cpu.data 2328 # number of demand (read+write) MSHR hits 1104system.cpu.l2cache.demand_mshr_hits::total 2341 # number of demand (read+write) MSHR hits 1105system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits 1106system.cpu.l2cache.overall_mshr_hits::cpu.data 2328 # number of overall MSHR hits 1107system.cpu.l2cache.overall_mshr_hits::total 2341 # number of overall MSHR hits 1108system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8918 # number of CleanEvict MSHR misses 1109system.cpu.l2cache.CleanEvict_mshr_misses::total 8918 # number of CleanEvict MSHR misses 1110system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202421 # number of HardPFReq MSHR misses 1111system.cpu.l2cache.HardPFReq_mshr_misses::total 202421 # number of HardPFReq MSHR misses 1112system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses 1113system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses 1114system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1394 # number of ReadExReq MSHR misses 1115system.cpu.l2cache.ReadExReq_mshr_misses::total 1394 # number of ReadExReq MSHR misses 1116system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3547 # number of ReadCleanReq MSHR misses 1117system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3547 # number of ReadCleanReq MSHR misses 1118system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 108176 # number of ReadSharedReq MSHR misses 1119system.cpu.l2cache.ReadSharedReq_mshr_misses::total 108176 # number of ReadSharedReq MSHR misses 1120system.cpu.l2cache.demand_mshr_misses::cpu.inst 3547 # number of demand (read+write) MSHR misses 1121system.cpu.l2cache.demand_mshr_misses::cpu.data 109570 # number of demand (read+write) MSHR misses 1122system.cpu.l2cache.demand_mshr_misses::total 113117 # number of demand (read+write) MSHR misses 1123system.cpu.l2cache.overall_mshr_misses::cpu.inst 3547 # number of overall MSHR misses 1124system.cpu.l2cache.overall_mshr_misses::cpu.data 109570 # number of overall MSHR misses 1125system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202421 # number of overall MSHR misses 1126system.cpu.l2cache.overall_mshr_misses::total 315538 # number of overall MSHR misses 1127system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17045778133 # number of HardPFReq MSHR miss cycles 1128system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17045778133 # number of HardPFReq MSHR miss cycles 1129system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 268500 # number of UpgradeReq MSHR miss cycles 1130system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 268500 # number of UpgradeReq MSHR miss cycles 1131system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 123342500 # number of ReadExReq MSHR miss cycles 1132system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 123342500 # number of ReadExReq MSHR miss cycles 1133system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 239801000 # number of ReadCleanReq MSHR miss cycles 1134system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 239801000 # number of ReadCleanReq MSHR miss cycles 1135system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7820358000 # number of ReadSharedReq MSHR miss cycles 1136system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7820358000 # number of ReadSharedReq MSHR miss cycles 1137system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 239801000 # number of demand (read+write) MSHR miss cycles 1138system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7943700500 # number of demand (read+write) MSHR miss cycles 1139system.cpu.l2cache.demand_mshr_miss_latency::total 8183501500 # number of demand (read+write) MSHR miss cycles 1140system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 239801000 # number of overall MSHR miss cycles 1141system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7943700500 # number of overall MSHR miss cycles 1142system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17045778133 # number of overall MSHR miss cycles 1143system.cpu.l2cache.overall_mshr_miss_latency::total 25229279633 # number of overall MSHR miss cycles 1144system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1145system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1146system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1147system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1148system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1149system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1150system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001934 # mshr miss rate for ReadExReq accesses 1151system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001934 # mshr miss rate for ReadExReq accesses 1152system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadCleanReq accesses 1153system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadCleanReq accesses 1154system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053136 # mshr miss rate for ReadSharedReq accesses 1155system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053136 # mshr miss rate for ReadSharedReq accesses 1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039747 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::total 0.014271 # mshr miss rate for demand accesses 1159system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses 1160system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039747 # mshr miss rate for overall accesses 1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1162system.cpu.l2cache.overall_mshr_miss_rate::total 0.039809 # mshr miss rate for overall accesses 1163system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253 # average HardPFReq mshr miss latency 1164system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84209.534253 # average HardPFReq mshr miss latency 1165system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16781.250000 # average UpgradeReq mshr miss latency 1166system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16781.250000 # average UpgradeReq mshr miss latency 1167system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88480.989957 # average ReadExReq mshr miss latency 1168system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88480.989957 # average ReadExReq mshr miss latency 1169system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67606.709896 # average ReadCleanReq mshr miss latency 1170system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67606.709896 # average ReadCleanReq mshr miss latency 1171system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72292.911552 # average ReadSharedReq mshr miss latency 1172system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72292.911552 # average ReadSharedReq mshr miss latency 1173system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67606.709896 # average overall mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72498.863740 # average overall mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72345.460894 # average overall mshr miss latency 1176system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67606.709896 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72498.863740 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79956.390777 # average overall mshr miss latency 1180system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1181system.cpu.toL2Bus.trans_dist::ReadResp 7205469 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::Writeback 801528 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::CleanEvict 6778838 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::HardPFReq 266094 # Transaction distribution 1185system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution 1186system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution 1187system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169621 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035849 # Transaction distribution 1191system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15507443 # Packet count per connected master and slave (bytes) 1192system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626416 # Packet count per connected master and slave (bytes) 1193system.cpu.toL2Bus.pkt_count::total 23133859 # Packet count per connected master and slave (bytes) 1194system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330854720 # Cumulative packet size per connected master and slave (bytes) 1195system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223480704 # Cumulative packet size per connected master and slave (bytes) 1196system.cpu.toL2Bus.pkt_size::total 554335424 # Cumulative packet size per connected master and slave (bytes) 1197system.cpu.toL2Bus.snoops 565266 # Total snoops (count) 1198system.cpu.toL2Bus.snoop_fanout::samples 16416862 # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::mean 1.034431 # Request fanout histogram 1200system.cpu.toL2Bus.snoop_fanout::stdev 0.182334 # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1202system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1203system.cpu.toL2Bus.snoop_fanout::1 15851611 96.56% 96.56% # Request fanout histogram 1204system.cpu.toL2Bus.snoop_fanout::2 565251 3.44% 100.00% # Request fanout histogram 1205system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1206system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1207system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::total 16416862 # Request fanout histogram 1209system.cpu.toL2Bus.reqLayer0.occupancy 8660995500 # Layer occupancy (ticks) 1210system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) 1211system.cpu.toL2Bus.respLayer0.occupancy 7754456946 # Layer occupancy (ticks) 1212system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 1213system.cpu.toL2Bus.respLayer1.occupancy 4135063976 # Layer occupancy (ticks) 1214system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 1215system.membus.trans_dist::ReadResp 314068 # Transaction distribution 1216system.membus.trans_dist::Writeback 66338 # Transaction distribution 1217system.membus.trans_dist::CleanEvict 232219 # Transaction distribution 1218system.membus.trans_dist::UpgradeReq 16 # Transaction distribution 1219system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 1220system.membus.trans_dist::ReadExReq 1394 # Transaction distribution 1221system.membus.trans_dist::ReadExResp 1394 # Transaction distribution 1222system.membus.trans_dist::ReadSharedReq 314068 # Transaction distribution 1223system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 929513 # Packet count per connected master and slave (bytes) 1224system.membus.pkt_count::total 929513 # Packet count per connected master and slave (bytes) 1225system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435200 # Cumulative packet size per connected master and slave (bytes) 1226system.membus.pkt_size::total 24435200 # Cumulative packet size per connected master and slave (bytes) 1227system.membus.snoops 0 # Total snoops (count) 1228system.membus.snoop_fanout::samples 614035 # Request fanout histogram 1229system.membus.snoop_fanout::mean 0 # Request fanout histogram 1230system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1231system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1232system.membus.snoop_fanout::0 614035 100.00% 100.00% # Request fanout histogram 1233system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1234system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1235system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1236system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1237system.membus.snoop_fanout::total 614035 # Request fanout histogram 1238system.membus.reqLayer0.occupancy 967133123 # Layer occupancy (ticks) 1239system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 1240system.membus.respLayer1.occupancy 1648308021 # Layer occupancy (ticks) 1241system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 1242 1243---------- End Simulation Statistics ---------- 1244