config.ini revision 10798:74e3c7359393
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26mmap_using_noreserve=false 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=16 52LSQCheckLoads=true 53LSQDepCheckShift=0 54SQEntries=16 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=2 70decodeWidth=3 71dispatchWidth=6 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dstage2_mmu=system.cpu.dstage2_mmu 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=16 79fetchQueueSize=32 80fetchToDecodeDelay=3 81fetchTrapLatency=1 82fetchWidth=3 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95istage2_mmu=system.cpu.istage2_mmu 96itb=system.cpu.itb 97max_insts_all_threads=0 98max_insts_any_thread=0 99max_loads_all_threads=0 100max_loads_any_thread=0 101needsTSO=false 102numIQEntries=32 103numPhysCCRegs=640 104numPhysFloatRegs=192 105numPhysIntRegs=128 106numROBEntries=40 107numRobs=1 108numThreads=1 109profile=0 110progress_interval=0 111renameToDecodeDelay=1 112renameToFetchDelay=1 113renameToIEWDelay=1 114renameToROBDelay=1 115renameWidth=3 116simpoint_start_insts= 117smtCommitPolicy=RoundRobin 118smtFetchPolicy=SingleThread 119smtIQPolicy=Partitioned 120smtIQThreshold=100 121smtLSQPolicy=Partitioned 122smtLSQThreshold=100 123smtNumFetchingThreads=1 124smtROBPolicy=Partitioned 125smtROBThreshold=100 126socket_id=0 127squashWidth=8 128store_set_clear_period=250000 129switched_out=false 130system=system 131tracer=system.cpu.tracer 132trapLatency=13 133wbWidth=8 134workload=system.cpu.workload 135dcache_port=system.cpu.dcache.cpu_side 136icache_port=system.cpu.icache.cpu_side 137 138[system.cpu.branchPred] 139type=BiModeBP 140BTBEntries=2048 141BTBTagSize=18 142RASSize=16 143choiceCtrBits=2 144choicePredictorSize=8192 145eventq_index=0 146globalCtrBits=2 147globalPredictorSize=8192 148instShiftAmt=2 149numThreads=1 150 151[system.cpu.dcache] 152type=BaseCache 153children=tags 154addr_ranges=0:18446744073709551615 155assoc=2 156clk_domain=system.cpu_clk_domain 157demand_mshr_reserve=1 158eventq_index=0 159forward_snoops=true 160hit_latency=2 161is_top_level=true 162max_miss_count=0 163mshrs=6 164prefetch_on_access=false 165prefetcher=Null 166response_latency=2 167sequential_access=false 168size=32768 169system=system 170tags=system.cpu.dcache.tags 171tgts_per_mshr=8 172two_queue=false 173write_buffers=16 174cpu_side=system.cpu.dcache_port 175mem_side=system.cpu.toL2Bus.slave[1] 176 177[system.cpu.dcache.tags] 178type=LRU 179assoc=2 180block_size=64 181clk_domain=system.cpu_clk_domain 182eventq_index=0 183hit_latency=2 184sequential_access=false 185size=32768 186 187[system.cpu.dstage2_mmu] 188type=ArmStage2MMU 189children=stage2_tlb 190eventq_index=0 191stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 192sys=system 193tlb=system.cpu.dtb 194 195[system.cpu.dstage2_mmu.stage2_tlb] 196type=ArmTLB 197children=walker 198eventq_index=0 199is_stage2=true 200size=32 201walker=system.cpu.dstage2_mmu.stage2_tlb.walker 202 203[system.cpu.dstage2_mmu.stage2_tlb.walker] 204type=ArmTableWalker 205clk_domain=system.cpu_clk_domain 206eventq_index=0 207is_stage2=true 208num_squash_per_cycle=2 209sys=system 210 211[system.cpu.dtb] 212type=ArmTLB 213children=walker 214eventq_index=0 215is_stage2=false 216size=64 217walker=system.cpu.dtb.walker 218 219[system.cpu.dtb.walker] 220type=ArmTableWalker 221clk_domain=system.cpu_clk_domain 222eventq_index=0 223is_stage2=false 224num_squash_per_cycle=2 225sys=system 226port=system.cpu.toL2Bus.slave[3] 227 228[system.cpu.fuPool] 229type=FUPool 230children=FUList0 FUList1 FUList2 FUList3 FUList4 231FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 232eventq_index=0 233 234[system.cpu.fuPool.FUList0] 235type=FUDesc 236children=opList 237count=2 238eventq_index=0 239opList=system.cpu.fuPool.FUList0.opList 240 241[system.cpu.fuPool.FUList0.opList] 242type=OpDesc 243eventq_index=0 244issueLat=1 245opClass=IntAlu 246opLat=1 247 248[system.cpu.fuPool.FUList1] 249type=FUDesc 250children=opList0 opList1 opList2 251count=1 252eventq_index=0 253opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 254 255[system.cpu.fuPool.FUList1.opList0] 256type=OpDesc 257eventq_index=0 258issueLat=1 259opClass=IntMult 260opLat=3 261 262[system.cpu.fuPool.FUList1.opList1] 263type=OpDesc 264eventq_index=0 265issueLat=12 266opClass=IntDiv 267opLat=12 268 269[system.cpu.fuPool.FUList1.opList2] 270type=OpDesc 271eventq_index=0 272issueLat=1 273opClass=IprAccess 274opLat=3 275 276[system.cpu.fuPool.FUList2] 277type=FUDesc 278children=opList 279count=1 280eventq_index=0 281opList=system.cpu.fuPool.FUList2.opList 282 283[system.cpu.fuPool.FUList2.opList] 284type=OpDesc 285eventq_index=0 286issueLat=1 287opClass=MemRead 288opLat=2 289 290[system.cpu.fuPool.FUList3] 291type=FUDesc 292children=opList 293count=1 294eventq_index=0 295opList=system.cpu.fuPool.FUList3.opList 296 297[system.cpu.fuPool.FUList3.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=MemWrite 302opLat=2 303 304[system.cpu.fuPool.FUList4] 305type=FUDesc 306children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 307count=2 308eventq_index=0 309opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 310 311[system.cpu.fuPool.FUList4.opList00] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=SimdAdd 316opLat=4 317 318[system.cpu.fuPool.FUList4.opList01] 319type=OpDesc 320eventq_index=0 321issueLat=1 322opClass=SimdAddAcc 323opLat=4 324 325[system.cpu.fuPool.FUList4.opList02] 326type=OpDesc 327eventq_index=0 328issueLat=1 329opClass=SimdAlu 330opLat=4 331 332[system.cpu.fuPool.FUList4.opList03] 333type=OpDesc 334eventq_index=0 335issueLat=1 336opClass=SimdCmp 337opLat=4 338 339[system.cpu.fuPool.FUList4.opList04] 340type=OpDesc 341eventq_index=0 342issueLat=1 343opClass=SimdCvt 344opLat=3 345 346[system.cpu.fuPool.FUList4.opList05] 347type=OpDesc 348eventq_index=0 349issueLat=1 350opClass=SimdMisc 351opLat=3 352 353[system.cpu.fuPool.FUList4.opList06] 354type=OpDesc 355eventq_index=0 356issueLat=1 357opClass=SimdMult 358opLat=5 359 360[system.cpu.fuPool.FUList4.opList07] 361type=OpDesc 362eventq_index=0 363issueLat=1 364opClass=SimdMultAcc 365opLat=5 366 367[system.cpu.fuPool.FUList4.opList08] 368type=OpDesc 369eventq_index=0 370issueLat=1 371opClass=SimdShift 372opLat=3 373 374[system.cpu.fuPool.FUList4.opList09] 375type=OpDesc 376eventq_index=0 377issueLat=1 378opClass=SimdShiftAcc 379opLat=3 380 381[system.cpu.fuPool.FUList4.opList10] 382type=OpDesc 383eventq_index=0 384issueLat=1 385opClass=SimdSqrt 386opLat=9 387 388[system.cpu.fuPool.FUList4.opList11] 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=SimdFloatAdd 393opLat=5 394 395[system.cpu.fuPool.FUList4.opList12] 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=SimdFloatAlu 400opLat=5 401 402[system.cpu.fuPool.FUList4.opList13] 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=SimdFloatCmp 407opLat=3 408 409[system.cpu.fuPool.FUList4.opList14] 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdFloatCvt 414opLat=3 415 416[system.cpu.fuPool.FUList4.opList15] 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdFloatDiv 421opLat=3 422 423[system.cpu.fuPool.FUList4.opList16] 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdFloatMisc 428opLat=3 429 430[system.cpu.fuPool.FUList4.opList17] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdFloatMult 435opLat=3 436 437[system.cpu.fuPool.FUList4.opList18] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdFloatMultAcc 442opLat=1 443 444[system.cpu.fuPool.FUList4.opList19] 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdFloatSqrt 449opLat=9 450 451[system.cpu.fuPool.FUList4.opList20] 452type=OpDesc 453eventq_index=0 454issueLat=1 455opClass=FloatAdd 456opLat=5 457 458[system.cpu.fuPool.FUList4.opList21] 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=FloatCmp 463opLat=5 464 465[system.cpu.fuPool.FUList4.opList22] 466type=OpDesc 467eventq_index=0 468issueLat=1 469opClass=FloatCvt 470opLat=5 471 472[system.cpu.fuPool.FUList4.opList23] 473type=OpDesc 474eventq_index=0 475issueLat=9 476opClass=FloatDiv 477opLat=9 478 479[system.cpu.fuPool.FUList4.opList24] 480type=OpDesc 481eventq_index=0 482issueLat=33 483opClass=FloatSqrt 484opLat=33 485 486[system.cpu.fuPool.FUList4.opList25] 487type=OpDesc 488eventq_index=0 489issueLat=1 490opClass=FloatMult 491opLat=4 492 493[system.cpu.icache] 494type=BaseCache 495children=tags 496addr_ranges=0:18446744073709551615 497assoc=2 498clk_domain=system.cpu_clk_domain 499demand_mshr_reserve=1 500eventq_index=0 501forward_snoops=false 502hit_latency=1 503is_top_level=true 504max_miss_count=0 505mshrs=2 506prefetch_on_access=false 507prefetcher=Null 508response_latency=1 509sequential_access=false 510size=32768 511system=system 512tags=system.cpu.icache.tags 513tgts_per_mshr=8 514two_queue=false 515write_buffers=8 516cpu_side=system.cpu.icache_port 517mem_side=system.cpu.toL2Bus.slave[0] 518 519[system.cpu.icache.tags] 520type=LRU 521assoc=2 522block_size=64 523clk_domain=system.cpu_clk_domain 524eventq_index=0 525hit_latency=1 526sequential_access=false 527size=32768 528 529[system.cpu.interrupts] 530type=ArmInterrupts 531eventq_index=0 532 533[system.cpu.isa] 534type=ArmISA 535eventq_index=0 536fpsid=1090793632 537id_aa64afr0_el1=0 538id_aa64afr1_el1=0 539id_aa64dfr0_el1=1052678 540id_aa64dfr1_el1=0 541id_aa64isar0_el1=0 542id_aa64isar1_el1=0 543id_aa64mmfr0_el1=15728642 544id_aa64mmfr1_el1=0 545id_aa64pfr0_el1=17 546id_aa64pfr1_el1=0 547id_isar0=34607377 548id_isar1=34677009 549id_isar2=555950401 550id_isar3=17899825 551id_isar4=268501314 552id_isar5=0 553id_mmfr0=270536963 554id_mmfr1=0 555id_mmfr2=19070976 556id_mmfr3=34611729 557id_pfr0=49 558id_pfr1=4113 559midr=1091551472 560pmu=Null 561system=system 562 563[system.cpu.istage2_mmu] 564type=ArmStage2MMU 565children=stage2_tlb 566eventq_index=0 567stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 568sys=system 569tlb=system.cpu.itb 570 571[system.cpu.istage2_mmu.stage2_tlb] 572type=ArmTLB 573children=walker 574eventq_index=0 575is_stage2=true 576size=32 577walker=system.cpu.istage2_mmu.stage2_tlb.walker 578 579[system.cpu.istage2_mmu.stage2_tlb.walker] 580type=ArmTableWalker 581clk_domain=system.cpu_clk_domain 582eventq_index=0 583is_stage2=true 584num_squash_per_cycle=2 585sys=system 586 587[system.cpu.itb] 588type=ArmTLB 589children=walker 590eventq_index=0 591is_stage2=false 592size=64 593walker=system.cpu.itb.walker 594 595[system.cpu.itb.walker] 596type=ArmTableWalker 597clk_domain=system.cpu_clk_domain 598eventq_index=0 599is_stage2=false 600num_squash_per_cycle=2 601sys=system 602port=system.cpu.toL2Bus.slave[2] 603 604[system.cpu.l2cache] 605type=BaseCache 606children=prefetcher tags 607addr_ranges=0:18446744073709551615 608assoc=16 609clk_domain=system.cpu_clk_domain 610demand_mshr_reserve=1 611eventq_index=0 612forward_snoops=true 613hit_latency=12 614is_top_level=false 615max_miss_count=0 616mshrs=16 617prefetch_on_access=true 618prefetcher=system.cpu.l2cache.prefetcher 619response_latency=12 620sequential_access=false 621size=1048576 622system=system 623tags=system.cpu.l2cache.tags 624tgts_per_mshr=8 625two_queue=false 626write_buffers=8 627cpu_side=system.cpu.toL2Bus.master[0] 628mem_side=system.membus.slave[1] 629 630[system.cpu.l2cache.prefetcher] 631type=StridePrefetcher 632cache_snoop=false 633clk_domain=system.cpu_clk_domain 634degree=8 635eventq_index=0 636latency=1 637max_conf=7 638min_conf=0 639on_data=true 640on_inst=true 641on_miss=false 642on_read=true 643on_write=true 644queue_filter=true 645queue_size=32 646queue_squash=true 647start_conf=4 648sys=system 649table_assoc=4 650table_sets=16 651tag_prefetch=true 652thresh_conf=4 653use_master_id=true 654 655[system.cpu.l2cache.tags] 656type=RandomRepl 657assoc=16 658block_size=64 659clk_domain=system.cpu_clk_domain 660eventq_index=0 661hit_latency=12 662sequential_access=false 663size=1048576 664 665[system.cpu.toL2Bus] 666type=CoherentXBar 667clk_domain=system.cpu_clk_domain 668eventq_index=0 669forward_latency=0 670frontend_latency=1 671response_latency=1 672snoop_filter=Null 673snoop_response_latency=1 674system=system 675use_default_range=false 676width=32 677master=system.cpu.l2cache.cpu_side 678slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 679 680[system.cpu.tracer] 681type=ExeTracer 682eventq_index=0 683 684[system.cpu.workload] 685type=LiveProcess 686cmd=perlbmk -I. -I lib mdred.makerand.pl 687cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing 688drivers= 689egid=100 690env= 691errout=cerr 692euid=100 693eventq_index=0 694executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk 695gid=100 696input=cin 697kvmInSE=false 698max_stack_size=67108864 699output=cout 700pid=100 701ppid=99 702simpoint=0 703system=system 704uid=100 705useArchPT=false 706 707[system.cpu_clk_domain] 708type=SrcClockDomain 709clock=500 710domain_id=-1 711eventq_index=0 712init_perf_level=0 713voltage_domain=system.voltage_domain 714 715[system.dvfs_handler] 716type=DVFSHandler 717domains= 718enable=false 719eventq_index=0 720sys_clk_domain=system.clk_domain 721transition_latency=100000000 722 723[system.membus] 724type=CoherentXBar 725clk_domain=system.clk_domain 726eventq_index=0 727forward_latency=4 728frontend_latency=3 729response_latency=2 730snoop_filter=Null 731snoop_response_latency=4 732system=system 733use_default_range=false 734width=16 735master=system.physmem.port 736slave=system.system_port system.cpu.l2cache.mem_side 737 738[system.physmem] 739type=DRAMCtrl 740IDD0=0.075000 741IDD02=0.000000 742IDD2N=0.050000 743IDD2N2=0.000000 744IDD2P0=0.000000 745IDD2P02=0.000000 746IDD2P1=0.000000 747IDD2P12=0.000000 748IDD3N=0.057000 749IDD3N2=0.000000 750IDD3P0=0.000000 751IDD3P02=0.000000 752IDD3P1=0.000000 753IDD3P12=0.000000 754IDD4R=0.187000 755IDD4R2=0.000000 756IDD4W=0.165000 757IDD4W2=0.000000 758IDD5=0.220000 759IDD52=0.000000 760IDD6=0.000000 761IDD62=0.000000 762VDD=1.500000 763VDD2=0.000000 764activation_limit=4 765addr_mapping=RoRaBaCoCh 766bank_groups_per_rank=0 767banks_per_rank=8 768burst_length=8 769channels=1 770clk_domain=system.clk_domain 771conf_table_reported=true 772device_bus_width=8 773device_rowbuffer_size=1024 774device_size=536870912 775devices_per_rank=8 776dll=true 777eventq_index=0 778in_addr_map=true 779max_accesses_per_row=16 780mem_sched_policy=frfcfs 781min_writes_per_switch=16 782null=false 783page_policy=open_adaptive 784range=0:134217727 785ranks_per_channel=2 786read_buffer_size=32 787static_backend_latency=10000 788static_frontend_latency=10000 789tBURST=5000 790tCCD_L=0 791tCK=1250 792tCL=13750 793tCS=2500 794tRAS=35000 795tRCD=13750 796tREFI=7800000 797tRFC=260000 798tRP=13750 799tRRD=6000 800tRRD_L=0 801tRTP=7500 802tRTW=2500 803tWR=15000 804tWTR=7500 805tXAW=30000 806tXP=0 807tXPDLL=0 808tXS=0 809tXSDLL=0 810write_buffer_size=64 811write_high_thresh_perc=85 812write_low_thresh_perc=50 813port=system.membus.master[0] 814 815[system.voltage_domain] 816type=VoltageDomain 817eventq_index=0 818voltage=1.000000 819 820