stats.txt revision 11441:0edcf757b6a2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.489946 # Number of seconds simulated 4sim_ticks 489945697500 # Number of ticks simulated 5final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 199747 # Simulator instruction rate (inst/s) 8host_op_rate 245915 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 152758149 # Simulator tick rate (ticks/s) 10host_mem_usage 280032 # Number of bytes of host memory used 11host_seconds 3207.33 # Real time elapsed on the host 12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory 18system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 22system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 288654 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 291212 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 334143 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 37705926 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 38040069 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 334143 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 334143 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 8634165 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 8634165 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 8634165 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 334143 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 37705926 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 46674234 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 291212 # Number of read requests accepted 40system.physmem.writeReqs 66098 # Number of write requests accepted 41system.physmem.readBursts 291212 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue 45system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 18637568 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 18282 # Per bank write bursts 52system.physmem.perBankRdBursts::1 18130 # Per bank write bursts 53system.physmem.perBankRdBursts::2 18217 # Per bank write bursts 54system.physmem.perBankRdBursts::3 18178 # Per bank write bursts 55system.physmem.perBankRdBursts::4 18288 # Per bank write bursts 56system.physmem.perBankRdBursts::5 18411 # Per bank write bursts 57system.physmem.perBankRdBursts::6 18177 # Per bank write bursts 58system.physmem.perBankRdBursts::7 17990 # Per bank write bursts 59system.physmem.perBankRdBursts::8 18028 # Per bank write bursts 60system.physmem.perBankRdBursts::9 18056 # Per bank write bursts 61system.physmem.perBankRdBursts::10 18107 # Per bank write bursts 62system.physmem.perBankRdBursts::11 18202 # Per bank write bursts 63system.physmem.perBankRdBursts::12 18216 # Per bank write bursts 64system.physmem.perBankRdBursts::13 18274 # Per bank write bursts 65system.physmem.perBankRdBursts::14 18077 # Per bank write bursts 66system.physmem.perBankRdBursts::15 18258 # Per bank write bursts 67system.physmem.perBankWrBursts::0 4171 # Per bank write bursts 68system.physmem.perBankWrBursts::1 4099 # Per bank write bursts 69system.physmem.perBankWrBursts::2 4134 # Per bank write bursts 70system.physmem.perBankWrBursts::3 4146 # Per bank write bursts 71system.physmem.perBankWrBursts::4 4225 # Per bank write bursts 72system.physmem.perBankWrBursts::5 4224 # Per bank write bursts 73system.physmem.perBankWrBursts::6 4173 # Per bank write bursts 74system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 75system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 76system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 77system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 78system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 79system.physmem.perBankWrBursts::12 4095 # Per bank write bursts 80system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 81system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::15 4138 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 489945603000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 291212 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 66098 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 290509 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 903 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 903 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 4017 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 4017 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 4017 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 4019 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 4017 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 110179 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 207.337369 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 135.107709 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 257.005441 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 44928 40.78% 40.78% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 43473 39.46% 80.23% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 9308 8.45% 88.68% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 1919 1.74% 90.42% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 694 0.63% 91.05% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 753 0.68% 91.74% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 467 0.42% 92.16% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 575 0.52% 92.68% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 8062 7.32% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 110179 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 48.520538 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::gmean 34.272045 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 506.481387 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::mean 16.449091 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 16.428808 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 0.834669 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::16 3115 77.55% 77.55% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18 902 22.45% 100.00% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads 225system.physmem.totQLat 3297540750 # Total ticks spent queuing 226system.physmem.totMemAccLat 8751747000 # Total ticks spent from burst creation until serviced by the DRAM 227system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers 228system.physmem.avgQLat 11336.00 # Average queueing delay per DRAM burst 229system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 230system.physmem.avgMemAccLat 30086.00 # Average memory access latency per DRAM burst 231system.physmem.avgRdBW 38.00 # Average DRAM read bandwidth in MiByte/s 232system.physmem.avgWrBW 8.63 # Average achieved write bandwidth in MiByte/s 233system.physmem.avgRdBWSys 38.04 # Average system read bandwidth in MiByte/s 234system.physmem.avgWrBWSys 8.63 # Average system write bandwidth in MiByte/s 235system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 236system.physmem.busUtil 0.36 # Data bus utilization in percentage 237system.physmem.busUtilRead 0.30 # Data bus utilization in percentage for reads 238system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes 239system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 240system.physmem.avgWrQLen 22.85 # Average write queue length when enqueuing 241system.physmem.readRowHits 195161 # Number of row buffer hits during reads 242system.physmem.writeRowHits 51618 # Number of row buffer hits during writes 243system.physmem.readRowHitRate 67.09 # Row buffer hit rate for reads 244system.physmem.writeRowHitRate 78.09 # Row buffer hit rate for writes 245system.physmem.avgGap 1371205.96 # Average gap between requests 246system.physmem.pageHitRate 69.13 # Row buffer hit rate, read and write combined 247system.physmem_0.actEnergy 417417840 # Energy for activate commands per rank (pJ) 248system.physmem_0.preEnergy 227757750 # Energy for precharge commands per rank (pJ) 249system.physmem_0.readEnergy 1136210400 # Energy for read commands per rank (pJ) 250system.physmem_0.writeEnergy 215563680 # Energy for write commands per rank (pJ) 251system.physmem_0.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ) 252system.physmem_0.actBackEnergy 104435392590 # Energy for active background per rank (pJ) 253system.physmem_0.preBackEnergy 202355359500 # Energy for precharge background per rank (pJ) 254system.physmem_0.totalEnergy 340788331200 # Total energy per rank (pJ) 255system.physmem_0.averagePower 695.568361 # Core power per rank (mW) 256system.physmem_0.memoryStateTime::IDLE 335944764000 # Time in different power states 257system.physmem_0.memoryStateTime::REF 16360240000 # Time in different power states 258system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 259system.physmem_0.memoryStateTime::ACT 137638069000 # Time in different power states 260system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 261system.physmem_1.actEnergy 415474920 # Energy for activate commands per rank (pJ) 262system.physmem_1.preEnergy 226697625 # Energy for precharge commands per rank (pJ) 263system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) 264system.physmem_1.writeEnergy 212608800 # Energy for write commands per rank (pJ) 265system.physmem_1.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ) 266system.physmem_1.actBackEnergy 104010891930 # Energy for active background per rank (pJ) 267system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ) 268system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ) 269system.physmem_1.averagePower 695.442012 # Core power per rank (mW) 270system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states 271system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states 272system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 273system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states 274system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 275system.cpu.branchPred.lookups 144591747 # Number of BP lookups 276system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted 277system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect 278system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups 279system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits 280system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 281system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage 282system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target. 283system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions. 284system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups. 285system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits. 286system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses. 287system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches. 288system.cpu_clk_domain.clock 500 # Clock period in ticks 289system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 298system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 299system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 300system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 301system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 302system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 303system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 304system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 305system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 306system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 307system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 308system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 309system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 310system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 311system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 312system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 313system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 314system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 315system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 316system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 317system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 318system.cpu.dtb.walker.walks 0 # Table walker walks requested 319system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.inst_hits 0 # ITB inst hits 327system.cpu.dtb.inst_misses 0 # ITB inst misses 328system.cpu.dtb.read_hits 0 # DTB read hits 329system.cpu.dtb.read_misses 0 # DTB read misses 330system.cpu.dtb.write_hits 0 # DTB write hits 331system.cpu.dtb.write_misses 0 # DTB write misses 332system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 333system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 334system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 335system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 336system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 337system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 338system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 339system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 340system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 341system.cpu.dtb.read_accesses 0 # DTB read accesses 342system.cpu.dtb.write_accesses 0 # DTB write accesses 343system.cpu.dtb.inst_accesses 0 # ITB inst accesses 344system.cpu.dtb.hits 0 # DTB hits 345system.cpu.dtb.misses 0 # DTB misses 346system.cpu.dtb.accesses 0 # DTB accesses 347system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 356system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 357system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 358system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 359system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 360system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 361system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 362system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 363system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 364system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 365system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 366system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 367system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 368system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 369system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 370system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 371system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 372system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 373system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 374system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 375system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 376system.cpu.itb.walker.walks 0 # Table walker walks requested 377system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.inst_hits 0 # ITB inst hits 385system.cpu.itb.inst_misses 0 # ITB inst misses 386system.cpu.itb.read_hits 0 # DTB read hits 387system.cpu.itb.read_misses 0 # DTB read misses 388system.cpu.itb.write_hits 0 # DTB write hits 389system.cpu.itb.write_misses 0 # DTB write misses 390system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 391system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 392system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 393system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 394system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 395system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 396system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 397system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 398system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 399system.cpu.itb.read_accesses 0 # DTB read accesses 400system.cpu.itb.write_accesses 0 # DTB write accesses 401system.cpu.itb.inst_accesses 0 # ITB inst accesses 402system.cpu.itb.hits 0 # DTB hits 403system.cpu.itb.misses 0 # DTB misses 404system.cpu.itb.accesses 0 # DTB accesses 405system.cpu.workload.num_syscalls 673 # Number of system calls 406system.cpu.numCycles 979891395 # number of cpu cycles simulated 407system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 408system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 409system.cpu.committedInsts 640655085 # Number of instructions committed 410system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed 411system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit 412system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 413system.cpu.cpi 1.529515 # CPI: cycles per instruction 414system.cpu.ipc 0.653802 # IPC: instructions per cycle 415system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 416system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction 417system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 418system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 419system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 420system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 421system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 422system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 423system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 424system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 425system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 426system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 427system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 428system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 429system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 430system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 431system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 432system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 433system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 434system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 435system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 436system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 437system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 438system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 439system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 440system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 441system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 442system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 443system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 444system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 445system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 446system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction 447system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 448system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 449system.cpu.op_class_0::total 788730744 # Class of committed instruction 450system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked 451system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped 452system.cpu.dcache.tags.replacements 778302 # number of replacements 453system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use 454system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks. 455system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks. 456system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks. 457system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit. 458system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor 459system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy 460system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy 461system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 462system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 463system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 464system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id 465system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id 466system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id 467system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 468system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses 469system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses 470system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits 471system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits 472system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits 473system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits 474system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits 475system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits 476system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 477system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 478system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 479system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 480system.cpu.dcache.demand_hits::cpu.data 378433272 # number of demand (read+write) hits 481system.cpu.dcache.demand_hits::total 378433272 # number of demand (read+write) hits 482system.cpu.dcache.overall_hits::cpu.data 378436756 # number of overall hits 483system.cpu.dcache.overall_hits::total 378436756 # number of overall hits 484system.cpu.dcache.ReadReq_misses::cpu.data 713841 # number of ReadReq misses 485system.cpu.dcache.ReadReq_misses::total 713841 # number of ReadReq misses 486system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses 487system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses 488system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses 489system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses 490system.cpu.dcache.demand_misses::cpu.data 851552 # number of demand (read+write) misses 491system.cpu.dcache.demand_misses::total 851552 # number of demand (read+write) misses 492system.cpu.dcache.overall_misses::cpu.data 851693 # number of overall misses 493system.cpu.dcache.overall_misses::total 851693 # number of overall misses 494system.cpu.dcache.ReadReq_miss_latency::cpu.data 25188260500 # number of ReadReq miss cycles 495system.cpu.dcache.ReadReq_miss_latency::total 25188260500 # number of ReadReq miss cycles 496system.cpu.dcache.WriteReq_miss_latency::cpu.data 10109820000 # number of WriteReq miss cycles 497system.cpu.dcache.WriteReq_miss_latency::total 10109820000 # number of WriteReq miss cycles 498system.cpu.dcache.demand_miss_latency::cpu.data 35298080500 # number of demand (read+write) miss cycles 499system.cpu.dcache.demand_miss_latency::total 35298080500 # number of demand (read+write) miss cycles 500system.cpu.dcache.overall_miss_latency::cpu.data 35298080500 # number of overall miss cycles 501system.cpu.dcache.overall_miss_latency::total 35298080500 # number of overall miss cycles 502system.cpu.dcache.ReadReq_accesses::cpu.data 250333347 # number of ReadReq accesses(hits+misses) 503system.cpu.dcache.ReadReq_accesses::total 250333347 # number of ReadReq accesses(hits+misses) 504system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 505system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 506system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) 507system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) 508system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 509system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 510system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 511system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 512system.cpu.dcache.demand_accesses::cpu.data 379284824 # number of demand (read+write) accesses 513system.cpu.dcache.demand_accesses::total 379284824 # number of demand (read+write) accesses 514system.cpu.dcache.overall_accesses::cpu.data 379288449 # number of overall (read+write) accesses 515system.cpu.dcache.overall_accesses::total 379288449 # number of overall (read+write) accesses 516system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses 517system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses 518system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 519system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 520system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses 521system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses 522system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses 523system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses 524system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses 525system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses 526system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35285.533473 # average ReadReq miss latency 527system.cpu.dcache.ReadReq_avg_miss_latency::total 35285.533473 # average ReadReq miss latency 528system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73413.307579 # average WriteReq miss latency 529system.cpu.dcache.WriteReq_avg_miss_latency::total 73413.307579 # average WriteReq miss latency 530system.cpu.dcache.demand_avg_miss_latency::cpu.data 41451.468025 # average overall miss latency 531system.cpu.dcache.demand_avg_miss_latency::total 41451.468025 # average overall miss latency 532system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627 # average overall miss latency 533system.cpu.dcache.overall_avg_miss_latency::total 41444.605627 # average overall miss latency 534system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 540system.cpu.dcache.fast_writes 0 # number of fast writes performed 541system.cpu.dcache.cache_copies 0 # number of cache copies performed 542system.cpu.dcache.writebacks::writebacks 88712 # number of writebacks 543system.cpu.dcache.writebacks::total 88712 # number of writebacks 544system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904 # number of ReadReq MSHR hits 545system.cpu.dcache.ReadReq_mshr_hits::total 904 # number of ReadReq MSHR hits 546system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits 547system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits 548system.cpu.dcache.demand_mshr_hits::cpu.data 69293 # number of demand (read+write) MSHR hits 549system.cpu.dcache.demand_mshr_hits::total 69293 # number of demand (read+write) MSHR hits 550system.cpu.dcache.overall_mshr_hits::cpu.data 69293 # number of overall MSHR hits 551system.cpu.dcache.overall_mshr_hits::total 69293 # number of overall MSHR hits 552system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712937 # number of ReadReq MSHR misses 553system.cpu.dcache.ReadReq_mshr_misses::total 712937 # number of ReadReq MSHR misses 554system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 555system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 556system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 557system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 558system.cpu.dcache.demand_mshr_misses::cpu.data 782259 # number of demand (read+write) MSHR misses 559system.cpu.dcache.demand_mshr_misses::total 782259 # number of demand (read+write) MSHR misses 560system.cpu.dcache.overall_mshr_misses::cpu.data 782398 # number of overall MSHR misses 561system.cpu.dcache.overall_mshr_misses::total 782398 # number of overall MSHR misses 562system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24459771500 # number of ReadReq MSHR miss cycles 563system.cpu.dcache.ReadReq_mshr_miss_latency::total 24459771500 # number of ReadReq MSHR miss cycles 564system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5070040000 # number of WriteReq MSHR miss cycles 565system.cpu.dcache.WriteReq_mshr_miss_latency::total 5070040000 # number of WriteReq MSHR miss cycles 566system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles 567system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles 568system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29529811500 # number of demand (read+write) MSHR miss cycles 569system.cpu.dcache.demand_mshr_miss_latency::total 29529811500 # number of demand (read+write) MSHR miss cycles 570system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29531599500 # number of overall MSHR miss cycles 571system.cpu.dcache.overall_mshr_miss_latency::total 29531599500 # number of overall MSHR miss cycles 572system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses 573system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses 574system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 575system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 576system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses 577system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses 578system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 579system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 580system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses 581system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses 582system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34308.461337 # average ReadReq mshr miss latency 583system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34308.461337 # average ReadReq mshr miss latency 584system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency 585system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency 586system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency 587system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency 588system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency 589system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency 590system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency 591system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency 592system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 593system.cpu.icache.tags.replacements 24859 # number of replacements 594system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use 595system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. 596system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks. 597system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks. 598system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 599system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor 600system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy 601system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy 602system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id 603system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 604system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 605system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 # Occupied blocks per task id 606system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id 607system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses 608system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses 609system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits 610system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits 611system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits 612system.cpu.icache.demand_hits::total 252585994 # number of demand (read+write) hits 613system.cpu.icache.overall_hits::cpu.inst 252585994 # number of overall hits 614system.cpu.icache.overall_hits::total 252585994 # number of overall hits 615system.cpu.icache.ReadReq_misses::cpu.inst 26613 # number of ReadReq misses 616system.cpu.icache.ReadReq_misses::total 26613 # number of ReadReq misses 617system.cpu.icache.demand_misses::cpu.inst 26613 # number of demand (read+write) misses 618system.cpu.icache.demand_misses::total 26613 # number of demand (read+write) misses 619system.cpu.icache.overall_misses::cpu.inst 26613 # number of overall misses 620system.cpu.icache.overall_misses::total 26613 # number of overall misses 621system.cpu.icache.ReadReq_miss_latency::cpu.inst 516729500 # number of ReadReq miss cycles 622system.cpu.icache.ReadReq_miss_latency::total 516729500 # number of ReadReq miss cycles 623system.cpu.icache.demand_miss_latency::cpu.inst 516729500 # number of demand (read+write) miss cycles 624system.cpu.icache.demand_miss_latency::total 516729500 # number of demand (read+write) miss cycles 625system.cpu.icache.overall_miss_latency::cpu.inst 516729500 # number of overall miss cycles 626system.cpu.icache.overall_miss_latency::total 516729500 # number of overall miss cycles 627system.cpu.icache.ReadReq_accesses::cpu.inst 252612607 # number of ReadReq accesses(hits+misses) 628system.cpu.icache.ReadReq_accesses::total 252612607 # number of ReadReq accesses(hits+misses) 629system.cpu.icache.demand_accesses::cpu.inst 252612607 # number of demand (read+write) accesses 630system.cpu.icache.demand_accesses::total 252612607 # number of demand (read+write) accesses 631system.cpu.icache.overall_accesses::cpu.inst 252612607 # number of overall (read+write) accesses 632system.cpu.icache.overall_accesses::total 252612607 # number of overall (read+write) accesses 633system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000105 # miss rate for ReadReq accesses 634system.cpu.icache.ReadReq_miss_rate::total 0.000105 # miss rate for ReadReq accesses 635system.cpu.icache.demand_miss_rate::cpu.inst 0.000105 # miss rate for demand accesses 636system.cpu.icache.demand_miss_rate::total 0.000105 # miss rate for demand accesses 637system.cpu.icache.overall_miss_rate::cpu.inst 0.000105 # miss rate for overall accesses 638system.cpu.icache.overall_miss_rate::total 0.000105 # miss rate for overall accesses 639system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19416.431819 # average ReadReq miss latency 640system.cpu.icache.ReadReq_avg_miss_latency::total 19416.431819 # average ReadReq miss latency 641system.cpu.icache.demand_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency 642system.cpu.icache.demand_avg_miss_latency::total 19416.431819 # average overall miss latency 643system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency 644system.cpu.icache.overall_avg_miss_latency::total 19416.431819 # average overall miss latency 645system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 646system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 647system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 648system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 649system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 650system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 651system.cpu.icache.fast_writes 0 # number of fast writes performed 652system.cpu.icache.cache_copies 0 # number of cache copies performed 653system.cpu.icache.writebacks::writebacks 24859 # number of writebacks 654system.cpu.icache.writebacks::total 24859 # number of writebacks 655system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26613 # number of ReadReq MSHR misses 656system.cpu.icache.ReadReq_mshr_misses::total 26613 # number of ReadReq MSHR misses 657system.cpu.icache.demand_mshr_misses::cpu.inst 26613 # number of demand (read+write) MSHR misses 658system.cpu.icache.demand_mshr_misses::total 26613 # number of demand (read+write) MSHR misses 659system.cpu.icache.overall_mshr_misses::cpu.inst 26613 # number of overall MSHR misses 660system.cpu.icache.overall_mshr_misses::total 26613 # number of overall MSHR misses 661system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 490117500 # number of ReadReq MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_miss_latency::total 490117500 # number of ReadReq MSHR miss cycles 663system.cpu.icache.demand_mshr_miss_latency::cpu.inst 490117500 # number of demand (read+write) MSHR miss cycles 664system.cpu.icache.demand_mshr_miss_latency::total 490117500 # number of demand (read+write) MSHR miss cycles 665system.cpu.icache.overall_mshr_miss_latency::cpu.inst 490117500 # number of overall MSHR miss cycles 666system.cpu.icache.overall_mshr_miss_latency::total 490117500 # number of overall MSHR miss cycles 667system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses 668system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000105 # mshr miss rate for ReadReq accesses 669system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses 670system.cpu.icache.demand_mshr_miss_rate::total 0.000105 # mshr miss rate for demand accesses 671system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses 672system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses 673system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency 677system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency 679system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 680system.cpu.l2cache.tags.replacements 258808 # number of replacements 681system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use 682system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks. 683system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks. 684system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks. 685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 686system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor 688system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.783132 # Average occupied blocks per requestor 689system.cpu.l2cache.tags.occ_percent::writebacks 0.080339 # Average percentage of cache occupancy 690system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002698 # Average percentage of cache occupancy 691system.cpu.l2cache.tags.occ_percent::cpu.data 0.910638 # Average percentage of cache occupancy 692system.cpu.l2cache.tags.occ_percent::total 0.993675 # Average percentage of cache occupancy 693system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 695system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id 696system.cpu.l2cache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id 697system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3136 # Occupied blocks per task id 698system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 # Occupied blocks per task id 699system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id 700system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses 701system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses 702system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits 703system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits 704system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits 705system.cpu.l2cache.WritebackClean_hits::total 23528 # number of WritebackClean hits 706system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 707system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 708system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24049 # number of ReadCleanReq hits 709system.cpu.l2cache.ReadCleanReq_hits::total 24049 # number of ReadCleanReq hits 710system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490486 # number of ReadSharedReq hits 711system.cpu.l2cache.ReadSharedReq_hits::total 490486 # number of ReadSharedReq hits 712system.cpu.l2cache.demand_hits::cpu.inst 24049 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::cpu.data 493717 # number of demand (read+write) hits 714system.cpu.l2cache.demand_hits::total 517766 # number of demand (read+write) hits 715system.cpu.l2cache.overall_hits::cpu.inst 24049 # number of overall hits 716system.cpu.l2cache.overall_hits::cpu.data 493717 # number of overall hits 717system.cpu.l2cache.overall_hits::total 517766 # number of overall hits 718system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses 719system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses 720system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2564 # number of ReadCleanReq misses 721system.cpu.l2cache.ReadCleanReq_misses::total 2564 # number of ReadCleanReq misses 722system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222590 # number of ReadSharedReq misses 723system.cpu.l2cache.ReadSharedReq_misses::total 222590 # number of ReadSharedReq misses 724system.cpu.l2cache.demand_misses::cpu.inst 2564 # number of demand (read+write) misses 725system.cpu.l2cache.demand_misses::cpu.data 288681 # number of demand (read+write) misses 726system.cpu.l2cache.demand_misses::total 291245 # number of demand (read+write) misses 727system.cpu.l2cache.overall_misses::cpu.inst 2564 # number of overall misses 728system.cpu.l2cache.overall_misses::cpu.data 288681 # number of overall misses 729system.cpu.l2cache.overall_misses::total 291245 # number of overall misses 730system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4932129000 # number of ReadExReq miss cycles 731system.cpu.l2cache.ReadExReq_miss_latency::total 4932129000 # number of ReadExReq miss cycles 732system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 196405000 # number of ReadCleanReq miss cycles 733system.cpu.l2cache.ReadCleanReq_miss_latency::total 196405000 # number of ReadCleanReq miss cycles 734system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18239788500 # number of ReadSharedReq miss cycles 735system.cpu.l2cache.ReadSharedReq_miss_latency::total 18239788500 # number of ReadSharedReq miss cycles 736system.cpu.l2cache.demand_miss_latency::cpu.inst 196405000 # number of demand (read+write) miss cycles 737system.cpu.l2cache.demand_miss_latency::cpu.data 23171917500 # number of demand (read+write) miss cycles 738system.cpu.l2cache.demand_miss_latency::total 23368322500 # number of demand (read+write) miss cycles 739system.cpu.l2cache.overall_miss_latency::cpu.inst 196405000 # number of overall miss cycles 740system.cpu.l2cache.overall_miss_latency::cpu.data 23171917500 # number of overall miss cycles 741system.cpu.l2cache.overall_miss_latency::total 23368322500 # number of overall miss cycles 742system.cpu.l2cache.WritebackDirty_accesses::writebacks 88712 # number of WritebackDirty accesses(hits+misses) 743system.cpu.l2cache.WritebackDirty_accesses::total 88712 # number of WritebackDirty accesses(hits+misses) 744system.cpu.l2cache.WritebackClean_accesses::writebacks 23528 # number of WritebackClean accesses(hits+misses) 745system.cpu.l2cache.WritebackClean_accesses::total 23528 # number of WritebackClean accesses(hits+misses) 746system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 747system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 748system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26613 # number of ReadCleanReq accesses(hits+misses) 749system.cpu.l2cache.ReadCleanReq_accesses::total 26613 # number of ReadCleanReq accesses(hits+misses) 750system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 713076 # number of ReadSharedReq accesses(hits+misses) 751system.cpu.l2cache.ReadSharedReq_accesses::total 713076 # number of ReadSharedReq accesses(hits+misses) 752system.cpu.l2cache.demand_accesses::cpu.inst 26613 # number of demand (read+write) accesses 753system.cpu.l2cache.demand_accesses::cpu.data 782398 # number of demand (read+write) accesses 754system.cpu.l2cache.demand_accesses::total 809011 # number of demand (read+write) accesses 755system.cpu.l2cache.overall_accesses::cpu.inst 26613 # number of overall (read+write) accesses 756system.cpu.l2cache.overall_accesses::cpu.data 782398 # number of overall (read+write) accesses 757system.cpu.l2cache.overall_accesses::total 809011 # number of overall (read+write) accesses 758system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses 759system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses 760system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096344 # miss rate for ReadCleanReq accesses 761system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096344 # miss rate for ReadCleanReq accesses 762system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312155 # miss rate for ReadSharedReq accesses 763system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312155 # miss rate for ReadSharedReq accesses 764system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096344 # miss rate for demand accesses 765system.cpu.l2cache.demand_miss_rate::cpu.data 0.368970 # miss rate for demand accesses 766system.cpu.l2cache.demand_miss_rate::total 0.360001 # miss rate for demand accesses 767system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096344 # miss rate for overall accesses 768system.cpu.l2cache.overall_miss_rate::cpu.data 0.368970 # miss rate for overall accesses 769system.cpu.l2cache.overall_miss_rate::total 0.360001 # miss rate for overall accesses 770system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.333389 # average ReadExReq miss latency 771system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.333389 # average ReadExReq miss latency 772system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76601.014041 # average ReadCleanReq miss latency 773system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76601.014041 # average ReadCleanReq miss latency 774system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81943.431870 # average ReadSharedReq miss latency 775system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81943.431870 # average ReadSharedReq miss latency 776system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency 777system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency 778system.cpu.l2cache.demand_avg_miss_latency::total 80235.961132 # average overall miss latency 779system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency 780system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency 781system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132 # average overall miss latency 782system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 785system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 787system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 788system.cpu.l2cache.fast_writes 0 # number of fast writes performed 789system.cpu.l2cache.cache_copies 0 # number of cache copies performed 790system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 791system.cpu.l2cache.writebacks::total 66098 # number of writebacks 792system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits 793system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits 794system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits 795system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits 796system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 797system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits 798system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits 799system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 800system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits 801system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits 802system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses 803system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses 804system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2559 # number of ReadCleanReq MSHR misses 805system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2559 # number of ReadCleanReq MSHR misses 806system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222563 # number of ReadSharedReq MSHR misses 807system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222563 # number of ReadSharedReq MSHR misses 808system.cpu.l2cache.demand_mshr_misses::cpu.inst 2559 # number of demand (read+write) MSHR misses 809system.cpu.l2cache.demand_mshr_misses::cpu.data 288654 # number of demand (read+write) MSHR misses 810system.cpu.l2cache.demand_mshr_misses::total 291213 # number of demand (read+write) MSHR misses 811system.cpu.l2cache.overall_mshr_misses::cpu.inst 2559 # number of overall MSHR misses 812system.cpu.l2cache.overall_mshr_misses::cpu.data 288654 # number of overall MSHR misses 813system.cpu.l2cache.overall_mshr_misses::total 291213 # number of overall MSHR misses 814system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4271219000 # number of ReadExReq MSHR miss cycles 815system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4271219000 # number of ReadExReq MSHR miss cycles 816system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170500500 # number of ReadCleanReq MSHR miss cycles 817system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170500500 # number of ReadCleanReq MSHR miss cycles 818system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16012410500 # number of ReadSharedReq MSHR miss cycles 819system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16012410500 # number of ReadSharedReq MSHR miss cycles 820system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170500500 # number of demand (read+write) MSHR miss cycles 821system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20283629500 # number of demand (read+write) MSHR miss cycles 822system.cpu.l2cache.demand_mshr_miss_latency::total 20454130000 # number of demand (read+write) MSHR miss cycles 823system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170500500 # number of overall MSHR miss cycles 824system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20283629500 # number of overall MSHR miss cycles 825system.cpu.l2cache.overall_mshr_miss_latency::total 20454130000 # number of overall MSHR miss cycles 826system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 827system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 828system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for ReadCleanReq accesses 829system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096156 # mshr miss rate for ReadCleanReq accesses 830system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312117 # mshr miss rate for ReadSharedReq accesses 831system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312117 # mshr miss rate for ReadSharedReq accesses 832system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for demand accesses 833system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for demand accesses 834system.cpu.l2cache.demand_mshr_miss_rate::total 0.359962 # mshr miss rate for demand accesses 835system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for overall accesses 836system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for overall accesses 837system.cpu.l2cache.overall_mshr_miss_rate::total 0.359962 # mshr miss rate for overall accesses 838system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389 # average ReadExReq mshr miss latency 839system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389 # average ReadExReq mshr miss latency 840system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291 # average ReadCleanReq mshr miss latency 841system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291 # average ReadCleanReq mshr miss latency 842system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797 # average ReadSharedReq mshr miss latency 843system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797 # average ReadSharedReq mshr miss latency 844system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency 845system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency 846system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency 847system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency 848system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency 849system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency 850system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 851system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter. 852system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 853system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 854system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. 855system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 856system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 857system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution 858system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution 859system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution 860system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution 861system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 862system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution 865system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78084 # Packet count per connected master and slave (bytes) 866system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343098 # Packet count per connected master and slave (bytes) 867system.cpu.toL2Bus.pkt_count::total 2421182 # Packet count per connected master and slave (bytes) 868system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3294144 # Cumulative packet size per connected master and slave (bytes) 869system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55751040 # Cumulative packet size per connected master and slave (bytes) 870system.cpu.toL2Bus.pkt_size::total 59045184 # Cumulative packet size per connected master and slave (bytes) 871system.cpu.toL2Bus.snoops 258808 # Total snoops (count) 872system.cpu.toL2Bus.snoop_fanout::samples 1067819 # Request fanout histogram 873system.cpu.toL2Bus.snoop_fanout::mean 0.005072 # Request fanout histogram 874system.cpu.toL2Bus.snoop_fanout::stdev 0.071235 # Request fanout histogram 875system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 876system.cpu.toL2Bus.snoop_fanout::0 1062418 99.49% 99.49% # Request fanout histogram 877system.cpu.toL2Bus.snoop_fanout::1 5386 0.50% 100.00% # Request fanout histogram 878system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram 879system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 880system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 881system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 882system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram 883system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks) 884system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 885system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks) 886system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 887system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks) 888system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 889system.membus.trans_dist::ReadResp 225121 # Transaction distribution 890system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 891system.membus.trans_dist::CleanEvict 190682 # Transaction distribution 892system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 893system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 894system.membus.trans_dist::ReadSharedReq 225121 # Transaction distribution 895system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839204 # Packet count per connected master and slave (bytes) 896system.membus.pkt_count::total 839204 # Packet count per connected master and slave (bytes) 897system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22867840 # Cumulative packet size per connected master and slave (bytes) 898system.membus.pkt_size::total 22867840 # Cumulative packet size per connected master and slave (bytes) 899system.membus.snoops 0 # Total snoops (count) 900system.membus.snoop_fanout::samples 547992 # Request fanout histogram 901system.membus.snoop_fanout::mean 0 # Request fanout histogram 902system.membus.snoop_fanout::stdev 0 # Request fanout histogram 903system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 904system.membus.snoop_fanout::0 547992 100.00% 100.00% # Request fanout histogram 905system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 906system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 907system.membus.snoop_fanout::min_value 0 # Request fanout histogram 908system.membus.snoop_fanout::max_value 0 # Request fanout histogram 909system.membus.snoop_fanout::total 547992 # Request fanout histogram 910system.membus.reqLayer0.occupancy 916865000 # Layer occupancy (ticks) 911system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 912system.membus.respLayer1.occupancy 1554037500 # Layer occupancy (ticks) 913system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 914 915---------- End Simulation Statistics ---------- 916