stats.txt revision 10352:5f1f92bf76ee
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.537826 # Number of seconds simulated 4sim_ticks 537826498500 # Number of ticks simulated 5final_tick 537826498500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 114564 # Simulator instruction rate (inst/s) 8host_op_rate 141043 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 96175687 # Simulator tick rate (ticks/s) 10host_mem_usage 263048 # Number of bytes of host memory used 11host_seconds 5592.13 # Real time elapsed on the host 12sim_insts 640655084 # Number of instructions simulated 13sim_ops 788730743 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18593984 # Number of bytes read from this memory 17system.physmem.bytes_read::total 18593984 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 165056 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 165056 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 21system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 290531 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 290531 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 34572458 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 34572458 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 306895 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 306895 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 7865496 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 7865496 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 7865496 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 34572458 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 42437954 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 290531 # Number of read requests accepted 36system.physmem.writeReqs 66098 # Number of write requests accepted 37system.physmem.readBursts 290531 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 18574336 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue 41system.physmem.bytesWritten 4229312 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 18593984 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 47system.physmem.perBankRdBursts::0 18283 # Per bank write bursts 48system.physmem.perBankRdBursts::1 18133 # Per bank write bursts 49system.physmem.perBankRdBursts::2 18223 # Per bank write bursts 50system.physmem.perBankRdBursts::3 18187 # Per bank write bursts 51system.physmem.perBankRdBursts::4 18258 # Per bank write bursts 52system.physmem.perBankRdBursts::5 18313 # Per bank write bursts 53system.physmem.perBankRdBursts::6 18090 # Per bank write bursts 54system.physmem.perBankRdBursts::7 17910 # Per bank write bursts 55system.physmem.perBankRdBursts::8 17943 # Per bank write bursts 56system.physmem.perBankRdBursts::9 17966 # Per bank write bursts 57system.physmem.perBankRdBursts::10 18023 # Per bank write bursts 58system.physmem.perBankRdBursts::11 18118 # Per bank write bursts 59system.physmem.perBankRdBursts::12 18159 # Per bank write bursts 60system.physmem.perBankRdBursts::13 18277 # Per bank write bursts 61system.physmem.perBankRdBursts::14 18081 # Per bank write bursts 62system.physmem.perBankRdBursts::15 18260 # Per bank write bursts 63system.physmem.perBankWrBursts::0 4174 # Per bank write bursts 64system.physmem.perBankWrBursts::1 4102 # Per bank write bursts 65system.physmem.perBankWrBursts::2 4137 # Per bank write bursts 66system.physmem.perBankWrBursts::3 4147 # Per bank write bursts 67system.physmem.perBankWrBursts::4 4225 # Per bank write bursts 68system.physmem.perBankWrBursts::5 4225 # Per bank write bursts 69system.physmem.perBankWrBursts::6 4171 # Per bank write bursts 70system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 71system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 72system.physmem.perBankWrBursts::9 4093 # Per bank write bursts 73system.physmem.perBankWrBursts::10 4094 # Per bank write bursts 74system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 75system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 76system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 77system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 78system.physmem.perBankWrBursts::15 4138 # Per bank write bursts 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 81system.physmem.totGap 537826410500 # Total gap between requests 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) 88system.physmem.readPktSize::6 290531 # Read request sizes (log2) 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) 95system.physmem.writePktSize::6 66098 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 289825 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 128system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::15 975 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 978 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 4010 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 4008 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 4008 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 4008 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 4008 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 4008 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 192system.physmem.bytesPerActivate::samples 111452 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 204.586154 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 132.570788 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 256.465119 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 47032 42.20% 42.20% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 43501 39.03% 81.23% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 8758 7.86% 89.09% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 741 0.66% 89.75% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 1179 1.06% 90.81% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 1268 1.14% 91.95% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 550 0.49% 92.44% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 543 0.49% 92.93% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 7880 7.07% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 111452 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 4008 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 48.655439 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::gmean 36.051521 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::stdev 507.704420 # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::0-1023 4005 99.93% 99.93% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::total 4008 # Reads before turning the bus around for writes 215system.physmem.wrPerTurnAround::samples 4008 # Writes before turning the bus around for reads 216system.physmem.wrPerTurnAround::mean 16.487774 # Writes before turning the bus around for reads 217system.physmem.wrPerTurnAround::gmean 16.466259 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::stdev 0.859394 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::16 3030 75.60% 75.60% # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::17 3 0.07% 75.67% # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::18 973 24.28% 99.95% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::total 4008 # Writes before turning the bus around for reads 224system.physmem.totQLat 3341298000 # Total ticks spent queuing 225system.physmem.totMemAccLat 8782998000 # Total ticks spent from burst creation until serviced by the DRAM 226system.physmem.totBusLat 1451120000 # Total ticks spent in databus transfers 227system.physmem.avgQLat 11512.82 # Average queueing delay per DRAM burst 228system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 229system.physmem.avgMemAccLat 30262.82 # Average memory access latency per DRAM burst 230system.physmem.avgRdBW 34.54 # Average DRAM read bandwidth in MiByte/s 231system.physmem.avgWrBW 7.86 # Average achieved write bandwidth in MiByte/s 232system.physmem.avgRdBWSys 34.57 # Average system read bandwidth in MiByte/s 233system.physmem.avgWrBWSys 7.87 # Average system write bandwidth in MiByte/s 234system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 235system.physmem.busUtil 0.33 # Data bus utilization in percentage 236system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads 237system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 238system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 239system.physmem.avgWrQLen 29.26 # Average write queue length when enqueuing 240system.physmem.readRowHits 194846 # Number of row buffer hits during reads 241system.physmem.writeRowHits 49995 # Number of row buffer hits during writes 242system.physmem.readRowHitRate 67.14 # Row buffer hit rate for reads 243system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes 244system.physmem.avgGap 1508083.78 # Average gap between requests 245system.physmem.pageHitRate 68.71 # Row buffer hit rate, read and write combined 246system.physmem.memoryStateTime::IDLE 253517983250 # Time in different power states 247system.physmem.memoryStateTime::REF 17958980000 # Time in different power states 248system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 249system.physmem.memoryStateTime::ACT 266342956750 # Time in different power states 250system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 251system.membus.throughput 42437954 # Throughput (bytes/s) 252system.membus.trans_dist::ReadReq 224439 # Transaction distribution 253system.membus.trans_dist::ReadResp 224439 # Transaction distribution 254system.membus.trans_dist::Writeback 66098 # Transaction distribution 255system.membus.trans_dist::ReadExReq 66092 # Transaction distribution 256system.membus.trans_dist::ReadExResp 66092 # Transaction distribution 257system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647160 # Packet count per connected master and slave (bytes) 258system.membus.pkt_count::total 647160 # Packet count per connected master and slave (bytes) 259system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824256 # Cumulative packet size per connected master and slave (bytes) 260system.membus.tot_pkt_size::total 22824256 # Cumulative packet size per connected master and slave (bytes) 261system.membus.data_through_bus 22824256 # Total data (bytes) 262system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 263system.membus.reqLayer0.occupancy 974430000 # Layer occupancy (ticks) 264system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 265system.membus.respLayer1.occupancy 2738631750 # Layer occupancy (ticks) 266system.membus.respLayer1.utilization 0.5 # Layer utilization (%) 267system.cpu_clk_domain.clock 500 # Clock period in ticks 268system.cpu.branchPred.lookups 154837020 # Number of BP lookups 269system.cpu.branchPred.condPredicted 104970668 # Number of conditional branches predicted 270system.cpu.branchPred.condIncorrect 12892448 # Number of conditional branches incorrect 271system.cpu.branchPred.BTBLookups 106220966 # Number of BTB lookups 272system.cpu.branchPred.BTBHits 82647169 # Number of BTB hits 273system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 274system.cpu.branchPred.BTBHitPct 77.806832 # BTB Hit Percentage 275system.cpu.branchPred.usedRAS 19441660 # Number of times the RAS was used to get a target. 276system.cpu.branchPred.RASInCorrect 1323 # Number of incorrect RAS predictions. 277system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 278system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 279system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 280system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 281system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 282system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 283system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 285system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 286system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 287system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 288system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 289system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 290system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 291system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 292system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 293system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 294system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 295system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 296system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 297system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 298system.cpu.dtb.inst_hits 0 # ITB inst hits 299system.cpu.dtb.inst_misses 0 # ITB inst misses 300system.cpu.dtb.read_hits 0 # DTB read hits 301system.cpu.dtb.read_misses 0 # DTB read misses 302system.cpu.dtb.write_hits 0 # DTB write hits 303system.cpu.dtb.write_misses 0 # DTB write misses 304system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 305system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 306system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 307system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 308system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 309system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 310system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 311system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 312system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 313system.cpu.dtb.read_accesses 0 # DTB read accesses 314system.cpu.dtb.write_accesses 0 # DTB write accesses 315system.cpu.dtb.inst_accesses 0 # ITB inst accesses 316system.cpu.dtb.hits 0 # DTB hits 317system.cpu.dtb.misses 0 # DTB misses 318system.cpu.dtb.accesses 0 # DTB accesses 319system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 320system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 321system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 322system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 323system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 324system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 325system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 326system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 327system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 328system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 329system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 330system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 331system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 332system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 333system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 334system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 335system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 336system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 337system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 338system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 339system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 340system.cpu.itb.inst_hits 0 # ITB inst hits 341system.cpu.itb.inst_misses 0 # ITB inst misses 342system.cpu.itb.read_hits 0 # DTB read hits 343system.cpu.itb.read_misses 0 # DTB read misses 344system.cpu.itb.write_hits 0 # DTB write hits 345system.cpu.itb.write_misses 0 # DTB write misses 346system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 347system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 348system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 349system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 350system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 351system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 352system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 353system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.itb.read_accesses 0 # DTB read accesses 356system.cpu.itb.write_accesses 0 # DTB write accesses 357system.cpu.itb.inst_accesses 0 # ITB inst accesses 358system.cpu.itb.hits 0 # DTB hits 359system.cpu.itb.misses 0 # DTB misses 360system.cpu.itb.accesses 0 # DTB accesses 361system.cpu.workload.num_syscalls 673 # Number of system calls 362system.cpu.numCycles 1075652997 # number of cpu cycles simulated 363system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 364system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 365system.cpu.committedInsts 640655084 # Number of instructions committed 366system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed 367system.cpu.discardedOps 25219021 # Number of ops (including micro ops) which were discarded before commit 368system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 369system.cpu.cpi 1.678989 # CPI: cycles per instruction 370system.cpu.ipc 0.595596 # IPC: instructions per cycle 371system.cpu.tickCycles 1020176275 # Number of cycles that the object actually ticked 372system.cpu.idleCycles 55476722 # Total number of cycles that the object has spent stopped 373system.cpu.icache.tags.replacements 23597 # number of replacements 374system.cpu.icache.tags.tagsinuse 1711.182078 # Cycle average of tags in use 375system.cpu.icache.tags.total_refs 289999264 # Total number of references to valid blocks. 376system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. 377system.cpu.icache.tags.avg_refs 11441.167160 # Average number of references to valid blocks. 378system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 379system.cpu.icache.tags.occ_blocks::cpu.inst 1711.182078 # Average occupied blocks per requestor 380system.cpu.icache.tags.occ_percent::cpu.inst 0.835538 # Average percentage of cache occupancy 381system.cpu.icache.tags.occ_percent::total 0.835538 # Average percentage of cache occupancy 382system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id 383system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 384system.cpu.icache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id 385system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id 386system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id 387system.cpu.icache.tags.tag_accesses 580074571 # Number of tag accesses 388system.cpu.icache.tags.data_accesses 580074571 # Number of data accesses 389system.cpu.icache.ReadReq_hits::cpu.inst 289999264 # number of ReadReq hits 390system.cpu.icache.ReadReq_hits::total 289999264 # number of ReadReq hits 391system.cpu.icache.demand_hits::cpu.inst 289999264 # number of demand (read+write) hits 392system.cpu.icache.demand_hits::total 289999264 # number of demand (read+write) hits 393system.cpu.icache.overall_hits::cpu.inst 289999264 # number of overall hits 394system.cpu.icache.overall_hits::total 289999264 # number of overall hits 395system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses 396system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses 397system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses 398system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses 399system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses 400system.cpu.icache.overall_misses::total 25348 # number of overall misses 401system.cpu.icache.ReadReq_miss_latency::cpu.inst 480804246 # number of ReadReq miss cycles 402system.cpu.icache.ReadReq_miss_latency::total 480804246 # number of ReadReq miss cycles 403system.cpu.icache.demand_miss_latency::cpu.inst 480804246 # number of demand (read+write) miss cycles 404system.cpu.icache.demand_miss_latency::total 480804246 # number of demand (read+write) miss cycles 405system.cpu.icache.overall_miss_latency::cpu.inst 480804246 # number of overall miss cycles 406system.cpu.icache.overall_miss_latency::total 480804246 # number of overall miss cycles 407system.cpu.icache.ReadReq_accesses::cpu.inst 290024612 # number of ReadReq accesses(hits+misses) 408system.cpu.icache.ReadReq_accesses::total 290024612 # number of ReadReq accesses(hits+misses) 409system.cpu.icache.demand_accesses::cpu.inst 290024612 # number of demand (read+write) accesses 410system.cpu.icache.demand_accesses::total 290024612 # number of demand (read+write) accesses 411system.cpu.icache.overall_accesses::cpu.inst 290024612 # number of overall (read+write) accesses 412system.cpu.icache.overall_accesses::total 290024612 # number of overall (read+write) accesses 413system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses 414system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses 415system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses 416system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses 417system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses 418system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses 419system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.133423 # average ReadReq miss latency 420system.cpu.icache.ReadReq_avg_miss_latency::total 18968.133423 # average ReadReq miss latency 421system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency 422system.cpu.icache.demand_avg_miss_latency::total 18968.133423 # average overall miss latency 423system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.133423 # average overall miss latency 424system.cpu.icache.overall_avg_miss_latency::total 18968.133423 # average overall miss latency 425system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 426system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 427system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 428system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 429system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 430system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 431system.cpu.icache.fast_writes 0 # number of fast writes performed 432system.cpu.icache.cache_copies 0 # number of cache copies performed 433system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses 434system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses 435system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses 436system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses 437system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses 438system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses 439system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429006754 # number of ReadReq MSHR miss cycles 440system.cpu.icache.ReadReq_mshr_miss_latency::total 429006754 # number of ReadReq MSHR miss cycles 441system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429006754 # number of demand (read+write) MSHR miss cycles 442system.cpu.icache.demand_mshr_miss_latency::total 429006754 # number of demand (read+write) MSHR miss cycles 443system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429006754 # number of overall MSHR miss cycles 444system.cpu.icache.overall_mshr_miss_latency::total 429006754 # number of overall MSHR miss cycles 445system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses 446system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses 447system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses 448system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses 449system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses 450system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses 451system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.678633 # average ReadReq mshr miss latency 452system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.678633 # average ReadReq mshr miss latency 453system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency 454system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency 455system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.678633 # average overall mshr miss latency 456system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.678633 # average overall mshr miss latency 457system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.cpu.toL2Bus.throughput 107000990 # Throughput (bytes/s) 459system.cpu.toL2Bus.trans_dist::ReadReq 738445 # Transaction distribution 460system.cpu.toL2Bus.trans_dist::ReadResp 738444 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution 464system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) 465system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656260 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.pkt_count::total 1706955 # Packet count per connected master and slave (bytes) 467system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) 468system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55925760 # Cumulative packet size per connected master and slave (bytes) 469system.cpu.toL2Bus.tot_pkt_size::total 57547968 # Cumulative packet size per connected master and slave (bytes) 470system.cpu.toL2Bus.data_through_bus 57547968 # Total data (bytes) 471system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 472system.cpu.toL2Bus.reqLayer0.occupancy 541014000 # Layer occupancy (ticks) 473system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 474system.cpu.toL2Bus.respLayer0.occupancy 38572246 # Layer occupancy (ticks) 475system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 476system.cpu.toL2Bus.respLayer1.occupancy 1224995475 # Layer occupancy (ticks) 477system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 478system.cpu.l2cache.tags.replacements 257750 # number of replacements 479system.cpu.l2cache.tags.tagsinuse 32582.970291 # Cycle average of tags in use 480system.cpu.l2cache.tags.total_refs 539180 # Total number of references to valid blocks. 481system.cpu.l2cache.tags.sampled_refs 290494 # Sample count of references to valid blocks. 482system.cpu.l2cache.tags.avg_refs 1.856080 # Average number of references to valid blocks. 483system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 484system.cpu.l2cache.tags.occ_blocks::writebacks 2866.246405 # Average occupied blocks per requestor 485system.cpu.l2cache.tags.occ_blocks::cpu.inst 29716.723886 # Average occupied blocks per requestor 486system.cpu.l2cache.tags.occ_percent::writebacks 0.087471 # Average percentage of cache occupancy 487system.cpu.l2cache.tags.occ_percent::cpu.inst 0.906882 # Average percentage of cache occupancy 488system.cpu.l2cache.tags.occ_percent::total 0.994353 # Average percentage of cache occupancy 489system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id 490system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 491system.cpu.l2cache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id 492system.cpu.l2cache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id 493system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2831 # Occupied blocks per task id 494system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29389 # Occupied blocks per task id 495system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id 496system.cpu.l2cache.tags.tag_accesses 7553321 # Number of tag accesses 497system.cpu.l2cache.tags.data_accesses 7553321 # Number of data accesses 498system.cpu.l2cache.ReadReq_hits::cpu.inst 513976 # number of ReadReq hits 499system.cpu.l2cache.ReadReq_hits::total 513976 # number of ReadReq hits 500system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits 501system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits 502system.cpu.l2cache.ReadExReq_hits::cpu.inst 3231 # number of ReadExReq hits 503system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 504system.cpu.l2cache.demand_hits::cpu.inst 517207 # number of demand (read+write) hits 505system.cpu.l2cache.demand_hits::total 517207 # number of demand (read+write) hits 506system.cpu.l2cache.overall_hits::cpu.inst 517207 # number of overall hits 507system.cpu.l2cache.overall_hits::total 517207 # number of overall hits 508system.cpu.l2cache.ReadReq_misses::cpu.inst 224469 # number of ReadReq misses 509system.cpu.l2cache.ReadReq_misses::total 224469 # number of ReadReq misses 510system.cpu.l2cache.ReadExReq_misses::cpu.inst 66092 # number of ReadExReq misses 511system.cpu.l2cache.ReadExReq_misses::total 66092 # number of ReadExReq misses 512system.cpu.l2cache.demand_misses::cpu.inst 290561 # number of demand (read+write) misses 513system.cpu.l2cache.demand_misses::total 290561 # number of demand (read+write) misses 514system.cpu.l2cache.overall_misses::cpu.inst 290561 # number of overall misses 515system.cpu.l2cache.overall_misses::total 290561 # number of overall misses 516system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16737523000 # number of ReadReq miss cycles 517system.cpu.l2cache.ReadReq_miss_latency::total 16737523000 # number of ReadReq miss cycles 518system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4423362750 # number of ReadExReq miss cycles 519system.cpu.l2cache.ReadExReq_miss_latency::total 4423362750 # number of ReadExReq miss cycles 520system.cpu.l2cache.demand_miss_latency::cpu.inst 21160885750 # number of demand (read+write) miss cycles 521system.cpu.l2cache.demand_miss_latency::total 21160885750 # number of demand (read+write) miss cycles 522system.cpu.l2cache.overall_miss_latency::cpu.inst 21160885750 # number of overall miss cycles 523system.cpu.l2cache.overall_miss_latency::total 21160885750 # number of overall miss cycles 524system.cpu.l2cache.ReadReq_accesses::cpu.inst 738445 # number of ReadReq accesses(hits+misses) 525system.cpu.l2cache.ReadReq_accesses::total 738445 # number of ReadReq accesses(hits+misses) 526system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) 527system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) 528system.cpu.l2cache.ReadExReq_accesses::cpu.inst 69323 # number of ReadExReq accesses(hits+misses) 529system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) 530system.cpu.l2cache.demand_accesses::cpu.inst 807768 # number of demand (read+write) accesses 531system.cpu.l2cache.demand_accesses::total 807768 # number of demand (read+write) accesses 532system.cpu.l2cache.overall_accesses::cpu.inst 807768 # number of overall (read+write) accesses 533system.cpu.l2cache.overall_accesses::total 807768 # number of overall (read+write) accesses 534system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.303975 # miss rate for ReadReq accesses 535system.cpu.l2cache.ReadReq_miss_rate::total 0.303975 # miss rate for ReadReq accesses 536system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.953392 # miss rate for ReadExReq accesses 537system.cpu.l2cache.ReadExReq_miss_rate::total 0.953392 # miss rate for ReadExReq accesses 538system.cpu.l2cache.demand_miss_rate::cpu.inst 0.359708 # miss rate for demand accesses 539system.cpu.l2cache.demand_miss_rate::total 0.359708 # miss rate for demand accesses 540system.cpu.l2cache.overall_miss_rate::cpu.inst 0.359708 # miss rate for overall accesses 541system.cpu.l2cache.overall_miss_rate::total 0.359708 # miss rate for overall accesses 542system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74564.964427 # average ReadReq miss latency 543system.cpu.l2cache.ReadReq_avg_miss_latency::total 74564.964427 # average ReadReq miss latency 544system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66927.355051 # average ReadExReq miss latency 545system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66927.355051 # average ReadExReq miss latency 546system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency 547system.cpu.l2cache.demand_avg_miss_latency::total 72827.687646 # average overall miss latency 548system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72827.687646 # average overall miss latency 549system.cpu.l2cache.overall_avg_miss_latency::total 72827.687646 # average overall miss latency 550system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 551system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 552system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 553system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 554system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 555system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 556system.cpu.l2cache.fast_writes 0 # number of fast writes performed 557system.cpu.l2cache.cache_copies 0 # number of cache copies performed 558system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 559system.cpu.l2cache.writebacks::total 66098 # number of writebacks 560system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 29 # number of ReadReq MSHR hits 561system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits 562system.cpu.l2cache.demand_mshr_hits::cpu.inst 29 # number of demand (read+write) MSHR hits 563system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits 564system.cpu.l2cache.overall_mshr_hits::cpu.inst 29 # number of overall MSHR hits 565system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits 566system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 224440 # number of ReadReq MSHR misses 567system.cpu.l2cache.ReadReq_mshr_misses::total 224440 # number of ReadReq MSHR misses 568system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66092 # number of ReadExReq MSHR misses 569system.cpu.l2cache.ReadExReq_mshr_misses::total 66092 # number of ReadExReq MSHR misses 570system.cpu.l2cache.demand_mshr_misses::cpu.inst 290532 # number of demand (read+write) MSHR misses 571system.cpu.l2cache.demand_mshr_misses::total 290532 # number of demand (read+write) MSHR misses 572system.cpu.l2cache.overall_mshr_misses::cpu.inst 290532 # number of overall MSHR misses 573system.cpu.l2cache.overall_mshr_misses::total 290532 # number of overall MSHR misses 574system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13902147000 # number of ReadReq MSHR miss cycles 575system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13902147000 # number of ReadReq MSHR miss cycles 576system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3594959250 # number of ReadExReq MSHR miss cycles 577system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3594959250 # number of ReadExReq MSHR miss cycles 578system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17497106250 # number of demand (read+write) MSHR miss cycles 579system.cpu.l2cache.demand_mshr_miss_latency::total 17497106250 # number of demand (read+write) MSHR miss cycles 580system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17497106250 # number of overall MSHR miss cycles 581system.cpu.l2cache.overall_mshr_miss_latency::total 17497106250 # number of overall MSHR miss cycles 582system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.303936 # mshr miss rate for ReadReq accesses 583system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303936 # mshr miss rate for ReadReq accesses 584system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.953392 # mshr miss rate for ReadExReq accesses 585system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953392 # mshr miss rate for ReadExReq accesses 586system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for demand accesses 587system.cpu.l2cache.demand_mshr_miss_rate::total 0.359673 # mshr miss rate for demand accesses 588system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.359673 # mshr miss rate for overall accesses 589system.cpu.l2cache.overall_mshr_miss_rate::total 0.359673 # mshr miss rate for overall accesses 590system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.485475 # average ReadReq mshr miss latency 591system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61941.485475 # average ReadReq mshr miss latency 592system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54393.258639 # average ReadExReq mshr miss latency 593system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54393.258639 # average ReadExReq mshr miss latency 594system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency 595system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency 596system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60224.368572 # average overall mshr miss latency 597system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60224.368572 # average overall mshr miss latency 598system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 599system.cpu.dcache.tags.replacements 778324 # number of replacements 600system.cpu.dcache.tags.tagsinuse 4092.650508 # Cycle average of tags in use 601system.cpu.dcache.tags.total_refs 378453595 # Total number of references to valid blocks. 602system.cpu.dcache.tags.sampled_refs 782420 # Sample count of references to valid blocks. 603system.cpu.dcache.tags.avg_refs 483.696218 # Average number of references to valid blocks. 604system.cpu.dcache.tags.warmup_cycle 745524250 # Cycle when the warmup percentage was hit. 605system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.650508 # Average occupied blocks per requestor 606system.cpu.dcache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy 607system.cpu.dcache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy 608system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 609system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 610system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::3 1354 # Occupied blocks per task id 613system.cpu.dcache.tags.age_task_id_blocks_1024::4 1577 # Occupied blocks per task id 614system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 615system.cpu.dcache.tags.tag_accesses 759392478 # Number of tag accesses 616system.cpu.dcache.tags.data_accesses 759392478 # Number of data accesses 617system.cpu.dcache.ReadReq_hits::cpu.inst 249628224 # number of ReadReq hits 618system.cpu.dcache.ReadReq_hits::total 249628224 # number of ReadReq hits 619system.cpu.dcache.WriteReq_hits::cpu.inst 128813893 # number of WriteReq hits 620system.cpu.dcache.WriteReq_hits::total 128813893 # number of WriteReq hits 621system.cpu.dcache.LoadLockedReq_hits::cpu.inst 5739 # number of LoadLockedReq hits 622system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 623system.cpu.dcache.StoreCondReq_hits::cpu.inst 5739 # number of StoreCondReq hits 624system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 625system.cpu.dcache.demand_hits::cpu.inst 378442117 # number of demand (read+write) hits 626system.cpu.dcache.demand_hits::total 378442117 # number of demand (read+write) hits 627system.cpu.dcache.overall_hits::cpu.inst 378442117 # number of overall hits 628system.cpu.dcache.overall_hits::total 378442117 # number of overall hits 629system.cpu.dcache.ReadReq_misses::cpu.inst 713850 # number of ReadReq misses 630system.cpu.dcache.ReadReq_misses::total 713850 # number of ReadReq misses 631system.cpu.dcache.WriteReq_misses::cpu.inst 137584 # number of WriteReq misses 632system.cpu.dcache.WriteReq_misses::total 137584 # number of WriteReq misses 633system.cpu.dcache.demand_misses::cpu.inst 851434 # number of demand (read+write) misses 634system.cpu.dcache.demand_misses::total 851434 # number of demand (read+write) misses 635system.cpu.dcache.overall_misses::cpu.inst 851434 # number of overall misses 636system.cpu.dcache.overall_misses::total 851434 # number of overall misses 637system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23698499970 # number of ReadReq miss cycles 638system.cpu.dcache.ReadReq_miss_latency::total 23698499970 # number of ReadReq miss cycles 639system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9186329500 # number of WriteReq miss cycles 640system.cpu.dcache.WriteReq_miss_latency::total 9186329500 # number of WriteReq miss cycles 641system.cpu.dcache.demand_miss_latency::cpu.inst 32884829470 # number of demand (read+write) miss cycles 642system.cpu.dcache.demand_miss_latency::total 32884829470 # number of demand (read+write) miss cycles 643system.cpu.dcache.overall_miss_latency::cpu.inst 32884829470 # number of overall miss cycles 644system.cpu.dcache.overall_miss_latency::total 32884829470 # number of overall miss cycles 645system.cpu.dcache.ReadReq_accesses::cpu.inst 250342074 # number of ReadReq accesses(hits+misses) 646system.cpu.dcache.ReadReq_accesses::total 250342074 # number of ReadReq accesses(hits+misses) 647system.cpu.dcache.WriteReq_accesses::cpu.inst 128951477 # number of WriteReq accesses(hits+misses) 648system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 649system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 5739 # number of LoadLockedReq accesses(hits+misses) 650system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 651system.cpu.dcache.StoreCondReq_accesses::cpu.inst 5739 # number of StoreCondReq accesses(hits+misses) 652system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 653system.cpu.dcache.demand_accesses::cpu.inst 379293551 # number of demand (read+write) accesses 654system.cpu.dcache.demand_accesses::total 379293551 # number of demand (read+write) accesses 655system.cpu.dcache.overall_accesses::cpu.inst 379293551 # number of overall (read+write) accesses 656system.cpu.dcache.overall_accesses::total 379293551 # number of overall (read+write) accesses 657system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002851 # miss rate for ReadReq accesses 658system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses 659system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.001067 # miss rate for WriteReq accesses 660system.cpu.dcache.WriteReq_miss_rate::total 0.001067 # miss rate for WriteReq accesses 661system.cpu.dcache.demand_miss_rate::cpu.inst 0.002245 # miss rate for demand accesses 662system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses 663system.cpu.dcache.overall_miss_rate::cpu.inst 0.002245 # miss rate for overall accesses 664system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses 665system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 33198.150830 # average ReadReq miss latency 666system.cpu.dcache.ReadReq_avg_miss_latency::total 33198.150830 # average ReadReq miss latency 667system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66768.879376 # average WriteReq miss latency 668system.cpu.dcache.WriteReq_avg_miss_latency::total 66768.879376 # average WriteReq miss latency 669system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency 670system.cpu.dcache.demand_avg_miss_latency::total 38622.875608 # average overall miss latency 671system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38622.875608 # average overall miss latency 672system.cpu.dcache.overall_avg_miss_latency::total 38622.875608 # average overall miss latency 673system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 674system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 675system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 676system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 677system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 678system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 679system.cpu.dcache.fast_writes 0 # number of fast writes performed 680system.cpu.dcache.cache_copies 0 # number of cache copies performed 681system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks 682system.cpu.dcache.writebacks::total 91420 # number of writebacks 683system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 753 # number of ReadReq MSHR hits 684system.cpu.dcache.ReadReq_mshr_hits::total 753 # number of ReadReq MSHR hits 685system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 68261 # number of WriteReq MSHR hits 686system.cpu.dcache.WriteReq_mshr_hits::total 68261 # number of WriteReq MSHR hits 687system.cpu.dcache.demand_mshr_hits::cpu.inst 69014 # number of demand (read+write) MSHR hits 688system.cpu.dcache.demand_mshr_hits::total 69014 # number of demand (read+write) MSHR hits 689system.cpu.dcache.overall_mshr_hits::cpu.inst 69014 # number of overall MSHR hits 690system.cpu.dcache.overall_mshr_hits::total 69014 # number of overall MSHR hits 691system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 713097 # number of ReadReq MSHR misses 692system.cpu.dcache.ReadReq_mshr_misses::total 713097 # number of ReadReq MSHR misses 693system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 69323 # number of WriteReq MSHR misses 694system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses 695system.cpu.dcache.demand_mshr_misses::cpu.inst 782420 # number of demand (read+write) MSHR misses 696system.cpu.dcache.demand_mshr_misses::total 782420 # number of demand (read+write) MSHR misses 697system.cpu.dcache.overall_mshr_misses::cpu.inst 782420 # number of overall MSHR misses 698system.cpu.dcache.overall_mshr_misses::total 782420 # number of overall MSHR misses 699system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 22186804275 # number of ReadReq MSHR miss cycles 700system.cpu.dcache.ReadReq_mshr_miss_latency::total 22186804275 # number of ReadReq MSHR miss cycles 701system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4524997250 # number of WriteReq MSHR miss cycles 702system.cpu.dcache.WriteReq_mshr_miss_latency::total 4524997250 # number of WriteReq MSHR miss cycles 703system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26711801525 # number of demand (read+write) MSHR miss cycles 704system.cpu.dcache.demand_mshr_miss_latency::total 26711801525 # number of demand (read+write) MSHR miss cycles 705system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26711801525 # number of overall MSHR miss cycles 706system.cpu.dcache.overall_mshr_miss_latency::total 26711801525 # number of overall MSHR miss cycles 707system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002848 # mshr miss rate for ReadReq accesses 708system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses 709system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000538 # mshr miss rate for WriteReq accesses 710system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 711system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for demand accesses 712system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses 713system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002063 # mshr miss rate for overall accesses 714system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses 715system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.304747 # average ReadReq mshr miss latency 716system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31113.304747 # average ReadReq mshr miss latency 717system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 65274.111767 # average WriteReq mshr miss latency 718system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65274.111767 # average WriteReq mshr miss latency 719system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency 720system.cpu.dcache.demand_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency 721system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 34139.977921 # average overall mshr miss latency 722system.cpu.dcache.overall_avg_mshr_miss_latency::total 34139.977921 # average overall mshr miss latency 723system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 724 725---------- End Simulation Statistics ---------- 726