stats.txt revision 11201:b1bd4afb6b16
12SN/A 21762SN/A---------- Begin Simulation Statistics ---------- 32SN/Asim_seconds 0.517291 # Number of seconds simulated 42SN/Asim_ticks 517291025500 # Number of ticks simulated 52SN/Afinal_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 62SN/Asim_freq 1000000000000 # Frequency of simulated ticks 72SN/Ahost_inst_rate 635145 # Simulator instruction rate (inst/s) 82SN/Ahost_op_rate 762516 # Simulator op (including micro ops) rate (op/s) 92SN/Ahost_tick_rate 1204648551 # Simulator tick rate (ticks/s) 102SN/Ahost_mem_usage 323584 # Number of bytes of host memory used 112SN/Ahost_seconds 429.41 # Real time elapsed on the host 122SN/Asim_insts 272739286 # Number of instructions simulated 132SN/Asim_ops 327433744 # Number of ops (including micro ops) simulated 142SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 152SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 162SN/Asystem.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory 172SN/Asystem.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory 182SN/Asystem.physmem.bytes_read::total 437248 # Number of bytes read from this memory 192SN/Asystem.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory 202SN/Asystem.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory 212SN/Asystem.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory 222SN/Asystem.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory 232SN/Asystem.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 242SN/Asystem.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) 252SN/Asystem.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) 262SN/Asystem.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) 272665Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) 282665Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) 292741Sksewell@umich.edusystem.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) 302SN/Asystem.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) 312SN/Asystem.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) 322439SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 33146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391717SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 411717SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 431977SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 442623SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 452683Sktlim@umich.edusystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 461717SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 482683Sktlim@umich.edusystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 491917SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 502592SN/Asystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 512683Sktlim@umich.edusystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 522036SN/Asystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 5456SN/Asystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 5556SN/Asystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 5656SN/Asystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57695SN/Asystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 582SN/Asystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 591858SN/Asystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 6056SN/Asystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61146SN/Asystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 622171SN/Asystem.cpu.dtb.walker.walks 0 # Table walker walks requested 632170SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 642170SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65146SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 662462SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67146SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 682SN/Asystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 692SN/Asystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 702449SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 711355SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 722623SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 732683Sktlim@umich.edusystem.cpu.dtb.read_misses 0 # DTB read misses 74224SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 751858SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 762683Sktlim@umich.edusystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 772420SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 782683Sktlim@umich.edusystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 792520SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 802420SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 812SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 822683Sktlim@umich.edusystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 832672Sktlim@umich.edusystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 842683Sktlim@umich.edusystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 852SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 862SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 87334SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 88140SN/Asystem.cpu.dtb.hits 0 # DTB hits 89334SN/Asystem.cpu.dtb.misses 0 # DTB misses 902SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 912SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 922SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 932680Sktlim@umich.edusystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 942SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 952SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 962623SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 972SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 982SN/Asystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 992SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 100180SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1012623SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 102393SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 103393SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 104393SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105393SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106384SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107384SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 108393SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1092623SN/Asystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 110393SN/Asystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 111393SN/Asystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 112393SN/Asystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113393SN/Asystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114384SN/Asystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115189SN/Asystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116189SN/Asystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1172623SN/Asystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1182SN/Asystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119729SN/Asystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 120334SN/Asystem.cpu.itb.walker.walks 0 # Table walker walks requested 1212SN/Asystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1222SN/Asystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1232SN/Asystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1242SN/Asystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1252SN/Asystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1262SN/Asystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1272SN/Asystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1282SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 1292SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 1302SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 1312SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 1322SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 1331001SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 1341001SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 1351001SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1361001SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1371001SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1382SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 1392SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1402SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1412SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1422SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1432SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 1442SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 1452SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 1462SN/Asystem.cpu.itb.hits 0 # DTB hits 1472SN/Asystem.cpu.itb.misses 0 # DTB misses 1482SN/Asystem.cpu.itb.accesses 0 # DTB accesses 1492SN/Asystem.cpu.workload.num_syscalls 191 # Number of system calls 1502SN/Asystem.cpu.numCycles 1034582051 # number of cpu cycles simulated 1512SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1522SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1532SN/Asystem.cpu.committedInsts 272739286 # Number of instructions committed 1542SN/Asystem.cpu.committedOps 327433744 # Number of ops (including micro ops) committed 1552390SN/Asystem.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses 1562390SN/Asystem.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 1572390SN/Asystem.cpu.num_func_calls 12448615 # number of times a function call or return occured 1582390SN/Asystem.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls 1592390SN/Asystem.cpu.num_int_insts 258331537 # number of integer instructions 1602390SN/Asystem.cpu.num_fp_insts 114216705 # number of float instructions 1612390SN/Asystem.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read 1622390SN/Asystem.cpu.num_int_register_writes 162499693 # number of times the integer registers were written 1632390SN/Asystem.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 1642390SN/Asystem.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 1652390SN/Asystem.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read 1662390SN/Asystem.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written 167385SN/Asystem.cpu.num_mem_refs 168107847 # number of memory refs 1682SN/Asystem.cpu.num_load_insts 85732248 # Number of load instructions 1692SN/Asystem.cpu.num_store_insts 82375599 # Number of store instructions 1702SN/Asystem.cpu.num_idle_cycles 0.002000 # Number of idle cycles 1712623SN/Asystem.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles 172334SN/Asystem.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173334SN/Asystem.cpu.idle_fraction 0.000000 # Percentage of idle cycles 1742623SN/Asystem.cpu.Branches 30563503 # Number of branches fetched 175334SN/Asystem.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176334SN/Asystem.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction 177334SN/Asystem.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction 1782623SN/Asystem.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction 1792SN/Asystem.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction 180921SN/Asystem.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction 1812915Sktlim@umich.edusystem.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction 1822915Sktlim@umich.edusystem.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction 1832683Sktlim@umich.edusystem.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction 1842SN/Asystem.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction 1852SN/Asystem.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction 1862SN/Asystem.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction 1872623SN/Asystem.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction 1882SN/Asystem.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction 189921SN/Asystem.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction 1902915Sktlim@umich.edusystem.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction 1912915Sktlim@umich.edusystem.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction 1922SN/Asystem.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction 1932SN/Asystem.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction 1942SN/Asystem.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction 1952SN/Asystem.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction 1962SN/Asystem.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction 1972SN/Asystem.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction 1982SN/Asystem.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction 199595SN/Asystem.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction 2002623SN/Asystem.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction 201595SN/Asystem.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction 2022390SN/Asystem.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 2031080SN/Asystem.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 2041080SN/Asystem.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 2051080SN/Asystem.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction 2061080SN/Asystem.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction 2071080SN/Asystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 2081080SN/Asystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 2091080SN/Asystem.cpu.op_class::total 327812214 # Class of executed instruction 2101121SN/Asystem.cpu.dcache.tags.replacements 1332 # number of replacements 2112107SN/Asystem.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use 2121089SN/Asystem.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. 2131089SN/Asystem.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 2141080SN/Asystem.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. 2151080SN/Asystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2161080SN/Asystem.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor 2171080SN/Asystem.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy 218595SN/Asystem.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy 2192623SN/Asystem.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id 2202683Sktlim@umich.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 221595SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id 2222090SN/Asystem.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 2232683Sktlim@umich.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 2242683Sktlim@umich.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id 225595SN/Asystem.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id 2262205SN/Asystem.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses 2272205SN/Asystem.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses 2282683Sktlim@umich.edusystem.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits 2292683Sktlim@umich.edusystem.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits 230595SN/Asystem.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 231595SN/Asystem.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 2322390SN/Asystem.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits 2332423SN/Asystem.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits 2342390SN/Asystem.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 235595SN/Asystem.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 236595SN/Asystem.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 237595SN/Asystem.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 2382623SN/Asystem.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits 239595SN/Asystem.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits 2402390SN/Asystem.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits 2411080SN/Asystem.cpu.dcache.overall_hits::total 168337827 # number of overall hits 242595SN/Asystem.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses 2431080SN/Asystem.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses 2441080SN/Asystem.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 245595SN/Asystem.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 2462683Sktlim@umich.edusystem.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses 2471080SN/Asystem.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses 2481080SN/Asystem.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses 2491080SN/Asystem.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses 2501121SN/Asystem.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses 2512107SN/Asystem.cpu.dcache.overall_misses::total 4479 # number of overall misses 2521089SN/Asystem.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles 2531080SN/Asystem.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles 2541089SN/Asystem.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles 2551080SN/Asystem.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles 2561080SN/Asystem.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles 2571080SN/Asystem.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles 258595SN/Asystem.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles 2592683Sktlim@umich.edusystem.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles 2601080SN/Asystem.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) 2612090SN/Asystem.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) 2621080SN/Asystem.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 263595SN/Asystem.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 2642683Sktlim@umich.edusystem.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) 2652683Sktlim@umich.edusystem.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) 266595SN/Asystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 2672683Sktlim@umich.edusystem.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 2681098SN/Asystem.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 2691098SN/Asystem.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 2701098SN/Asystem.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses 2712683Sktlim@umich.edusystem.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses 2721098SN/Asystem.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses 2731098SN/Asystem.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses 2741098SN/Asystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses 2752012SN/Asystem.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses 2761098SN/Asystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 2771098SN/Asystem.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 278595SN/Asystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses 2792205SN/Asystem.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses 2802205SN/Asystem.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses 2812205SN/Asystem.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses 282595SN/Asystem.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses 2832390SN/Asystem.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses 2842420SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency 2852423SN/Asystem.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency 2862390SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency 287595SN/Asystem.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency 288595SN/Asystem.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency 2891858SN/Asystem.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency 2902SN/Asystem.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency 2912623SN/Asystem.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency 2922SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2932680Sktlim@umich.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2942SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 2952SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 2962SN/Asystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2971858SN/Asystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2982SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 2992623SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 3002SN/Asystem.cpu.dcache.writebacks::writebacks 998 # number of writebacks 3012SN/Asystem.cpu.dcache.writebacks::total 998 # number of writebacks 3022SN/Asystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 3032683Sktlim@umich.edusystem.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 3042SN/Asystem.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 3052683Sktlim@umich.edusystem.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 3062SN/Asystem.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 3072SN/Asystem.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits 3082SN/Asystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses 3092SN/Asystem.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses 3102SN/Asystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 3112623SN/Asystem.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 3122SN/Asystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 3131858SN/Asystem.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 3142683Sktlim@umich.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses 3152SN/Asystem.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses 3162SN/Asystem.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 3171133SN/Asystem.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 3182SN/Asystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles 3192683Sktlim@umich.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles 3202107SN/Asystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles 3212107SN/Asystem.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles 3222683Sktlim@umich.edusystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles 3232SN/Asystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles 3242107SN/Asystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles 3252SN/Asystem.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles 3262SN/Asystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles 3272SN/Asystem.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles 3282SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 3292SN/Asystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 3302683Sktlim@umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 3312107SN/Asystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 3322107SN/Asystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses 3332SN/Asystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses 3342SN/Asystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 3352SN/Asystem.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 3362SN/Asystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 3372SN/Asystem.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 3382SN/Asystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency 3392SN/Asystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency 3402683Sktlim@umich.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency 3412SN/Asystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency 3422SN/Asystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 3432683Sktlim@umich.edusystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 3442683Sktlim@umich.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency 3452683Sktlim@umich.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency 3462234SN/Asystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency 3472680Sktlim@umich.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency 3482SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 3492SN/Asystem.cpu.icache.tags.replacements 13796 # number of replacements 3502683Sktlim@umich.edusystem.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use 3512SN/Asystem.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. 3522SN/Asystem.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 3532SN/Asystem.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. 3542623SN/Asystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3552SN/Asystem.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor 3562623SN/Asystem.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy 3572623SN/Asystem.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy 3582662Sstever@eecs.umich.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id 3592623SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 3602623SN/Asystem.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 3612741Sksewell@umich.edusystem.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 3622741Sksewell@umich.edusystem.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 3632741Sksewell@umich.edusystem.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id 3642741Sksewell@umich.edusystem.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id 3652683Sktlim@umich.edusystem.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses 3662683Sktlim@umich.edusystem.cpu.icache.tags.data_accesses 697336309 # Number of data accesses 3672741Sksewell@umich.edusystem.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits 3682623SN/Asystem.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits 3692683Sktlim@umich.edusystem.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits 3702683Sktlim@umich.edusystem.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits 3712683Sktlim@umich.edusystem.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits 3722623SN/Asystem.cpu.icache.overall_hits::total 348644750 # number of overall hits 3732683Sktlim@umich.edusystem.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 3742623SN/Asystem.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 3752623SN/Asystem.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 3762623SN/Asystem.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 3772623SN/Asystem.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 3782623SN/Asystem.cpu.icache.overall_misses::total 15603 # number of overall misses 3792623SN/Asystem.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles 3802623SN/Asystem.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles 3812623SN/Asystem.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles 3822SN/Asystem.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles 3832683Sktlim@umich.edusystem.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles 3842427SN/Asystem.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles 3852683Sktlim@umich.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) 3862427SN/Asystem.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) 3872SN/Asystem.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses 3882623SN/Asystem.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses 3892623SN/Asystem.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses 3902623SN/Asystem.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses 3912SN/Asystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 3922683Sktlim@umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 3932SN/Asystem.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 3942623SN/Asystem.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 3952623SN/Asystem.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 3962SN/Asystem.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 3972623SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency 3982623SN/Asystem.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency 3992683Sktlim@umich.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency 4002470SN/Asystem.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency 4012680Sktlim@umich.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency 4022683Sktlim@umich.edusystem.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency 4032623SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4042623SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4052623SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 4062623SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 4072623SN/Asystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4082623SN/Asystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4092683Sktlim@umich.edusystem.cpu.icache.fast_writes 0 # number of fast writes performed 4102623SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 4112623SN/Asystem.cpu.icache.writebacks::writebacks 13796 # number of writebacks 4122623SN/Asystem.cpu.icache.writebacks::total 13796 # number of writebacks 4132623SN/Asystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 4142623SN/Asystem.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 4152623SN/Asystem.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 4162623SN/Asystem.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 4172683Sktlim@umich.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 4182623SN/Asystem.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses 4192683Sktlim@umich.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles 4202683Sktlim@umich.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles 4212683Sktlim@umich.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles 4222623SN/Asystem.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles 4232683Sktlim@umich.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles 4242623SN/Asystem.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles 4252420SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 4262SN/Asystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 4272623SN/Asystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 4282623SN/Asystem.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 4292SN/Asystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 4302SN/Asystem.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 4312623SN/Asystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency 4322623SN/Asystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency 4332623SN/Asystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 4342623SN/Asystem.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency 4352SN/Asystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency 4362683Sktlim@umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency 4372644Sstever@eecs.umich.edusystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4382644Sstever@eecs.umich.edusystem.cpu.l2cache.tags.replacements 0 # number of replacements 4392644Sstever@eecs.umich.edusystem.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use 4402644Sstever@eecs.umich.edusystem.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. 4412623SN/Asystem.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 4422SN/Asystem.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. 4432SN/Asystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4442623SN/Asystem.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor 4452623SN/Asystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor 4462623SN/Asystem.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor 4472090SN/Asystem.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy 4482680Sktlim@umich.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy 4492SN/Asystem.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy 4502SN/Asystem.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy 4512SN/Asystem.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id 4522683Sktlim@umich.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 4532623SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 4542683Sktlim@umich.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 4552251SN/Asystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id 4562683Sktlim@umich.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id 4572683Sktlim@umich.edusystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id 4582251SN/Asystem.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses 4592251SN/Asystem.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses 4602SN/Asystem.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits 4612SN/Asystem.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits 4621858SN/Asystem.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits 4632SN/Asystem.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits 4642SN/Asystem.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 4652683Sktlim@umich.edusystem.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 4662680Sktlim@umich.edusystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits 4672683Sktlim@umich.edusystem.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits 4682SN/Asystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits 4692SN/Asystem.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits 4702SN/Asystem.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits 471system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits 472system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits 473system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits 474system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits 475system.cpu.l2cache.overall_hits::total 13249 # number of overall hits 476system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 477system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 478system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses 479system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses 480system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses 481system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses 482system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses 483system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses 484system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 485system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses 486system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses 487system.cpu.l2cache.overall_misses::total 6832 # number of overall misses 488system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles 489system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles 490system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles 491system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles 492system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles 493system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles 494system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles 495system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles 496system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles 497system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles 498system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles 499system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles 500system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) 501system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) 502system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) 503system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses) 504system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 505system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 506system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) 507system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) 508system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) 509system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) 510system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses 511system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses 512system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses 513system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses 514system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses 515system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses 516system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 517system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 518system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses 519system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses 520system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses 521system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses 522system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses 523system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses 524system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 525system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses 526system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses 527system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses 528system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency 529system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency 530system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency 531system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency 532system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency 533system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency 534system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency 535system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency 536system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency 537system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency 538system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency 539system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency 540system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 541system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 542system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 543system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 544system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 545system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 546system.cpu.l2cache.fast_writes 0 # number of fast writes performed 547system.cpu.l2cache.cache_copies 0 # number of cache copies performed 548system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 549system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 550system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses 551system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses 552system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses 553system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses 554system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses 555system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses 556system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 557system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses 558system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses 559system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses 560system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles 561system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles 562system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles 563system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles 564system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles 565system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles 566system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles 567system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles 568system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles 569system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles 570system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles 571system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles 572system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 573system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 574system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses 575system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses 576system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses 577system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses 578system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses 579system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses 580system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 581system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses 582system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses 583system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses 584system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency 585system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency 586system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency 587system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency 588system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency 589system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 591system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 592system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency 594system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency 595system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency 596system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 597system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. 598system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. 599system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 600system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 601system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 602system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 603system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::WritebackClean 6212 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::CleanEvict 253 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution 611system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37418 # Packet count per connected master and slave (bytes) 612system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10207 # Packet count per connected master and slave (bytes) 613system.cpu.toL2Bus.pkt_count::total 47625 # Packet count per connected master and slave (bytes) 614system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1396160 # Cumulative packet size per connected master and slave (bytes) 615system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) 616system.cpu.toL2Bus.pkt_size::total 1746624 # Cumulative packet size per connected master and slave (bytes) 617system.cpu.toL2Bus.snoops 0 # Total snoops (count) 618system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram 619system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram 620system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram 621system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 622system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram 623system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram 624system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 625system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 626system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 628system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram 629system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) 630system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 631system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 632system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 633system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 634system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 635system.membus.trans_dist::ReadResp 3976 # Transaction distribution 636system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 637system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 638system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution 639system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) 640system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) 641system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) 642system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) 643system.membus.snoops 0 # Total snoops (count) 644system.membus.snoop_fanout::samples 6833 # Request fanout histogram 645system.membus.snoop_fanout::mean 0 # Request fanout histogram 646system.membus.snoop_fanout::stdev 0 # Request fanout histogram 647system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 648system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram 649system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 650system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 651system.membus.snoop_fanout::min_value 0 # Request fanout histogram 652system.membus.snoop_fanout::max_value 0 # Request fanout histogram 653system.membus.snoop_fanout::total 6833 # Request fanout histogram 654system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks) 655system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 656system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks) 657system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 658 659---------- End Simulation Statistics ---------- 660