stats.txt revision 9055:38f1926fb599
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.212344 # Number of seconds simulated 4sim_ticks 212344048000 # Number of ticks simulated 5final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1586428 # Simulator instruction rate (inst/s) 8host_op_rate 2028172 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1233780581 # Simulator tick rate (ticks/s) 10host_mem_usage 229108 # Number of bytes of host memory used 11host_seconds 172.11 # Real time elapsed on the host 12sim_insts 273037671 # Number of instructions simulated 13sim_ops 349065408 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 1394641440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 480709269 # Number of bytes read from this memory 16system.physmem.bytes_read::total 1875350709 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 1394641440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 1394641440 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory 20system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 348660360 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 94582506 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 443242866 # Number of read requests responded to by this memory 24system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 6567838624 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 2263822667 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 8831661291 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 6567838624 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 6567838624 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::cpu.data 1883960425 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 1883960425 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 6567838624 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 4147783092 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 10715621716 # Total bandwidth to/from this memory (bytes/s) 36system.cpu.dtb.inst_hits 0 # ITB inst hits 37system.cpu.dtb.inst_misses 0 # ITB inst misses 38system.cpu.dtb.read_hits 0 # DTB read hits 39system.cpu.dtb.read_misses 0 # DTB read misses 40system.cpu.dtb.write_hits 0 # DTB write hits 41system.cpu.dtb.write_misses 0 # DTB write misses 42system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 43system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 44system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 45system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 46system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 47system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 48system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 49system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 50system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 51system.cpu.dtb.read_accesses 0 # DTB read accesses 52system.cpu.dtb.write_accesses 0 # DTB write accesses 53system.cpu.dtb.inst_accesses 0 # ITB inst accesses 54system.cpu.dtb.hits 0 # DTB hits 55system.cpu.dtb.misses 0 # DTB misses 56system.cpu.dtb.accesses 0 # DTB accesses 57system.cpu.itb.inst_hits 0 # ITB inst hits 58system.cpu.itb.inst_misses 0 # ITB inst misses 59system.cpu.itb.read_hits 0 # DTB read hits 60system.cpu.itb.read_misses 0 # DTB read misses 61system.cpu.itb.write_hits 0 # DTB write hits 62system.cpu.itb.write_misses 0 # DTB write misses 63system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 64system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 65system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 66system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 67system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 68system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 69system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 70system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 71system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 72system.cpu.itb.read_accesses 0 # DTB read accesses 73system.cpu.itb.write_accesses 0 # DTB write accesses 74system.cpu.itb.inst_accesses 0 # ITB inst accesses 75system.cpu.itb.hits 0 # DTB hits 76system.cpu.itb.misses 0 # DTB misses 77system.cpu.itb.accesses 0 # DTB accesses 78system.cpu.workload.num_syscalls 191 # Number of system calls 79system.cpu.numCycles 424688097 # number of cpu cycles simulated 80system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 81system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 82system.cpu.committedInsts 273037671 # Number of instructions committed 83system.cpu.committedOps 349065408 # Number of ops (including micro ops) committed 84system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses 85system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 86system.cpu.num_func_calls 12433363 # number of times a function call or return occured 87system.cpu.num_conditional_control_insts 18087062 # number of instructions that are conditional controls 88system.cpu.num_int_insts 279584926 # number of integer instructions 89system.cpu.num_fp_insts 114216705 # number of float instructions 90system.cpu.num_int_register_reads 1887652191 # number of times the integer registers were read 91system.cpu.num_int_register_writes 251197918 # number of times the integer registers were written 92system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 93system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 94system.cpu.num_mem_refs 177024357 # number of memory refs 95system.cpu.num_load_insts 94648758 # Number of load instructions 96system.cpu.num_store_insts 82375599 # Number of store instructions 97system.cpu.num_idle_cycles 0 # Number of idle cycles 98system.cpu.num_busy_cycles 424688097 # Number of busy cycles 99system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 100system.cpu.idle_fraction 0 # Percentage of idle cycles 101 102---------- End Simulation Statistics ---------- 103