stats.txt revision 10488:7c27480a5031
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.201717 # Number of seconds simulated 4sim_ticks 201717313500 # Number of ticks simulated 5final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1306299 # Simulator instruction rate (inst/s) 8host_op_rate 1568357 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 965080142 # Simulator tick rate (ticks/s) 10host_mem_usage 305108 # Number of bytes of host memory used 11host_seconds 209.02 # Real time elapsed on the host 12sim_insts 273037594 # Number of instructions simulated 13sim_ops 327811949 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 1394641092 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory 18system.physmem.bytes_read::total 1875350308 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 1394641092 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 1394641092 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory 22system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 348660273 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 434960784 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 6913839312 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 2383083572 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 9296922884 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6913839312 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6913839312 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1983209850 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1983209850 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s) 38system.membus.trans_dist::ReadReq 434895827 # Transaction distribution 39system.membus.trans_dist::ReadResp 434906722 # Transaction distribution 40system.membus.trans_dist::WriteReq 82052672 # Transaction distribution 41system.membus.trans_dist::WriteResp 82052672 # Transaction distribution 42system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution 43system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution 44system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution 45system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution 46system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution 47system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320546 # Packet count per connected master and slave (bytes) 48system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes) 49system.membus.pkt_count::total 1034048702 # Packet count per connected master and slave (bytes) 50system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641092 # Cumulative packet size per connected master and slave (bytes) 51system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes) 52system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) 53system.membus.snoops 0 # Total snoops (count) 54system.membus.snoop_fanout::samples 517024351 # Request fanout histogram 55system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram 56system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram 57system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 58system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 59system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 60system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 61system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 62system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram 63system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram 64system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 65system.membus.snoop_fanout::min_value 4 # Request fanout histogram 66system.membus.snoop_fanout::max_value 5 # Request fanout histogram 67system.membus.snoop_fanout::total 517024351 # Request fanout histogram 68system.cpu_clk_domain.clock 500 # Clock period in ticks 69system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 70system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 71system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 72system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 73system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 74system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 75system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 76system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 77system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 78system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 79system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 80system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 81system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 82system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 83system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 84system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 85system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 86system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 87system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 88system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 89system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 90system.cpu.dtb.inst_hits 0 # ITB inst hits 91system.cpu.dtb.inst_misses 0 # ITB inst misses 92system.cpu.dtb.read_hits 0 # DTB read hits 93system.cpu.dtb.read_misses 0 # DTB read misses 94system.cpu.dtb.write_hits 0 # DTB write hits 95system.cpu.dtb.write_misses 0 # DTB write misses 96system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 97system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 98system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 99system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 100system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 101system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 102system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 103system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 104system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 105system.cpu.dtb.read_accesses 0 # DTB read accesses 106system.cpu.dtb.write_accesses 0 # DTB write accesses 107system.cpu.dtb.inst_accesses 0 # ITB inst accesses 108system.cpu.dtb.hits 0 # DTB hits 109system.cpu.dtb.misses 0 # DTB misses 110system.cpu.dtb.accesses 0 # DTB accesses 111system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 112system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 113system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 114system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 115system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 116system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 132system.cpu.itb.inst_hits 0 # ITB inst hits 133system.cpu.itb.inst_misses 0 # ITB inst misses 134system.cpu.itb.read_hits 0 # DTB read hits 135system.cpu.itb.read_misses 0 # DTB read misses 136system.cpu.itb.write_hits 0 # DTB write hits 137system.cpu.itb.write_misses 0 # DTB write misses 138system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 139system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 140system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 141system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 142system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 143system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 144system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 145system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 146system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 147system.cpu.itb.read_accesses 0 # DTB read accesses 148system.cpu.itb.write_accesses 0 # DTB write accesses 149system.cpu.itb.inst_accesses 0 # ITB inst accesses 150system.cpu.itb.hits 0 # DTB hits 151system.cpu.itb.misses 0 # DTB misses 152system.cpu.itb.accesses 0 # DTB accesses 153system.cpu.workload.num_syscalls 191 # Number of system calls 154system.cpu.numCycles 403434628 # number of cpu cycles simulated 155system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 156system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 157system.cpu.committedInsts 273037594 # Number of instructions committed 158system.cpu.committedOps 327811949 # Number of ops (including micro ops) committed 159system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses 160system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 161system.cpu.num_func_calls 12448615 # number of times a function call or return occured 162system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls 163system.cpu.num_int_insts 258331481 # number of integer instructions 164system.cpu.num_fp_insts 114216705 # number of float instructions 165system.cpu.num_int_register_reads 1174407516 # number of times the integer registers were read 166system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written 167system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 168system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 169system.cpu.num_cc_register_reads 985884623 # number of times the CC registers were read 170system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written 171system.cpu.num_mem_refs 168107829 # number of memory refs 172system.cpu.num_load_insts 85732235 # Number of load instructions 173system.cpu.num_store_insts 82375594 # Number of store instructions 174system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 175system.cpu.num_busy_cycles 403434627.998000 # Number of busy cycles 176system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 177system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 178system.cpu.Branches 30563490 # Number of branches fetched 179system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 180system.cpu.op_class::IntAlu 104312492 31.82% 31.82% # Class of executed instruction 181system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction 182system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction 183system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction 184system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction 185system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction 186system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction 187system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction 188system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction 189system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction 190system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction 191system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction 192system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction 193system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction 194system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction 195system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction 196system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction 197system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction 198system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction 199system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction 200system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction 201system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction 202system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction 203system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction 204system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction 205system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction 206system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction 207system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction 208system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction 209system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction 210system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction 211system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 212system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 213system.cpu.op_class::total 327812144 # Class of executed instruction 214 215---------- End Simulation Statistics ---------- 216