stats.txt revision 9079:9a244ebdc3c9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.071244 # Number of seconds simulated 4sim_ticks 71244143500 # Number of ticks simulated 5final_tick 71244143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 187993 # Simulator instruction rate (inst/s) 8host_op_rate 240337 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49051248 # Simulator tick rate (ticks/s) 10host_mem_usage 243200 # Number of bytes of host memory used 11host_seconds 1452.44 # Real time elapsed on the host 12sim_insts 273048446 # Number of instructions simulated 13sim_ops 349076170 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 195520 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 273792 # Number of bytes read from this memory 16system.physmem.bytes_read::total 469312 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 195520 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 195520 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3055 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4278 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7333 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2744366 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 3843011 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 6587377 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 2744366 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 2744366 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 2744366 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 3843011 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 6587377 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 41system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 42system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 43system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 44system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45system.cpu.dtb.read_accesses 0 # DTB read accesses 46system.cpu.dtb.write_accesses 0 # DTB write accesses 47system.cpu.dtb.inst_accesses 0 # ITB inst accesses 48system.cpu.dtb.hits 0 # DTB hits 49system.cpu.dtb.misses 0 # DTB misses 50system.cpu.dtb.accesses 0 # DTB accesses 51system.cpu.itb.inst_hits 0 # ITB inst hits 52system.cpu.itb.inst_misses 0 # ITB inst misses 53system.cpu.itb.read_hits 0 # DTB read hits 54system.cpu.itb.read_misses 0 # DTB read misses 55system.cpu.itb.write_hits 0 # DTB write hits 56system.cpu.itb.write_misses 0 # DTB write misses 57system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 191 # Number of system calls 73system.cpu.numCycles 142488288 # number of cpu cycles simulated 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.BPredUnit.lookups 36834655 # Number of BP lookups 77system.cpu.BPredUnit.condPredicted 22011992 # Number of conditional branches predicted 78system.cpu.BPredUnit.condIncorrect 2128141 # Number of conditional branches incorrect 79system.cpu.BPredUnit.BTBLookups 21111775 # Number of BTB lookups 80system.cpu.BPredUnit.BTBHits 17921807 # Number of BTB hits 81system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 82system.cpu.BPredUnit.usedRAS 7049660 # Number of times the RAS was used to get a target. 83system.cpu.BPredUnit.RASInCorrect 9673 # Number of incorrect RAS predictions. 84system.cpu.fetch.icacheStallCycles 41170537 # Number of cycles fetch is stalled on an Icache miss 85system.cpu.fetch.Insts 330092344 # Number of instructions fetch has processed 86system.cpu.fetch.Branches 36834655 # Number of branches that fetch encountered 87system.cpu.fetch.predictedBranches 24971467 # Number of branches that fetch has predicted taken 88system.cpu.fetch.Cycles 74065448 # Number of cycles fetch has run and was not squashing or blocked 89system.cpu.fetch.SquashCycles 8653461 # Number of cycles fetch has spent squashing 90system.cpu.fetch.BlockedCycles 20659218 # Number of cycles fetch has spent blocked 91system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 92system.cpu.fetch.PendingTrapStallCycles 3712 # Number of stall cycles due to pending traps 93system.cpu.fetch.CacheLines 39589827 # Number of cache lines fetched 94system.cpu.fetch.IcacheSquashes 662584 # Number of outstanding Icache misses that were squashed 95system.cpu.fetch.rateDist::samples 142371733 # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::mean 2.982100 # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::stdev 3.456260 # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::0 68999572 48.46% 48.46% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::1 7443838 5.23% 53.69% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::2 5890912 4.14% 57.83% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::3 6290109 4.42% 62.25% # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::4 5018667 3.53% 65.77% # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::5 4222472 2.97% 68.74% # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.rateDist::6 3222890 2.26% 71.00% # Number of instructions fetched each cycle (Total) 106system.cpu.fetch.rateDist::7 4319860 3.03% 74.04% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::8 36963413 25.96% 100.00% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::total 142371733 # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.branchRate 0.258510 # Number of branch fetches per cycle 113system.cpu.fetch.rate 2.316628 # Number of inst fetches per cycle 114system.cpu.decode.IdleCycles 47920905 # Number of cycles decode is idle 115system.cpu.decode.BlockedCycles 15947714 # Number of cycles decode is blocked 116system.cpu.decode.RunCycles 69670851 # Number of cycles decode is running 117system.cpu.decode.UnblockCycles 2428941 # Number of cycles decode is unblocking 118system.cpu.decode.SquashCycles 6403322 # Number of cycles decode is squashing 119system.cpu.decode.BranchResolved 7589257 # Number of times decode resolved a branch 120system.cpu.decode.BranchMispred 69989 # Number of times decode detected a branch misprediction 121system.cpu.decode.DecodedInsts 416841547 # Number of instructions handled by decode 122system.cpu.decode.SquashedInsts 209997 # Number of squashed instructions handled by decode 123system.cpu.rename.SquashCycles 6403322 # Number of cycles rename is squashing 124system.cpu.rename.IdleCycles 53735690 # Number of cycles rename is idle 125system.cpu.rename.BlockCycles 1551358 # Number of cycles rename is blocking 126system.cpu.rename.serializeStallCycles 361067 # count of cycles rename stalled for serializing inst 127system.cpu.rename.RunCycles 66219864 # Number of cycles rename is running 128system.cpu.rename.UnblockCycles 14100432 # Number of cycles rename is unblocking 129system.cpu.rename.RenamedInsts 406248964 # Number of instructions processed by rename 130system.cpu.rename.ROBFullEvents 31 # Number of times rename has blocked due to ROB full 131system.cpu.rename.IQFullEvents 1649610 # Number of times rename has blocked due to IQ full 132system.cpu.rename.LSQFullEvents 10115480 # Number of times rename has blocked due to LSQ full 133system.cpu.rename.FullRegisterEvents 773 # Number of times there has been no free registers 134system.cpu.rename.RenamedOperands 445265070 # Number of destination operands rename has renamed 135system.cpu.rename.RenameLookups 2397426033 # Number of register rename lookups that rename has made 136system.cpu.rename.int_rename_lookups 1310073571 # Number of integer rename lookups 137system.cpu.rename.fp_rename_lookups 1087352462 # Number of floating rename lookups 138system.cpu.rename.CommittedMaps 384584954 # Number of HB maps that are committed 139system.cpu.rename.UndoneMaps 60680116 # Number of HB maps that are undone due to squashing 140system.cpu.rename.serializingInsts 19505 # count of serializing insts renamed 141system.cpu.rename.tempSerializingInsts 19502 # count of temporary serializing insts renamed 142system.cpu.rename.skidInsts 35831958 # count of insts added to the skid buffer 143system.cpu.memDep0.insertedLoads 105842469 # Number of loads inserted to the mem dependence unit. 144system.cpu.memDep0.insertedStores 93258241 # Number of stores inserted to the mem dependence unit. 145system.cpu.memDep0.conflictingLoads 4666139 # Number of conflicting loads. 146system.cpu.memDep0.conflictingStores 5699487 # Number of conflicting stores. 147system.cpu.iq.iqInstsAdded 393022623 # Number of instructions added to the IQ (excludes non-spec) 148system.cpu.iq.iqNonSpecInstsAdded 30465 # Number of non-speculative instructions added to the IQ 149system.cpu.iq.iqInstsIssued 378573033 # Number of instructions issued 150system.cpu.iq.iqSquashedInstsIssued 1364119 # Number of squashed instructions issued 151system.cpu.iq.iqSquashedInstsExamined 42964941 # Number of squashed instructions iterated over during squash; mainly for profiling 152system.cpu.iq.iqSquashedOperandsExamined 113697743 # Number of squashed operands that are examined and possibly removed from graph 153system.cpu.iq.iqSquashedNonSpecRemoved 5987 # Number of squashed non-spec instructions that were removed 154system.cpu.iq.issued_per_cycle::samples 142371733 # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::mean 2.659046 # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::stdev 2.045030 # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::0 29238426 20.54% 20.54% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::1 20559915 14.44% 34.98% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::2 20888687 14.67% 49.65% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::3 18235605 12.81% 62.46% # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::4 24142271 16.96% 79.42% # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::5 16046767 11.27% 90.69% # Number of insts issued each cycle 164system.cpu.iq.issued_per_cycle::6 9027765 6.34% 97.03% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::7 3298956 2.32% 99.34% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::8 933341 0.66% 100.00% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::total 142371733 # Number of insts issued each cycle 171system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 172system.cpu.iq.fu_full::IntAlu 9050 0.05% 0.05% # attempts to use FU when none available 173system.cpu.iq.fu_full::IntMult 4700 0.03% 0.08% # attempts to use FU when none available 174system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available 175system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available 176system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available 177system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available 178system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available 179system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available 180system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatAdd 48305 0.27% 0.35% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdFloatCmp 7771 0.04% 0.39% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdFloatCvt 390 0.00% 0.39% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.39% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdFloatMisc 194430 1.08% 1.47% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatMult 4896 0.03% 1.50% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatMultAcc 241266 1.34% 2.85% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available 201system.cpu.iq.fu_full::MemRead 9438470 52.59% 55.43% # attempts to use FU when none available 202system.cpu.iq.fu_full::MemWrite 7998776 44.57% 100.00% # attempts to use FU when none available 203system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 204system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 205system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 206system.cpu.iq.FU_type_0::IntAlu 128705433 34.00% 34.00% # Type of FU issued 207system.cpu.iq.FU_type_0::IntMult 2178586 0.58% 34.57% # Type of FU issued 208system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.57% # Type of FU issued 209system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.57% # Type of FU issued 210system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.57% # Type of FU issued 211system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.57% # Type of FU issued 212system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.57% # Type of FU issued 213system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.57% # Type of FU issued 214system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.57% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.57% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.57% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.57% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdCmp 5 0.00% 34.57% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.57% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.57% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.57% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.57% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.57% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.57% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.57% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatAdd 6839771 1.81% 36.38% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.38% # Type of FU issued 228system.cpu.iq.FU_type_0::SimdFloatCmp 8697995 2.30% 38.68% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdFloatCvt 3451888 0.91% 39.59% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdFloatDiv 1605167 0.42% 40.01% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdFloatMisc 21254253 5.61% 45.63% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatMult 7183697 1.90% 47.52% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136969 1.89% 49.41% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.46% # Type of FU issued 235system.cpu.iq.FU_type_0::MemRead 102677998 27.12% 76.58% # Type of FU issued 236system.cpu.iq.FU_type_0::MemWrite 88665985 23.42% 100.00% # Type of FU issued 237system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 238system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 239system.cpu.iq.FU_type_0::total 378573033 # Type of FU issued 240system.cpu.iq.rate 2.656871 # Inst issue rate 241system.cpu.iq.fu_busy_cnt 17948057 # FU busy when requested 242system.cpu.iq.fu_busy_rate 0.047410 # FU busy rate (busy events/executed inst) 243system.cpu.iq.int_inst_queue_reads 668230837 # Number of integer instruction queue reads 244system.cpu.iq.int_inst_queue_writes 303627249 # Number of integer instruction queue writes 245system.cpu.iq.int_inst_queue_wakeup_accesses 252741444 # Number of integer instruction queue wakeup accesses 246system.cpu.iq.fp_inst_queue_reads 250599138 # Number of floating instruction queue reads 247system.cpu.iq.fp_inst_queue_writes 132404625 # Number of floating instruction queue writes 248system.cpu.iq.fp_inst_queue_wakeup_accesses 118730959 # Number of floating instruction queue wakeup accesses 249system.cpu.iq.int_alu_accesses 267327381 # Number of integer alu accesses 250system.cpu.iq.fp_alu_accesses 129193709 # Number of floating point alu accesses 251system.cpu.iew.lsq.thread0.forwLoads 10789214 # Number of loads that had data forwarded from stores 252system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 253system.cpu.iew.lsq.thread0.squashedLoads 11191376 # Number of loads squashed 254system.cpu.iew.lsq.thread0.ignoredResponses 112013 # Number of memory responses ignored because the instruction is squashed 255system.cpu.iew.lsq.thread0.memOrderViolation 13979 # Number of memory ordering violations 256system.cpu.iew.lsq.thread0.squashedStores 10880305 # Number of stores squashed 257system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 258system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 259system.cpu.iew.lsq.thread0.rescheduledLoads 7857 # Number of loads that were rescheduled 260system.cpu.iew.lsq.thread0.cacheBlocked 112 # Number of times an access to memory failed due to the cache being blocked 261system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 262system.cpu.iew.iewSquashCycles 6403322 # Number of cycles IEW is squashing 263system.cpu.iew.iewBlockCycles 34047 # Number of cycles IEW is blocking 264system.cpu.iew.iewUnblockCycles 1473 # Number of cycles IEW is unblocking 265system.cpu.iew.iewDispatchedInsts 393102382 # Number of instructions dispatched to IQ 266system.cpu.iew.iewDispSquashedInsts 1223414 # Number of squashed instructions skipped by dispatch 267system.cpu.iew.iewDispLoadInsts 105842469 # Number of dispatched load instructions 268system.cpu.iew.iewDispStoreInsts 93258241 # Number of dispatched store instructions 269system.cpu.iew.iewDispNonSpecInsts 19294 # Number of dispatched non-speculative instructions 270system.cpu.iew.iewIQFullEvents 195 # Number of times the IQ has become full, causing a stall 271system.cpu.iew.iewLSQFullEvents 174 # Number of times the LSQ has become full, causing a stall 272system.cpu.iew.memOrderViolationEvents 13979 # Number of memory order violations 273system.cpu.iew.predictedTakenIncorrect 1692038 # Number of branches that were predicted taken incorrectly 274system.cpu.iew.predictedNotTakenIncorrect 558009 # Number of branches that were predicted not taken incorrectly 275system.cpu.iew.branchMispredicts 2250047 # Number of branch mispredicts detected at execute 276system.cpu.iew.iewExecutedInsts 373788733 # Number of executed instructions 277system.cpu.iew.iewExecLoadInsts 101161202 # Number of load instructions executed 278system.cpu.iew.iewExecSquashedInsts 4784300 # Number of squashed instructions skipped in execute 279system.cpu.iew.exec_swp 0 # number of swp insts executed 280system.cpu.iew.exec_nop 49294 # number of nop insts executed 281system.cpu.iew.exec_refs 188542226 # number of memory reference insts executed 282system.cpu.iew.exec_branches 32415827 # Number of branches executed 283system.cpu.iew.exec_stores 87381024 # Number of stores executed 284system.cpu.iew.exec_rate 2.623294 # Inst execution rate 285system.cpu.iew.wb_sent 372275263 # cumulative count of insts sent to commit 286system.cpu.iew.wb_count 371472403 # cumulative count of insts written-back 287system.cpu.iew.wb_producers 184833323 # num instructions producing a value 288system.cpu.iew.wb_consumers 367854017 # num instructions consuming a value 289system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 290system.cpu.iew.wb_rate 2.607038 # insts written-back per cycle 291system.cpu.iew.wb_fanout 0.502464 # average fanout of values written-back 292system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 293system.cpu.commit.commitCommittedInsts 273049058 # The number of committed instructions 294system.cpu.commit.commitCommittedOps 349076782 # The number of committed instructions 295system.cpu.commit.commitSquashedInsts 44025608 # The number of squashed insts skipped by commit 296system.cpu.commit.commitNonSpecStalls 24478 # The number of times commit has been forced to stall to communicate backwards 297system.cpu.commit.branchMispredicts 2100754 # The number of times a branch was mispredicted 298system.cpu.commit.committed_per_cycle::samples 135968412 # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::mean 2.567337 # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::stdev 2.653672 # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::0 38641813 28.42% 28.42% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::1 29058445 21.37% 49.79% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::2 13534255 9.95% 59.75% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::3 11222379 8.25% 68.00% # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::4 13789944 10.14% 78.14% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::5 7224545 5.31% 83.45% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::6 4032637 2.97% 86.42% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::7 3910785 2.88% 89.30% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::8 14553609 10.70% 100.00% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::total 135968412 # Number of insts commited each cycle 315system.cpu.commit.committedInsts 273049058 # Number of instructions committed 316system.cpu.commit.committedOps 349076782 # Number of ops (including micro ops) committed 317system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 318system.cpu.commit.refs 177029029 # Number of memory references committed 319system.cpu.commit.loads 94651093 # Number of loads committed 320system.cpu.commit.membars 11033 # Number of memory barriers committed 321system.cpu.commit.branches 30523988 # Number of branches committed 322system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 323system.cpu.commit.int_insts 279593987 # Number of committed integer instructions. 324system.cpu.commit.function_calls 6225112 # Number of function calls committed. 325system.cpu.commit.bw_lim_events 14553609 # number cycles where commit BW limit reached 326system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 327system.cpu.rob.rob_reads 514514670 # The number of ROB reads 328system.cpu.rob.rob_writes 792612920 # The number of ROB writes 329system.cpu.timesIdled 2826 # Number of times that the entire CPU went into an idle state and unscheduled itself 330system.cpu.idleCycles 116555 # Total number of cycles that the CPU has spent unscheduled due to idling 331system.cpu.committedInsts 273048446 # Number of Instructions Simulated 332system.cpu.committedOps 349076170 # Number of Ops (including micro ops) Simulated 333system.cpu.committedInsts_total 273048446 # Number of Instructions Simulated 334system.cpu.cpi 0.521843 # CPI: Cycles Per Instruction 335system.cpu.cpi_total 0.521843 # CPI: Total CPI of All Threads 336system.cpu.ipc 1.916287 # IPC: Instructions Per Cycle 337system.cpu.ipc_total 1.916287 # IPC: Total IPC of All Threads 338system.cpu.int_regfile_reads 1784947411 # number of integer regfile reads 339system.cpu.int_regfile_writes 236351279 # number of integer regfile writes 340system.cpu.fp_regfile_reads 189697788 # number of floating regfile reads 341system.cpu.fp_regfile_writes 133433924 # number of floating regfile writes 342system.cpu.misc_regfile_reads 991980863 # number of misc regfile reads 343system.cpu.misc_regfile_writes 34426471 # number of misc regfile writes 344system.cpu.icache.replacements 14091 # number of replacements 345system.cpu.icache.tagsinuse 1855.139503 # Cycle average of tags in use 346system.cpu.icache.total_refs 39573076 # Total number of references to valid blocks. 347system.cpu.icache.sampled_refs 15985 # Sample count of references to valid blocks. 348system.cpu.icache.avg_refs 2475.638161 # Average number of references to valid blocks. 349system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 350system.cpu.icache.occ_blocks::cpu.inst 1855.139503 # Average occupied blocks per requestor 351system.cpu.icache.occ_percent::cpu.inst 0.905830 # Average percentage of cache occupancy 352system.cpu.icache.occ_percent::total 0.905830 # Average percentage of cache occupancy 353system.cpu.icache.ReadReq_hits::cpu.inst 39573076 # number of ReadReq hits 354system.cpu.icache.ReadReq_hits::total 39573076 # number of ReadReq hits 355system.cpu.icache.demand_hits::cpu.inst 39573076 # number of demand (read+write) hits 356system.cpu.icache.demand_hits::total 39573076 # number of demand (read+write) hits 357system.cpu.icache.overall_hits::cpu.inst 39573076 # number of overall hits 358system.cpu.icache.overall_hits::total 39573076 # number of overall hits 359system.cpu.icache.ReadReq_misses::cpu.inst 16751 # number of ReadReq misses 360system.cpu.icache.ReadReq_misses::total 16751 # number of ReadReq misses 361system.cpu.icache.demand_misses::cpu.inst 16751 # number of demand (read+write) misses 362system.cpu.icache.demand_misses::total 16751 # number of demand (read+write) misses 363system.cpu.icache.overall_misses::cpu.inst 16751 # number of overall misses 364system.cpu.icache.overall_misses::total 16751 # number of overall misses 365system.cpu.icache.ReadReq_miss_latency::cpu.inst 205369500 # number of ReadReq miss cycles 366system.cpu.icache.ReadReq_miss_latency::total 205369500 # number of ReadReq miss cycles 367system.cpu.icache.demand_miss_latency::cpu.inst 205369500 # number of demand (read+write) miss cycles 368system.cpu.icache.demand_miss_latency::total 205369500 # number of demand (read+write) miss cycles 369system.cpu.icache.overall_miss_latency::cpu.inst 205369500 # number of overall miss cycles 370system.cpu.icache.overall_miss_latency::total 205369500 # number of overall miss cycles 371system.cpu.icache.ReadReq_accesses::cpu.inst 39589827 # number of ReadReq accesses(hits+misses) 372system.cpu.icache.ReadReq_accesses::total 39589827 # number of ReadReq accesses(hits+misses) 373system.cpu.icache.demand_accesses::cpu.inst 39589827 # number of demand (read+write) accesses 374system.cpu.icache.demand_accesses::total 39589827 # number of demand (read+write) accesses 375system.cpu.icache.overall_accesses::cpu.inst 39589827 # number of overall (read+write) accesses 376system.cpu.icache.overall_accesses::total 39589827 # number of overall (read+write) accesses 377system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000423 # miss rate for ReadReq accesses 378system.cpu.icache.ReadReq_miss_rate::total 0.000423 # miss rate for ReadReq accesses 379system.cpu.icache.demand_miss_rate::cpu.inst 0.000423 # miss rate for demand accesses 380system.cpu.icache.demand_miss_rate::total 0.000423 # miss rate for demand accesses 381system.cpu.icache.overall_miss_rate::cpu.inst 0.000423 # miss rate for overall accesses 382system.cpu.icache.overall_miss_rate::total 0.000423 # miss rate for overall accesses 383system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12260.133723 # average ReadReq miss latency 384system.cpu.icache.ReadReq_avg_miss_latency::total 12260.133723 # average ReadReq miss latency 385system.cpu.icache.demand_avg_miss_latency::cpu.inst 12260.133723 # average overall miss latency 386system.cpu.icache.demand_avg_miss_latency::total 12260.133723 # average overall miss latency 387system.cpu.icache.overall_avg_miss_latency::cpu.inst 12260.133723 # average overall miss latency 388system.cpu.icache.overall_avg_miss_latency::total 12260.133723 # average overall miss latency 389system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.icache.fast_writes 0 # number of fast writes performed 396system.cpu.icache.cache_copies 0 # number of cache copies performed 397system.cpu.icache.ReadReq_mshr_hits::cpu.inst 765 # number of ReadReq MSHR hits 398system.cpu.icache.ReadReq_mshr_hits::total 765 # number of ReadReq MSHR hits 399system.cpu.icache.demand_mshr_hits::cpu.inst 765 # number of demand (read+write) MSHR hits 400system.cpu.icache.demand_mshr_hits::total 765 # number of demand (read+write) MSHR hits 401system.cpu.icache.overall_mshr_hits::cpu.inst 765 # number of overall MSHR hits 402system.cpu.icache.overall_mshr_hits::total 765 # number of overall MSHR hits 403system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15986 # number of ReadReq MSHR misses 404system.cpu.icache.ReadReq_mshr_misses::total 15986 # number of ReadReq MSHR misses 405system.cpu.icache.demand_mshr_misses::cpu.inst 15986 # number of demand (read+write) MSHR misses 406system.cpu.icache.demand_mshr_misses::total 15986 # number of demand (read+write) MSHR misses 407system.cpu.icache.overall_mshr_misses::cpu.inst 15986 # number of overall MSHR misses 408system.cpu.icache.overall_mshr_misses::total 15986 # number of overall MSHR misses 409system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 137471000 # number of ReadReq MSHR miss cycles 410system.cpu.icache.ReadReq_mshr_miss_latency::total 137471000 # number of ReadReq MSHR miss cycles 411system.cpu.icache.demand_mshr_miss_latency::cpu.inst 137471000 # number of demand (read+write) MSHR miss cycles 412system.cpu.icache.demand_mshr_miss_latency::total 137471000 # number of demand (read+write) MSHR miss cycles 413system.cpu.icache.overall_mshr_miss_latency::cpu.inst 137471000 # number of overall MSHR miss cycles 414system.cpu.icache.overall_mshr_miss_latency::total 137471000 # number of overall MSHR miss cycles 415system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for ReadReq accesses 416system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000404 # mshr miss rate for ReadReq accesses 417system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for demand accesses 418system.cpu.icache.demand_mshr_miss_rate::total 0.000404 # mshr miss rate for demand accesses 419system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for overall accesses 420system.cpu.icache.overall_mshr_miss_rate::total 0.000404 # mshr miss rate for overall accesses 421system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8599.462029 # average ReadReq mshr miss latency 422system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8599.462029 # average ReadReq mshr miss latency 423system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8599.462029 # average overall mshr miss latency 424system.cpu.icache.demand_avg_mshr_miss_latency::total 8599.462029 # average overall mshr miss latency 425system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8599.462029 # average overall mshr miss latency 426system.cpu.icache.overall_avg_mshr_miss_latency::total 8599.462029 # average overall mshr miss latency 427system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 428system.cpu.dcache.replacements 1422 # number of replacements 429system.cpu.dcache.tagsinuse 3120.754345 # Cycle average of tags in use 430system.cpu.dcache.total_refs 172231049 # Total number of references to valid blocks. 431system.cpu.dcache.sampled_refs 4634 # Sample count of references to valid blocks. 432system.cpu.dcache.avg_refs 37166.821105 # Average number of references to valid blocks. 433system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 434system.cpu.dcache.occ_blocks::cpu.data 3120.754345 # Average occupied blocks per requestor 435system.cpu.dcache.occ_percent::cpu.data 0.761903 # Average percentage of cache occupancy 436system.cpu.dcache.occ_percent::total 0.761903 # Average percentage of cache occupancy 437system.cpu.dcache.ReadReq_hits::cpu.data 90171406 # number of ReadReq hits 438system.cpu.dcache.ReadReq_hits::total 90171406 # number of ReadReq hits 439system.cpu.dcache.WriteReq_hits::cpu.data 82032842 # number of WriteReq hits 440system.cpu.dcache.WriteReq_hits::total 82032842 # number of WriteReq hits 441system.cpu.dcache.LoadLockedReq_hits::cpu.data 13547 # number of LoadLockedReq hits 442system.cpu.dcache.LoadLockedReq_hits::total 13547 # number of LoadLockedReq hits 443system.cpu.dcache.StoreCondReq_hits::cpu.data 13253 # number of StoreCondReq hits 444system.cpu.dcache.StoreCondReq_hits::total 13253 # number of StoreCondReq hits 445system.cpu.dcache.demand_hits::cpu.data 172204248 # number of demand (read+write) hits 446system.cpu.dcache.demand_hits::total 172204248 # number of demand (read+write) hits 447system.cpu.dcache.overall_hits::cpu.data 172204248 # number of overall hits 448system.cpu.dcache.overall_hits::total 172204248 # number of overall hits 449system.cpu.dcache.ReadReq_misses::cpu.data 3698 # number of ReadReq misses 450system.cpu.dcache.ReadReq_misses::total 3698 # number of ReadReq misses 451system.cpu.dcache.WriteReq_misses::cpu.data 19818 # number of WriteReq misses 452system.cpu.dcache.WriteReq_misses::total 19818 # number of WriteReq misses 453system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 454system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 455system.cpu.dcache.demand_misses::cpu.data 23516 # number of demand (read+write) misses 456system.cpu.dcache.demand_misses::total 23516 # number of demand (read+write) misses 457system.cpu.dcache.overall_misses::cpu.data 23516 # number of overall misses 458system.cpu.dcache.overall_misses::total 23516 # number of overall misses 459system.cpu.dcache.ReadReq_miss_latency::cpu.data 118442000 # number of ReadReq miss cycles 460system.cpu.dcache.ReadReq_miss_latency::total 118442000 # number of ReadReq miss cycles 461system.cpu.dcache.WriteReq_miss_latency::cpu.data 655611500 # number of WriteReq miss cycles 462system.cpu.dcache.WriteReq_miss_latency::total 655611500 # number of WriteReq miss cycles 463system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles 464system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles 465system.cpu.dcache.demand_miss_latency::cpu.data 774053500 # number of demand (read+write) miss cycles 466system.cpu.dcache.demand_miss_latency::total 774053500 # number of demand (read+write) miss cycles 467system.cpu.dcache.overall_miss_latency::cpu.data 774053500 # number of overall miss cycles 468system.cpu.dcache.overall_miss_latency::total 774053500 # number of overall miss cycles 469system.cpu.dcache.ReadReq_accesses::cpu.data 90175104 # number of ReadReq accesses(hits+misses) 470system.cpu.dcache.ReadReq_accesses::total 90175104 # number of ReadReq accesses(hits+misses) 471system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) 472system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) 473system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13549 # number of LoadLockedReq accesses(hits+misses) 474system.cpu.dcache.LoadLockedReq_accesses::total 13549 # number of LoadLockedReq accesses(hits+misses) 475system.cpu.dcache.StoreCondReq_accesses::cpu.data 13253 # number of StoreCondReq accesses(hits+misses) 476system.cpu.dcache.StoreCondReq_accesses::total 13253 # number of StoreCondReq accesses(hits+misses) 477system.cpu.dcache.demand_accesses::cpu.data 172227764 # number of demand (read+write) accesses 478system.cpu.dcache.demand_accesses::total 172227764 # number of demand (read+write) accesses 479system.cpu.dcache.overall_accesses::cpu.data 172227764 # number of overall (read+write) accesses 480system.cpu.dcache.overall_accesses::total 172227764 # number of overall (read+write) accesses 481system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000041 # miss rate for ReadReq accesses 482system.cpu.dcache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses 483system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000242 # miss rate for WriteReq accesses 484system.cpu.dcache.WriteReq_miss_rate::total 0.000242 # miss rate for WriteReq accesses 485system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000148 # miss rate for LoadLockedReq accesses 486system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000148 # miss rate for LoadLockedReq accesses 487system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses 488system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses 489system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses 490system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses 491system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32028.664143 # average ReadReq miss latency 492system.cpu.dcache.ReadReq_avg_miss_latency::total 32028.664143 # average ReadReq miss latency 493system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33081.617721 # average WriteReq miss latency 494system.cpu.dcache.WriteReq_avg_miss_latency::total 33081.617721 # average WriteReq miss latency 495system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency 496system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency 497system.cpu.dcache.demand_avg_miss_latency::cpu.data 32916.035890 # average overall miss latency 498system.cpu.dcache.demand_avg_miss_latency::total 32916.035890 # average overall miss latency 499system.cpu.dcache.overall_avg_miss_latency::cpu.data 32916.035890 # average overall miss latency 500system.cpu.dcache.overall_avg_miss_latency::total 32916.035890 # average overall miss latency 501system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 502system.cpu.dcache.blocked_cycles::no_targets 307000 # number of cycles access was blocked 503system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 504system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked 505system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 506system.cpu.dcache.avg_blocked_cycles::no_targets 27909.090909 # average number of cycles each access was blocked 507system.cpu.dcache.fast_writes 0 # number of fast writes performed 508system.cpu.dcache.cache_copies 0 # number of cache copies performed 509system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks 510system.cpu.dcache.writebacks::total 1041 # number of writebacks 511system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1882 # number of ReadReq MSHR hits 512system.cpu.dcache.ReadReq_mshr_hits::total 1882 # number of ReadReq MSHR hits 513system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16999 # number of WriteReq MSHR hits 514system.cpu.dcache.WriteReq_mshr_hits::total 16999 # number of WriteReq MSHR hits 515system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 516system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 517system.cpu.dcache.demand_mshr_hits::cpu.data 18881 # number of demand (read+write) MSHR hits 518system.cpu.dcache.demand_mshr_hits::total 18881 # number of demand (read+write) MSHR hits 519system.cpu.dcache.overall_mshr_hits::cpu.data 18881 # number of overall MSHR hits 520system.cpu.dcache.overall_mshr_hits::total 18881 # number of overall MSHR hits 521system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1816 # number of ReadReq MSHR misses 522system.cpu.dcache.ReadReq_mshr_misses::total 1816 # number of ReadReq MSHR misses 523system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2819 # number of WriteReq MSHR misses 524system.cpu.dcache.WriteReq_mshr_misses::total 2819 # number of WriteReq MSHR misses 525system.cpu.dcache.demand_mshr_misses::cpu.data 4635 # number of demand (read+write) MSHR misses 526system.cpu.dcache.demand_mshr_misses::total 4635 # number of demand (read+write) MSHR misses 527system.cpu.dcache.overall_mshr_misses::cpu.data 4635 # number of overall MSHR misses 528system.cpu.dcache.overall_mshr_misses::total 4635 # number of overall MSHR misses 529system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 55172500 # number of ReadReq MSHR miss cycles 530system.cpu.dcache.ReadReq_mshr_miss_latency::total 55172500 # number of ReadReq MSHR miss cycles 531system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100155500 # number of WriteReq MSHR miss cycles 532system.cpu.dcache.WriteReq_mshr_miss_latency::total 100155500 # number of WriteReq MSHR miss cycles 533system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155328000 # number of demand (read+write) MSHR miss cycles 534system.cpu.dcache.demand_mshr_miss_latency::total 155328000 # number of demand (read+write) MSHR miss cycles 535system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155328000 # number of overall MSHR miss cycles 536system.cpu.dcache.overall_mshr_miss_latency::total 155328000 # number of overall MSHR miss cycles 537system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses 538system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses 539system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses 540system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses 541system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 542system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 543system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 544system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 545system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30381.332599 # average ReadReq mshr miss latency 546system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30381.332599 # average ReadReq mshr miss latency 547system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35528.733593 # average WriteReq mshr miss latency 548system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35528.733593 # average WriteReq mshr miss latency 549system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33511.974110 # average overall mshr miss latency 550system.cpu.dcache.demand_avg_mshr_miss_latency::total 33511.974110 # average overall mshr miss latency 551system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33511.974110 # average overall mshr miss latency 552system.cpu.dcache.overall_avg_mshr_miss_latency::total 33511.974110 # average overall mshr miss latency 553system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 554system.cpu.l2cache.replacements 0 # number of replacements 555system.cpu.l2cache.tagsinuse 3993.397220 # Cycle average of tags in use 556system.cpu.l2cache.total_refs 13323 # Total number of references to valid blocks. 557system.cpu.l2cache.sampled_refs 5445 # Sample count of references to valid blocks. 558system.cpu.l2cache.avg_refs 2.446832 # Average number of references to valid blocks. 559system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 560system.cpu.l2cache.occ_blocks::writebacks 372.052721 # Average occupied blocks per requestor 561system.cpu.l2cache.occ_blocks::cpu.inst 2804.768410 # Average occupied blocks per requestor 562system.cpu.l2cache.occ_blocks::cpu.data 816.576088 # Average occupied blocks per requestor 563system.cpu.l2cache.occ_percent::writebacks 0.011354 # Average percentage of cache occupancy 564system.cpu.l2cache.occ_percent::cpu.inst 0.085595 # Average percentage of cache occupancy 565system.cpu.l2cache.occ_percent::cpu.data 0.024920 # Average percentage of cache occupancy 566system.cpu.l2cache.occ_percent::total 0.121869 # Average percentage of cache occupancy 567system.cpu.l2cache.ReadReq_hits::cpu.inst 12916 # number of ReadReq hits 568system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits 569system.cpu.l2cache.ReadReq_hits::total 13217 # number of ReadReq hits 570system.cpu.l2cache.Writeback_hits::writebacks 1041 # number of Writeback hits 571system.cpu.l2cache.Writeback_hits::total 1041 # number of Writeback hits 572system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 573system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 574system.cpu.l2cache.ReadExReq_hits::cpu.data 18 # number of ReadExReq hits 575system.cpu.l2cache.ReadExReq_hits::total 18 # number of ReadExReq hits 576system.cpu.l2cache.demand_hits::cpu.inst 12916 # number of demand (read+write) hits 577system.cpu.l2cache.demand_hits::cpu.data 319 # number of demand (read+write) hits 578system.cpu.l2cache.demand_hits::total 13235 # number of demand (read+write) hits 579system.cpu.l2cache.overall_hits::cpu.inst 12916 # number of overall hits 580system.cpu.l2cache.overall_hits::cpu.data 319 # number of overall hits 581system.cpu.l2cache.overall_hits::total 13235 # number of overall hits 582system.cpu.l2cache.ReadReq_misses::cpu.inst 3069 # number of ReadReq misses 583system.cpu.l2cache.ReadReq_misses::cpu.data 1513 # number of ReadReq misses 584system.cpu.l2cache.ReadReq_misses::total 4582 # number of ReadReq misses 585system.cpu.l2cache.ReadExReq_misses::cpu.data 2802 # number of ReadExReq misses 586system.cpu.l2cache.ReadExReq_misses::total 2802 # number of ReadExReq misses 587system.cpu.l2cache.demand_misses::cpu.inst 3069 # number of demand (read+write) misses 588system.cpu.l2cache.demand_misses::cpu.data 4315 # number of demand (read+write) misses 589system.cpu.l2cache.demand_misses::total 7384 # number of demand (read+write) misses 590system.cpu.l2cache.overall_misses::cpu.inst 3069 # number of overall misses 591system.cpu.l2cache.overall_misses::cpu.data 4315 # number of overall misses 592system.cpu.l2cache.overall_misses::total 7384 # number of overall misses 593system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 105043500 # number of ReadReq miss cycles 594system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51988500 # number of ReadReq miss cycles 595system.cpu.l2cache.ReadReq_miss_latency::total 157032000 # number of ReadReq miss cycles 596system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 96644500 # number of ReadExReq miss cycles 597system.cpu.l2cache.ReadExReq_miss_latency::total 96644500 # number of ReadExReq miss cycles 598system.cpu.l2cache.demand_miss_latency::cpu.inst 105043500 # number of demand (read+write) miss cycles 599system.cpu.l2cache.demand_miss_latency::cpu.data 148633000 # number of demand (read+write) miss cycles 600system.cpu.l2cache.demand_miss_latency::total 253676500 # number of demand (read+write) miss cycles 601system.cpu.l2cache.overall_miss_latency::cpu.inst 105043500 # number of overall miss cycles 602system.cpu.l2cache.overall_miss_latency::cpu.data 148633000 # number of overall miss cycles 603system.cpu.l2cache.overall_miss_latency::total 253676500 # number of overall miss cycles 604system.cpu.l2cache.ReadReq_accesses::cpu.inst 15985 # number of ReadReq accesses(hits+misses) 605system.cpu.l2cache.ReadReq_accesses::cpu.data 1814 # number of ReadReq accesses(hits+misses) 606system.cpu.l2cache.ReadReq_accesses::total 17799 # number of ReadReq accesses(hits+misses) 607system.cpu.l2cache.Writeback_accesses::writebacks 1041 # number of Writeback accesses(hits+misses) 608system.cpu.l2cache.Writeback_accesses::total 1041 # number of Writeback accesses(hits+misses) 609system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) 610system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) 611system.cpu.l2cache.ReadExReq_accesses::cpu.data 2820 # number of ReadExReq accesses(hits+misses) 612system.cpu.l2cache.ReadExReq_accesses::total 2820 # number of ReadExReq accesses(hits+misses) 613system.cpu.l2cache.demand_accesses::cpu.inst 15985 # number of demand (read+write) accesses 614system.cpu.l2cache.demand_accesses::cpu.data 4634 # number of demand (read+write) accesses 615system.cpu.l2cache.demand_accesses::total 20619 # number of demand (read+write) accesses 616system.cpu.l2cache.overall_accesses::cpu.inst 15985 # number of overall (read+write) accesses 617system.cpu.l2cache.overall_accesses::cpu.data 4634 # number of overall (read+write) accesses 618system.cpu.l2cache.overall_accesses::total 20619 # number of overall (read+write) accesses 619system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.191992 # miss rate for ReadReq accesses 620system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834068 # miss rate for ReadReq accesses 621system.cpu.l2cache.ReadReq_miss_rate::total 0.257430 # miss rate for ReadReq accesses 622system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993617 # miss rate for ReadExReq accesses 623system.cpu.l2cache.ReadExReq_miss_rate::total 0.993617 # miss rate for ReadExReq accesses 624system.cpu.l2cache.demand_miss_rate::cpu.inst 0.191992 # miss rate for demand accesses 625system.cpu.l2cache.demand_miss_rate::cpu.data 0.931161 # miss rate for demand accesses 626system.cpu.l2cache.demand_miss_rate::total 0.358116 # miss rate for demand accesses 627system.cpu.l2cache.overall_miss_rate::cpu.inst 0.191992 # miss rate for overall accesses 628system.cpu.l2cache.overall_miss_rate::cpu.data 0.931161 # miss rate for overall accesses 629system.cpu.l2cache.overall_miss_rate::total 0.358116 # miss rate for overall accesses 630system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34227.272727 # average ReadReq miss latency 631system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34361.202908 # average ReadReq miss latency 632system.cpu.l2cache.ReadReq_avg_miss_latency::total 34271.497163 # average ReadReq miss latency 633system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34491.256246 # average ReadExReq miss latency 634system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34491.256246 # average ReadExReq miss latency 635system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34227.272727 # average overall miss latency 636system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34445.654693 # average overall miss latency 637system.cpu.l2cache.demand_avg_miss_latency::total 34354.888949 # average overall miss latency 638system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34227.272727 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34445.654693 # average overall miss latency 640system.cpu.l2cache.overall_avg_miss_latency::total 34354.888949 # average overall miss latency 641system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 642system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 643system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 644system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 645system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 646system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 647system.cpu.l2cache.fast_writes 0 # number of fast writes performed 648system.cpu.l2cache.cache_copies 0 # number of cache copies performed 649system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits 650system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 37 # number of ReadReq MSHR hits 651system.cpu.l2cache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits 652system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits 653system.cpu.l2cache.demand_mshr_hits::cpu.data 37 # number of demand (read+write) MSHR hits 654system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits 655system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits 656system.cpu.l2cache.overall_mshr_hits::cpu.data 37 # number of overall MSHR hits 657system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits 658system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3055 # number of ReadReq MSHR misses 659system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1476 # number of ReadReq MSHR misses 660system.cpu.l2cache.ReadReq_mshr_misses::total 4531 # number of ReadReq MSHR misses 661system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2802 # number of ReadExReq MSHR misses 662system.cpu.l2cache.ReadExReq_mshr_misses::total 2802 # number of ReadExReq MSHR misses 663system.cpu.l2cache.demand_mshr_misses::cpu.inst 3055 # number of demand (read+write) MSHR misses 664system.cpu.l2cache.demand_mshr_misses::cpu.data 4278 # number of demand (read+write) MSHR misses 665system.cpu.l2cache.demand_mshr_misses::total 7333 # number of demand (read+write) MSHR misses 666system.cpu.l2cache.overall_mshr_misses::cpu.inst 3055 # number of overall MSHR misses 667system.cpu.l2cache.overall_mshr_misses::cpu.data 4278 # number of overall MSHR misses 668system.cpu.l2cache.overall_mshr_misses::total 7333 # number of overall MSHR misses 669system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 94947500 # number of ReadReq MSHR miss cycles 670system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 46180500 # number of ReadReq MSHR miss cycles 671system.cpu.l2cache.ReadReq_mshr_miss_latency::total 141128000 # number of ReadReq MSHR miss cycles 672system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87716500 # number of ReadExReq MSHR miss cycles 673system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87716500 # number of ReadExReq MSHR miss cycles 674system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 94947500 # number of demand (read+write) MSHR miss cycles 675system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133897000 # number of demand (read+write) MSHR miss cycles 676system.cpu.l2cache.demand_mshr_miss_latency::total 228844500 # number of demand (read+write) MSHR miss cycles 677system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94947500 # number of overall MSHR miss cycles 678system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133897000 # number of overall MSHR miss cycles 679system.cpu.l2cache.overall_mshr_miss_latency::total 228844500 # number of overall MSHR miss cycles 680system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for ReadReq accesses 681system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813671 # mshr miss rate for ReadReq accesses 682system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254565 # mshr miss rate for ReadReq accesses 683system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993617 # mshr miss rate for ReadExReq accesses 684system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993617 # mshr miss rate for ReadExReq accesses 685system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for demand accesses 686system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for demand accesses 687system.cpu.l2cache.demand_mshr_miss_rate::total 0.355643 # mshr miss rate for demand accesses 688system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191117 # mshr miss rate for overall accesses 689system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923177 # mshr miss rate for overall accesses 690system.cpu.l2cache.overall_mshr_miss_rate::total 0.355643 # mshr miss rate for overall accesses 691system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31079.378069 # average ReadReq mshr miss latency 692system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31287.601626 # average ReadReq mshr miss latency 693system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.208122 # average ReadReq mshr miss latency 694system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31304.960742 # average ReadExReq mshr miss latency 695system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31304.960742 # average ReadExReq mshr miss latency 696system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31079.378069 # average overall mshr miss latency 697system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.971482 # average overall mshr miss latency 698system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31207.486704 # average overall mshr miss latency 699system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31079.378069 # average overall mshr miss latency 700system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.971482 # average overall mshr miss latency 701system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31207.486704 # average overall mshr miss latency 702system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 703 704---------- End Simulation Statistics ---------- 705