stats.txt revision 8911:4da2ea94319f
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.071775 # Number of seconds simulated 4sim_ticks 71774859500 # Number of ticks simulated 5final_tick 71774859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 200202 # Simulator instruction rate (inst/s) 8host_op_rate 255946 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52626024 # Simulator tick rate (ticks/s) 10host_mem_usage 233120 # Number of bytes of host memory used 11host_seconds 1363.87 # Real time elapsed on the host 12sim_insts 273048474 # Number of instructions simulated 13sim_ops 349076199 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 472896 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 199168 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 7389 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 6588602 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 2774899 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 6588602 # Total bandwidth to/from this memory (bytes/s) 23system.cpu.dtb.inst_hits 0 # ITB inst hits 24system.cpu.dtb.inst_misses 0 # ITB inst misses 25system.cpu.dtb.read_hits 0 # DTB read hits 26system.cpu.dtb.read_misses 0 # DTB read misses 27system.cpu.dtb.write_hits 0 # DTB write hits 28system.cpu.dtb.write_misses 0 # DTB write misses 29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 34system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 35system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 36system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 37system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38system.cpu.dtb.read_accesses 0 # DTB read accesses 39system.cpu.dtb.write_accesses 0 # DTB write accesses 40system.cpu.dtb.inst_accesses 0 # ITB inst accesses 41system.cpu.dtb.hits 0 # DTB hits 42system.cpu.dtb.misses 0 # DTB misses 43system.cpu.dtb.accesses 0 # DTB accesses 44system.cpu.itb.inst_hits 0 # ITB inst hits 45system.cpu.itb.inst_misses 0 # ITB inst misses 46system.cpu.itb.read_hits 0 # DTB read hits 47system.cpu.itb.read_misses 0 # DTB read misses 48system.cpu.itb.write_hits 0 # DTB write hits 49system.cpu.itb.write_misses 0 # DTB write misses 50system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 51system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 54system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 55system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 56system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 57system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.itb.read_accesses 0 # DTB read accesses 60system.cpu.itb.write_accesses 0 # DTB write accesses 61system.cpu.itb.inst_accesses 0 # ITB inst accesses 62system.cpu.itb.hits 0 # DTB hits 63system.cpu.itb.misses 0 # DTB misses 64system.cpu.itb.accesses 0 # DTB accesses 65system.cpu.workload.num_syscalls 191 # Number of system calls 66system.cpu.numCycles 143549720 # number of cpu cycles simulated 67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 69system.cpu.BPredUnit.lookups 37175542 # Number of BP lookups 70system.cpu.BPredUnit.condPredicted 22262323 # Number of conditional branches predicted 71system.cpu.BPredUnit.condIncorrect 2214096 # Number of conditional branches incorrect 72system.cpu.BPredUnit.BTBLookups 22505770 # Number of BTB lookups 73system.cpu.BPredUnit.BTBHits 18082192 # Number of BTB hits 74system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 75system.cpu.BPredUnit.usedRAS 7072101 # Number of times the RAS was used to get a target. 76system.cpu.BPredUnit.RASInCorrect 52600 # Number of incorrect RAS predictions. 77system.cpu.fetch.icacheStallCycles 41561697 # Number of cycles fetch is stalled on an Icache miss 78system.cpu.fetch.Insts 332366381 # Number of instructions fetch has processed 79system.cpu.fetch.Branches 37175542 # Number of branches that fetch encountered 80system.cpu.fetch.predictedBranches 25154293 # Number of branches that fetch has predicted taken 81system.cpu.fetch.Cycles 74569841 # Number of cycles fetch has run and was not squashing or blocked 82system.cpu.fetch.SquashCycles 8920940 # Number of cycles fetch has spent squashing 83system.cpu.fetch.BlockedCycles 20643175 # Number of cycles fetch has spent blocked 84system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 85system.cpu.fetch.PendingTrapStallCycles 4492 # Number of stall cycles due to pending traps 86system.cpu.fetch.CacheLines 39951299 # Number of cache lines fetched 87system.cpu.fetch.IcacheSquashes 710527 # Number of outstanding Icache misses that were squashed 88system.cpu.fetch.rateDist::samples 143433675 # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::mean 2.978110 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::stdev 3.454958 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::0 69560380 48.50% 48.50% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::1 7529870 5.25% 53.75% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::2 5927266 4.13% 57.88% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::3 6353418 4.43% 62.31% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::4 5053258 3.52% 65.83% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::5 4245115 2.96% 68.79% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::6 3249040 2.27% 71.06% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::7 4338891 3.03% 74.08% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::8 37176437 25.92% 100.00% # Number of instructions fetched each cycle (Total) 101system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::total 143433675 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.branchRate 0.258973 # Number of branch fetches per cycle 106system.cpu.fetch.rate 2.315340 # Number of inst fetches per cycle 107system.cpu.decode.IdleCycles 48398038 # Number of cycles decode is idle 108system.cpu.decode.BlockedCycles 15922899 # Number of cycles decode is blocked 109system.cpu.decode.RunCycles 70106313 # Number of cycles decode is running 110system.cpu.decode.UnblockCycles 2422163 # Number of cycles decode is unblocking 111system.cpu.decode.SquashCycles 6584262 # Number of cycles decode is squashing 112system.cpu.decode.BranchResolved 7647961 # Number of times decode resolved a branch 113system.cpu.decode.BranchMispred 70686 # Number of times decode detected a branch misprediction 114system.cpu.decode.DecodedInsts 419107715 # Number of instructions handled by decode 115system.cpu.decode.SquashedInsts 208401 # Number of squashed instructions handled by decode 116system.cpu.rename.SquashCycles 6584262 # Number of cycles rename is squashing 117system.cpu.rename.IdleCycles 54237445 # Number of cycles rename is idle 118system.cpu.rename.BlockCycles 1551128 # Number of cycles rename is blocking 119system.cpu.rename.serializeStallCycles 362766 # count of cycles rename stalled for serializing inst 120system.cpu.rename.RunCycles 66624532 # Number of cycles rename is running 121system.cpu.rename.UnblockCycles 14073542 # Number of cycles rename is unblocking 122system.cpu.rename.RenamedInsts 408263314 # Number of instructions processed by rename 123system.cpu.rename.ROBFullEvents 21 # Number of times rename has blocked due to ROB full 124system.cpu.rename.IQFullEvents 1648402 # Number of times rename has blocked due to IQ full 125system.cpu.rename.LSQFullEvents 10108765 # Number of times rename has blocked due to LSQ full 126system.cpu.rename.FullRegisterEvents 752 # Number of times there has been no free registers 127system.cpu.rename.RenamedOperands 447190592 # Number of destination operands rename has renamed 128system.cpu.rename.RenameLookups 2407780645 # Number of register rename lookups that rename has made 129system.cpu.rename.int_rename_lookups 1318183800 # Number of integer rename lookups 130system.cpu.rename.fp_rename_lookups 1089596845 # Number of floating rename lookups 131system.cpu.rename.CommittedMaps 384584999 # Number of HB maps that are committed 132system.cpu.rename.UndoneMaps 62605593 # Number of HB maps that are undone due to squashing 133system.cpu.rename.serializingInsts 23936 # count of serializing insts renamed 134system.cpu.rename.tempSerializingInsts 23899 # count of temporary serializing insts renamed 135system.cpu.rename.skidInsts 35817763 # count of insts added to the skid buffer 136system.cpu.memDep0.insertedLoads 106133186 # Number of loads inserted to the mem dependence unit. 137system.cpu.memDep0.insertedStores 93562284 # Number of stores inserted to the mem dependence unit. 138system.cpu.memDep0.conflictingLoads 4587440 # Number of conflicting loads. 139system.cpu.memDep0.conflictingStores 5646194 # Number of conflicting stores. 140system.cpu.iq.iqInstsAdded 394242574 # Number of instructions added to the IQ (excludes non-spec) 141system.cpu.iq.iqNonSpecInstsAdded 33887 # Number of non-speculative instructions added to the IQ 142system.cpu.iq.iqInstsIssued 379407553 # Number of instructions issued 143system.cpu.iq.iqSquashedInstsIssued 1341475 # Number of squashed instructions issued 144system.cpu.iq.iqSquashedInstsExamined 44167400 # Number of squashed instructions iterated over during squash; mainly for profiling 145system.cpu.iq.iqSquashedOperandsExamined 116755410 # Number of squashed operands that are examined and possibly removed from graph 146system.cpu.iq.iqSquashedNonSpecRemoved 9405 # Number of squashed non-spec instructions that were removed 147system.cpu.iq.issued_per_cycle::samples 143433675 # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::mean 2.645178 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::stdev 2.047092 # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::0 29947758 20.88% 20.88% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::1 20633542 14.39% 35.26% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::2 21077069 14.69% 49.96% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::3 18246072 12.72% 62.68% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::4 24216587 16.88% 79.56% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::5 16050569 11.19% 90.75% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::6 9012327 6.28% 97.04% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::7 3309506 2.31% 99.34% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::8 940245 0.66% 100.00% # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 163system.cpu.iq.issued_per_cycle::total 143433675 # Number of insts issued each cycle 164system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 165system.cpu.iq.fu_full::IntAlu 9527 0.05% 0.05% # attempts to use FU when none available 166system.cpu.iq.fu_full::IntMult 4696 0.03% 0.08% # attempts to use FU when none available 167system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available 168system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.08% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatMult 0 0.00% 0.08% # attempts to use FU when none available 172system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.08% # attempts to use FU when none available 173system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.08% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.08% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.08% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.08% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.08% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.08% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.08% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdMult 0 0.00% 0.08% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdFloatAdd 47773 0.27% 0.34% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatCmp 7824 0.04% 0.39% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatCvt 381 0.00% 0.39% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.39% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatMisc 194196 1.08% 1.47% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatMult 4065 0.02% 1.49% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdFloatMultAcc 241389 1.34% 2.83% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available 194system.cpu.iq.fu_full::MemRead 9461548 52.57% 55.40% # attempts to use FU when none available 195system.cpu.iq.fu_full::MemWrite 8027461 44.60% 100.00% # attempts to use FU when none available 196system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 197system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 198system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 199system.cpu.iq.FU_type_0::IntAlu 129140993 34.04% 34.04% # Type of FU issued 200system.cpu.iq.FU_type_0::IntMult 2178888 0.57% 34.61% # Type of FU issued 201system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.61% # Type of FU issued 202system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.61% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.61% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.61% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.61% # Type of FU issued 206system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.61% # Type of FU issued 207system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.61% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.61% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.61% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.61% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.61% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.61% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.61% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.61% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.61% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.61% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.61% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.61% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdFloatAdd 6841737 1.80% 36.42% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.42% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatCmp 8706483 2.29% 38.71% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatCvt 3462240 0.91% 39.62% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatDiv 1609824 0.42% 40.05% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatMisc 21270001 5.61% 45.65% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatMult 7182346 1.89% 47.55% # Type of FU issued 226system.cpu.iq.FU_type_0::SimdFloatMultAcc 7142588 1.88% 49.43% # Type of FU issued 227system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.47% # Type of FU issued 228system.cpu.iq.FU_type_0::MemRead 102963295 27.14% 76.61% # Type of FU issued 229system.cpu.iq.FU_type_0::MemWrite 88733868 23.39% 100.00% # Type of FU issued 230system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 231system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 232system.cpu.iq.FU_type_0::total 379407553 # Type of FU issued 233system.cpu.iq.rate 2.643039 # Inst issue rate 234system.cpu.iq.fu_busy_cnt 17998863 # FU busy when requested 235system.cpu.iq.fu_busy_rate 0.047439 # FU busy rate (busy events/executed inst) 236system.cpu.iq.int_inst_queue_reads 670841771 # Number of integer instruction queue reads 237system.cpu.iq.int_inst_queue_writes 305961612 # Number of integer instruction queue writes 238system.cpu.iq.int_inst_queue_wakeup_accesses 253223434 # Number of integer instruction queue wakeup accesses 239system.cpu.iq.fp_inst_queue_reads 250747348 # Number of floating instruction queue reads 240system.cpu.iq.fp_inst_queue_writes 132496015 # Number of floating instruction queue writes 241system.cpu.iq.fp_inst_queue_wakeup_accesses 118776381 # Number of floating instruction queue wakeup accesses 242system.cpu.iq.int_alu_accesses 268120952 # Number of integer alu accesses 243system.cpu.iq.fp_alu_accesses 129285464 # Number of floating point alu accesses 244system.cpu.iew.lsq.thread0.forwLoads 10792483 # Number of loads that had data forwarded from stores 245system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 246system.cpu.iew.lsq.thread0.squashedLoads 11482088 # Number of loads squashed 247system.cpu.iew.lsq.thread0.ignoredResponses 116027 # Number of memory responses ignored because the instruction is squashed 248system.cpu.iew.lsq.thread0.memOrderViolation 13932 # Number of memory ordering violations 249system.cpu.iew.lsq.thread0.squashedStores 11184344 # Number of stores squashed 250system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 251system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 252system.cpu.iew.lsq.thread0.rescheduledLoads 9709 # Number of loads that were rescheduled 253system.cpu.iew.lsq.thread0.cacheBlocked 181 # Number of times an access to memory failed due to the cache being blocked 254system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 255system.cpu.iew.iewSquashCycles 6584262 # Number of cycles IEW is squashing 256system.cpu.iew.iewBlockCycles 34186 # Number of cycles IEW is blocking 257system.cpu.iew.iewUnblockCycles 1479 # Number of cycles IEW is unblocking 258system.cpu.iew.iewDispatchedInsts 394326849 # Number of instructions dispatched to IQ 259system.cpu.iew.iewDispSquashedInsts 1347232 # Number of squashed instructions skipped by dispatch 260system.cpu.iew.iewDispLoadInsts 106133186 # Number of dispatched load instructions 261system.cpu.iew.iewDispStoreInsts 93562284 # Number of dispatched store instructions 262system.cpu.iew.iewDispNonSpecInsts 22722 # Number of dispatched non-speculative instructions 263system.cpu.iew.iewIQFullEvents 192 # Number of times the IQ has become full, causing a stall 264system.cpu.iew.iewLSQFullEvents 169 # Number of times the LSQ has become full, causing a stall 265system.cpu.iew.memOrderViolationEvents 13932 # Number of memory order violations 266system.cpu.iew.predictedTakenIncorrect 1780753 # Number of branches that were predicted taken incorrectly 267system.cpu.iew.predictedNotTakenIncorrect 562062 # Number of branches that were predicted not taken incorrectly 268system.cpu.iew.branchMispredicts 2342815 # Number of branch mispredicts detected at execute 269system.cpu.iew.iewExecutedInsts 374477920 # Number of executed instructions 270system.cpu.iew.iewExecLoadInsts 101438803 # Number of load instructions executed 271system.cpu.iew.iewExecSquashedInsts 4929633 # Number of squashed instructions skipped in execute 272system.cpu.iew.exec_swp 0 # number of swp insts executed 273system.cpu.iew.exec_nop 50388 # number of nop insts executed 274system.cpu.iew.exec_refs 188856020 # number of memory reference insts executed 275system.cpu.iew.exec_branches 32491949 # Number of branches executed 276system.cpu.iew.exec_stores 87417217 # Number of stores executed 277system.cpu.iew.exec_rate 2.608698 # Inst execution rate 278system.cpu.iew.wb_sent 372876985 # cumulative count of insts sent to commit 279system.cpu.iew.wb_count 371999815 # cumulative count of insts written-back 280system.cpu.iew.wb_producers 185166823 # num instructions producing a value 281system.cpu.iew.wb_consumers 368327153 # num instructions consuming a value 282system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 283system.cpu.iew.wb_rate 2.591435 # insts written-back per cycle 284system.cpu.iew.wb_fanout 0.502724 # average fanout of values written-back 285system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 286system.cpu.commit.commitCommittedInsts 273049086 # The number of committed instructions 287system.cpu.commit.commitCommittedOps 349076811 # The number of committed instructions 288system.cpu.commit.commitSquashedInsts 45250302 # The number of squashed insts skipped by commit 289system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards 290system.cpu.commit.branchMispredicts 2186131 # The number of times a branch was mispredicted 291system.cpu.commit.committed_per_cycle::samples 136849414 # Number of insts commited each cycle 292system.cpu.commit.committed_per_cycle::mean 2.550810 # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::stdev 2.650371 # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::0 39364225 28.76% 28.76% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::1 29162916 21.31% 50.07% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::2 13605145 9.94% 60.02% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::3 11228015 8.20% 68.22% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::4 13810148 10.09% 78.31% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::5 7236976 5.29% 83.60% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::6 4020101 2.94% 86.54% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::7 3901622 2.85% 89.39% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::8 14520266 10.61% 100.00% # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 305system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 306system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::total 136849414 # Number of insts commited each cycle 308system.cpu.commit.committedInsts 273049086 # Number of instructions committed 309system.cpu.commit.committedOps 349076811 # Number of ops (including micro ops) committed 310system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 311system.cpu.commit.refs 177029038 # Number of memory references committed 312system.cpu.commit.loads 94651098 # Number of loads committed 313system.cpu.commit.membars 11033 # Number of memory barriers committed 314system.cpu.commit.branches 30523993 # Number of branches committed 315system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 316system.cpu.commit.int_insts 279594011 # Number of committed integer instructions. 317system.cpu.commit.function_calls 6225112 # Number of function calls committed. 318system.cpu.commit.bw_lim_events 14520266 # number cycles where commit BW limit reached 319system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 320system.cpu.rob.rob_reads 516653738 # The number of ROB reads 321system.cpu.rob.rob_writes 795243409 # The number of ROB writes 322system.cpu.timesIdled 2720 # Number of times that the entire CPU went into an idle state and unscheduled itself 323system.cpu.idleCycles 116045 # Total number of cycles that the CPU has spent unscheduled due to idling 324system.cpu.committedInsts 273048474 # Number of Instructions Simulated 325system.cpu.committedOps 349076199 # Number of Ops (including micro ops) Simulated 326system.cpu.committedInsts_total 273048474 # Number of Instructions Simulated 327system.cpu.cpi 0.525730 # CPI: Cycles Per Instruction 328system.cpu.cpi_total 0.525730 # CPI: Total CPI of All Threads 329system.cpu.ipc 1.902118 # IPC: Instructions Per Cycle 330system.cpu.ipc_total 1.902118 # IPC: Total IPC of All Threads 331system.cpu.int_regfile_reads 1788157543 # number of integer regfile reads 332system.cpu.int_regfile_writes 236964047 # number of integer regfile writes 333system.cpu.fp_regfile_reads 189767378 # number of floating regfile reads 334system.cpu.fp_regfile_writes 133494852 # number of floating regfile writes 335system.cpu.misc_regfile_reads 995239791 # number of misc regfile reads 336system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes 337system.cpu.icache.replacements 14190 # number of replacements 338system.cpu.icache.tagsinuse 1864.933817 # Cycle average of tags in use 339system.cpu.icache.total_refs 39934285 # Total number of references to valid blocks. 340system.cpu.icache.sampled_refs 16092 # Sample count of references to valid blocks. 341system.cpu.icache.avg_refs 2481.623478 # Average number of references to valid blocks. 342system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 343system.cpu.icache.occ_blocks::cpu.inst 1864.933817 # Average occupied blocks per requestor 344system.cpu.icache.occ_percent::cpu.inst 0.910612 # Average percentage of cache occupancy 345system.cpu.icache.occ_percent::total 0.910612 # Average percentage of cache occupancy 346system.cpu.icache.ReadReq_hits::cpu.inst 39934285 # number of ReadReq hits 347system.cpu.icache.ReadReq_hits::total 39934285 # number of ReadReq hits 348system.cpu.icache.demand_hits::cpu.inst 39934285 # number of demand (read+write) hits 349system.cpu.icache.demand_hits::total 39934285 # number of demand (read+write) hits 350system.cpu.icache.overall_hits::cpu.inst 39934285 # number of overall hits 351system.cpu.icache.overall_hits::total 39934285 # number of overall hits 352system.cpu.icache.ReadReq_misses::cpu.inst 17014 # number of ReadReq misses 353system.cpu.icache.ReadReq_misses::total 17014 # number of ReadReq misses 354system.cpu.icache.demand_misses::cpu.inst 17014 # number of demand (read+write) misses 355system.cpu.icache.demand_misses::total 17014 # number of demand (read+write) misses 356system.cpu.icache.overall_misses::cpu.inst 17014 # number of overall misses 357system.cpu.icache.overall_misses::total 17014 # number of overall misses 358system.cpu.icache.ReadReq_miss_latency::cpu.inst 211050500 # number of ReadReq miss cycles 359system.cpu.icache.ReadReq_miss_latency::total 211050500 # number of ReadReq miss cycles 360system.cpu.icache.demand_miss_latency::cpu.inst 211050500 # number of demand (read+write) miss cycles 361system.cpu.icache.demand_miss_latency::total 211050500 # number of demand (read+write) miss cycles 362system.cpu.icache.overall_miss_latency::cpu.inst 211050500 # number of overall miss cycles 363system.cpu.icache.overall_miss_latency::total 211050500 # number of overall miss cycles 364system.cpu.icache.ReadReq_accesses::cpu.inst 39951299 # number of ReadReq accesses(hits+misses) 365system.cpu.icache.ReadReq_accesses::total 39951299 # number of ReadReq accesses(hits+misses) 366system.cpu.icache.demand_accesses::cpu.inst 39951299 # number of demand (read+write) accesses 367system.cpu.icache.demand_accesses::total 39951299 # number of demand (read+write) accesses 368system.cpu.icache.overall_accesses::cpu.inst 39951299 # number of overall (read+write) accesses 369system.cpu.icache.overall_accesses::total 39951299 # number of overall (read+write) accesses 370system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000426 # miss rate for ReadReq accesses 371system.cpu.icache.demand_miss_rate::cpu.inst 0.000426 # miss rate for demand accesses 372system.cpu.icache.overall_miss_rate::cpu.inst 0.000426 # miss rate for overall accesses 373system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12404.519807 # average ReadReq miss latency 374system.cpu.icache.demand_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency 375system.cpu.icache.overall_avg_miss_latency::cpu.inst 12404.519807 # average overall miss latency 376system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 380system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 381system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 382system.cpu.icache.fast_writes 0 # number of fast writes performed 383system.cpu.icache.cache_copies 0 # number of cache copies performed 384system.cpu.icache.ReadReq_mshr_hits::cpu.inst 900 # number of ReadReq MSHR hits 385system.cpu.icache.ReadReq_mshr_hits::total 900 # number of ReadReq MSHR hits 386system.cpu.icache.demand_mshr_hits::cpu.inst 900 # number of demand (read+write) MSHR hits 387system.cpu.icache.demand_mshr_hits::total 900 # number of demand (read+write) MSHR hits 388system.cpu.icache.overall_mshr_hits::cpu.inst 900 # number of overall MSHR hits 389system.cpu.icache.overall_mshr_hits::total 900 # number of overall MSHR hits 390system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16114 # number of ReadReq MSHR misses 391system.cpu.icache.ReadReq_mshr_misses::total 16114 # number of ReadReq MSHR misses 392system.cpu.icache.demand_mshr_misses::cpu.inst 16114 # number of demand (read+write) MSHR misses 393system.cpu.icache.demand_mshr_misses::total 16114 # number of demand (read+write) MSHR misses 394system.cpu.icache.overall_mshr_misses::cpu.inst 16114 # number of overall MSHR misses 395system.cpu.icache.overall_mshr_misses::total 16114 # number of overall MSHR misses 396system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 139714000 # number of ReadReq MSHR miss cycles 397system.cpu.icache.ReadReq_mshr_miss_latency::total 139714000 # number of ReadReq MSHR miss cycles 398system.cpu.icache.demand_mshr_miss_latency::cpu.inst 139714000 # number of demand (read+write) MSHR miss cycles 399system.cpu.icache.demand_mshr_miss_latency::total 139714000 # number of demand (read+write) MSHR miss cycles 400system.cpu.icache.overall_mshr_miss_latency::cpu.inst 139714000 # number of overall MSHR miss cycles 401system.cpu.icache.overall_mshr_miss_latency::total 139714000 # number of overall MSHR miss cycles 402system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for ReadReq accesses 403system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for demand accesses 404system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000403 # mshr miss rate for overall accesses 405system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8670.348765 # average ReadReq mshr miss latency 406system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency 407system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8670.348765 # average overall mshr miss latency 408system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 409system.cpu.dcache.replacements 1427 # number of replacements 410system.cpu.dcache.tagsinuse 3127.647604 # Cycle average of tags in use 411system.cpu.dcache.total_refs 172501472 # Total number of references to valid blocks. 412system.cpu.dcache.sampled_refs 4641 # Sample count of references to valid blocks. 413system.cpu.dcache.avg_refs 37169.030812 # Average number of references to valid blocks. 414system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 415system.cpu.dcache.occ_blocks::cpu.data 3127.647604 # Average occupied blocks per requestor 416system.cpu.dcache.occ_percent::cpu.data 0.763586 # Average percentage of cache occupancy 417system.cpu.dcache.occ_percent::total 0.763586 # Average percentage of cache occupancy 418system.cpu.dcache.ReadReq_hits::cpu.data 90441052 # number of ReadReq hits 419system.cpu.dcache.ReadReq_hits::total 90441052 # number of ReadReq hits 420system.cpu.dcache.WriteReq_hits::cpu.data 82033132 # number of WriteReq hits 421system.cpu.dcache.WriteReq_hits::total 82033132 # number of WriteReq hits 422system.cpu.dcache.LoadLockedReq_hits::cpu.data 14008 # number of LoadLockedReq hits 423system.cpu.dcache.LoadLockedReq_hits::total 14008 # number of LoadLockedReq hits 424system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits 425system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits 426system.cpu.dcache.demand_hits::cpu.data 172474184 # number of demand (read+write) hits 427system.cpu.dcache.demand_hits::total 172474184 # number of demand (read+write) hits 428system.cpu.dcache.overall_hits::cpu.data 172474184 # number of overall hits 429system.cpu.dcache.overall_hits::total 172474184 # number of overall hits 430system.cpu.dcache.ReadReq_misses::cpu.data 3598 # number of ReadReq misses 431system.cpu.dcache.ReadReq_misses::total 3598 # number of ReadReq misses 432system.cpu.dcache.WriteReq_misses::cpu.data 19528 # number of WriteReq misses 433system.cpu.dcache.WriteReq_misses::total 19528 # number of WriteReq misses 434system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 435system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 436system.cpu.dcache.demand_misses::cpu.data 23126 # number of demand (read+write) misses 437system.cpu.dcache.demand_misses::total 23126 # number of demand (read+write) misses 438system.cpu.dcache.overall_misses::cpu.data 23126 # number of overall misses 439system.cpu.dcache.overall_misses::total 23126 # number of overall misses 440system.cpu.dcache.ReadReq_miss_latency::cpu.data 115634000 # number of ReadReq miss cycles 441system.cpu.dcache.ReadReq_miss_latency::total 115634000 # number of ReadReq miss cycles 442system.cpu.dcache.WriteReq_miss_latency::cpu.data 650274000 # number of WriteReq miss cycles 443system.cpu.dcache.WriteReq_miss_latency::total 650274000 # number of WriteReq miss cycles 444system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles 445system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles 446system.cpu.dcache.demand_miss_latency::cpu.data 765908000 # number of demand (read+write) miss cycles 447system.cpu.dcache.demand_miss_latency::total 765908000 # number of demand (read+write) miss cycles 448system.cpu.dcache.overall_miss_latency::cpu.data 765908000 # number of overall miss cycles 449system.cpu.dcache.overall_miss_latency::total 765908000 # number of overall miss cycles 450system.cpu.dcache.ReadReq_accesses::cpu.data 90444650 # number of ReadReq accesses(hits+misses) 451system.cpu.dcache.ReadReq_accesses::total 90444650 # number of ReadReq accesses(hits+misses) 452system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) 453system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) 454system.cpu.dcache.LoadLockedReq_accesses::cpu.data 14010 # number of LoadLockedReq accesses(hits+misses) 455system.cpu.dcache.LoadLockedReq_accesses::total 14010 # number of LoadLockedReq accesses(hits+misses) 456system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses) 457system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) 458system.cpu.dcache.demand_accesses::cpu.data 172497310 # number of demand (read+write) accesses 459system.cpu.dcache.demand_accesses::total 172497310 # number of demand (read+write) accesses 460system.cpu.dcache.overall_accesses::cpu.data 172497310 # number of overall (read+write) accesses 461system.cpu.dcache.overall_accesses::total 172497310 # number of overall (read+write) accesses 462system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000040 # miss rate for ReadReq accesses 463system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000238 # miss rate for WriteReq accesses 464system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000143 # miss rate for LoadLockedReq accesses 465system.cpu.dcache.demand_miss_rate::cpu.data 0.000134 # miss rate for demand accesses 466system.cpu.dcache.overall_miss_rate::cpu.data 0.000134 # miss rate for overall accesses 467system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32138.410228 # average ReadReq miss latency 468system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33299.569848 # average WriteReq miss latency 469system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency 470system.cpu.dcache.demand_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency 471system.cpu.dcache.overall_avg_miss_latency::cpu.data 33118.913777 # average overall miss latency 472system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 473system.cpu.dcache.blocked_cycles::no_targets 315000 # number of cycles access was blocked 474system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked 476system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_targets 24230.769231 # average number of cycles each access was blocked 478system.cpu.dcache.fast_writes 0 # number of fast writes performed 479system.cpu.dcache.cache_copies 0 # number of cache copies performed 480system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks 481system.cpu.dcache.writebacks::total 1038 # number of writebacks 482system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1792 # number of ReadReq MSHR hits 483system.cpu.dcache.ReadReq_mshr_hits::total 1792 # number of ReadReq MSHR hits 484system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16671 # number of WriteReq MSHR hits 485system.cpu.dcache.WriteReq_mshr_hits::total 16671 # number of WriteReq MSHR hits 486system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 487system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 488system.cpu.dcache.demand_mshr_hits::cpu.data 18463 # number of demand (read+write) MSHR hits 489system.cpu.dcache.demand_mshr_hits::total 18463 # number of demand (read+write) MSHR hits 490system.cpu.dcache.overall_mshr_hits::cpu.data 18463 # number of overall MSHR hits 491system.cpu.dcache.overall_mshr_hits::total 18463 # number of overall MSHR hits 492system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1806 # number of ReadReq MSHR misses 493system.cpu.dcache.ReadReq_mshr_misses::total 1806 # number of ReadReq MSHR misses 494system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2857 # number of WriteReq MSHR misses 495system.cpu.dcache.WriteReq_mshr_misses::total 2857 # number of WriteReq MSHR misses 496system.cpu.dcache.demand_mshr_misses::cpu.data 4663 # number of demand (read+write) MSHR misses 497system.cpu.dcache.demand_mshr_misses::total 4663 # number of demand (read+write) MSHR misses 498system.cpu.dcache.overall_mshr_misses::cpu.data 4663 # number of overall MSHR misses 499system.cpu.dcache.overall_mshr_misses::total 4663 # number of overall MSHR misses 500system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 54896500 # number of ReadReq MSHR miss cycles 501system.cpu.dcache.ReadReq_mshr_miss_latency::total 54896500 # number of ReadReq MSHR miss cycles 502system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101557000 # number of WriteReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::total 101557000 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.demand_mshr_miss_latency::cpu.data 156453500 # number of demand (read+write) MSHR miss cycles 505system.cpu.dcache.demand_mshr_miss_latency::total 156453500 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.overall_mshr_miss_latency::cpu.data 156453500 # number of overall MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::total 156453500 # number of overall MSHR miss cycles 508system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses 509system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 510system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 511system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 512system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30396.733112 # average ReadReq mshr miss latency 513system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35546.727336 # average WriteReq mshr miss latency 514system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency 515system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33552.112374 # average overall mshr miss latency 516system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 517system.cpu.l2cache.replacements 69 # number of replacements 518system.cpu.l2cache.tagsinuse 4034.301662 # Cycle average of tags in use 519system.cpu.l2cache.total_refs 13357 # Total number of references to valid blocks. 520system.cpu.l2cache.sampled_refs 5499 # Sample count of references to valid blocks. 521system.cpu.l2cache.avg_refs 2.428987 # Average number of references to valid blocks. 522system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 523system.cpu.l2cache.occ_blocks::writebacks 380.580872 # Average occupied blocks per requestor 524system.cpu.l2cache.occ_blocks::cpu.inst 2851.587465 # Average occupied blocks per requestor 525system.cpu.l2cache.occ_blocks::cpu.data 802.133324 # Average occupied blocks per requestor 526system.cpu.l2cache.occ_percent::writebacks 0.011614 # Average percentage of cache occupancy 527system.cpu.l2cache.occ_percent::cpu.inst 0.087024 # Average percentage of cache occupancy 528system.cpu.l2cache.occ_percent::cpu.data 0.024479 # Average percentage of cache occupancy 529system.cpu.l2cache.occ_percent::total 0.123117 # Average percentage of cache occupancy 530system.cpu.l2cache.ReadReq_hits::cpu.inst 12970 # number of ReadReq hits 531system.cpu.l2cache.ReadReq_hits::cpu.data 298 # number of ReadReq hits 532system.cpu.l2cache.ReadReq_hits::total 13268 # number of ReadReq hits 533system.cpu.l2cache.Writeback_hits::writebacks 1038 # number of Writeback hits 534system.cpu.l2cache.Writeback_hits::total 1038 # number of Writeback hits 535system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits 536system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits 537system.cpu.l2cache.demand_hits::cpu.inst 12970 # number of demand (read+write) hits 538system.cpu.l2cache.demand_hits::cpu.data 315 # number of demand (read+write) hits 539system.cpu.l2cache.demand_hits::total 13285 # number of demand (read+write) hits 540system.cpu.l2cache.overall_hits::cpu.inst 12970 # number of overall hits 541system.cpu.l2cache.overall_hits::cpu.data 315 # number of overall hits 542system.cpu.l2cache.overall_hits::total 13285 # number of overall hits 543system.cpu.l2cache.ReadReq_misses::cpu.inst 3122 # number of ReadReq misses 544system.cpu.l2cache.ReadReq_misses::cpu.data 1507 # number of ReadReq misses 545system.cpu.l2cache.ReadReq_misses::total 4629 # number of ReadReq misses 546system.cpu.l2cache.UpgradeReq_misses::cpu.data 22 # number of UpgradeReq misses 547system.cpu.l2cache.UpgradeReq_misses::total 22 # number of UpgradeReq misses 548system.cpu.l2cache.ReadExReq_misses::cpu.data 2819 # number of ReadExReq misses 549system.cpu.l2cache.ReadExReq_misses::total 2819 # number of ReadExReq misses 550system.cpu.l2cache.demand_misses::cpu.inst 3122 # number of demand (read+write) misses 551system.cpu.l2cache.demand_misses::cpu.data 4326 # number of demand (read+write) misses 552system.cpu.l2cache.demand_misses::total 7448 # number of demand (read+write) misses 553system.cpu.l2cache.overall_misses::cpu.inst 3122 # number of overall misses 554system.cpu.l2cache.overall_misses::cpu.data 4326 # number of overall misses 555system.cpu.l2cache.overall_misses::total 7448 # number of overall misses 556system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106982000 # number of ReadReq miss cycles 557system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51758500 # number of ReadReq miss cycles 558system.cpu.l2cache.ReadReq_miss_latency::total 158740500 # number of ReadReq miss cycles 559system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97188000 # number of ReadExReq miss cycles 560system.cpu.l2cache.ReadExReq_miss_latency::total 97188000 # number of ReadExReq miss cycles 561system.cpu.l2cache.demand_miss_latency::cpu.inst 106982000 # number of demand (read+write) miss cycles 562system.cpu.l2cache.demand_miss_latency::cpu.data 148946500 # number of demand (read+write) miss cycles 563system.cpu.l2cache.demand_miss_latency::total 255928500 # number of demand (read+write) miss cycles 564system.cpu.l2cache.overall_miss_latency::cpu.inst 106982000 # number of overall miss cycles 565system.cpu.l2cache.overall_miss_latency::cpu.data 148946500 # number of overall miss cycles 566system.cpu.l2cache.overall_miss_latency::total 255928500 # number of overall miss cycles 567system.cpu.l2cache.ReadReq_accesses::cpu.inst 16092 # number of ReadReq accesses(hits+misses) 568system.cpu.l2cache.ReadReq_accesses::cpu.data 1805 # number of ReadReq accesses(hits+misses) 569system.cpu.l2cache.ReadReq_accesses::total 17897 # number of ReadReq accesses(hits+misses) 570system.cpu.l2cache.Writeback_accesses::writebacks 1038 # number of Writeback accesses(hits+misses) 571system.cpu.l2cache.Writeback_accesses::total 1038 # number of Writeback accesses(hits+misses) 572system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) 573system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) 574system.cpu.l2cache.ReadExReq_accesses::cpu.data 2836 # number of ReadExReq accesses(hits+misses) 575system.cpu.l2cache.ReadExReq_accesses::total 2836 # number of ReadExReq accesses(hits+misses) 576system.cpu.l2cache.demand_accesses::cpu.inst 16092 # number of demand (read+write) accesses 577system.cpu.l2cache.demand_accesses::cpu.data 4641 # number of demand (read+write) accesses 578system.cpu.l2cache.demand_accesses::total 20733 # number of demand (read+write) accesses 579system.cpu.l2cache.overall_accesses::cpu.inst 16092 # number of overall (read+write) accesses 580system.cpu.l2cache.overall_accesses::cpu.data 4641 # number of overall (read+write) accesses 581system.cpu.l2cache.overall_accesses::total 20733 # number of overall (read+write) accesses 582system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.194009 # miss rate for ReadReq accesses 583system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.834903 # miss rate for ReadReq accesses 584system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 585system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994006 # miss rate for ReadExReq accesses 586system.cpu.l2cache.demand_miss_rate::cpu.inst 0.194009 # miss rate for demand accesses 587system.cpu.l2cache.demand_miss_rate::cpu.data 0.932127 # miss rate for demand accesses 588system.cpu.l2cache.overall_miss_rate::cpu.inst 0.194009 # miss rate for overall accesses 589system.cpu.l2cache.overall_miss_rate::cpu.data 0.932127 # miss rate for overall accesses 590system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.136451 # average ReadReq miss latency 591system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34345.388188 # average ReadReq miss latency 592system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.055339 # average ReadExReq miss latency 593system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency 594system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency 595system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.136451 # average overall miss latency 596system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.536292 # average overall miss latency 597system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 598system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 599system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 600system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 601system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 602system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 603system.cpu.l2cache.fast_writes 0 # number of fast writes performed 604system.cpu.l2cache.cache_copies 0 # number of cache copies performed 605system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits 606system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 607system.cpu.l2cache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits 608system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits 609system.cpu.l2cache.demand_mshr_hits::cpu.data 49 # number of demand (read+write) MSHR hits 610system.cpu.l2cache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits 611system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits 612system.cpu.l2cache.overall_mshr_hits::cpu.data 49 # number of overall MSHR hits 613system.cpu.l2cache.overall_mshr_hits::total 59 # number of overall MSHR hits 614system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3112 # number of ReadReq MSHR misses 615system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1458 # number of ReadReq MSHR misses 616system.cpu.l2cache.ReadReq_mshr_misses::total 4570 # number of ReadReq MSHR misses 617system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 22 # number of UpgradeReq MSHR misses 618system.cpu.l2cache.UpgradeReq_mshr_misses::total 22 # number of UpgradeReq MSHR misses 619system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2819 # number of ReadExReq MSHR misses 620system.cpu.l2cache.ReadExReq_mshr_misses::total 2819 # number of ReadExReq MSHR misses 621system.cpu.l2cache.demand_mshr_misses::cpu.inst 3112 # number of demand (read+write) MSHR misses 622system.cpu.l2cache.demand_mshr_misses::cpu.data 4277 # number of demand (read+write) MSHR misses 623system.cpu.l2cache.demand_mshr_misses::total 7389 # number of demand (read+write) MSHR misses 624system.cpu.l2cache.overall_mshr_misses::cpu.inst 3112 # number of overall MSHR misses 625system.cpu.l2cache.overall_mshr_misses::cpu.data 4277 # number of overall MSHR misses 626system.cpu.l2cache.overall_mshr_misses::total 7389 # number of overall MSHR misses 627system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96743500 # number of ReadReq MSHR miss cycles 628system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45668000 # number of ReadReq MSHR miss cycles 629system.cpu.l2cache.ReadReq_mshr_miss_latency::total 142411500 # number of ReadReq MSHR miss cycles 630system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 682000 # number of UpgradeReq MSHR miss cycles 631system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 682000 # number of UpgradeReq MSHR miss cycles 632system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88208000 # number of ReadExReq MSHR miss cycles 633system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88208000 # number of ReadExReq MSHR miss cycles 634system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96743500 # number of demand (read+write) MSHR miss cycles 635system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 133876000 # number of demand (read+write) MSHR miss cycles 636system.cpu.l2cache.demand_mshr_miss_latency::total 230619500 # number of demand (read+write) MSHR miss cycles 637system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96743500 # number of overall MSHR miss cycles 638system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 133876000 # number of overall MSHR miss cycles 639system.cpu.l2cache.overall_mshr_miss_latency::total 230619500 # number of overall MSHR miss cycles 640system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for ReadReq accesses 641system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807756 # mshr miss rate for ReadReq accesses 642system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 643system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994006 # mshr miss rate for ReadExReq accesses 644system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for demand accesses 645system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for demand accesses 646system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.193388 # mshr miss rate for overall accesses 647system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921569 # mshr miss rate for overall accesses 648system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.242931 # average ReadReq mshr miss latency 649system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31322.359396 # average ReadReq mshr miss latency 650system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency 651system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31290.528556 # average ReadExReq mshr miss latency 652system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency 653system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency 654system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.242931 # average overall mshr miss latency 655system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31301.379472 # average overall mshr miss latency 656system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 657 658---------- End Simulation Statistics ---------- 659