stats.txt revision 11456:c0fb4435b80f
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.111754 # Number of seconds simulated 4sim_ticks 111753553500 # Number of ticks simulated 5final_tick 111753553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 153930 # Simulator instruction rate (inst/s) 8host_op_rate 184810 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 63003104 # Simulator tick rate (ticks/s) 10host_mem_usage 292088 # Number of bytes of host memory used 11host_seconds 1773.78 # Real time elapsed on the host 12sim_insts 273037220 # Number of instructions simulated 13sim_ops 327811602 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 620544 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4626112 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 168832 # Number of bytes read from this memory 19system.physmem.bytes_read::total 5415488 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 620544 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 620544 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 9696 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 72283 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 2638 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 84617 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 5552790 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 41395659 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 1510753 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 48459202 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 5552790 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 5552790 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 5552790 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 41395659 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 1510753 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 48459202 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 84617 # Number of read requests accepted 37system.physmem.writeReqs 0 # Number of write requests accepted 38system.physmem.readBursts 84617 # Number of DRAM read bursts, including those serviced by the write queue 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 40system.physmem.bytesReadDRAM 5415488 # Total number of bytes read from DRAM 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 43system.physmem.bytesReadSys 5415488 # Total read bytes from the system interface side 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 956 # Per bank write bursts 49system.physmem.perBankRdBursts::1 811 # Per bank write bursts 50system.physmem.perBankRdBursts::2 834 # Per bank write bursts 51system.physmem.perBankRdBursts::3 2907 # Per bank write bursts 52system.physmem.perBankRdBursts::4 10637 # Per bank write bursts 53system.physmem.perBankRdBursts::5 59817 # Per bank write bursts 54system.physmem.perBankRdBursts::6 152 # Per bank write bursts 55system.physmem.perBankRdBursts::7 259 # Per bank write bursts 56system.physmem.perBankRdBursts::8 225 # Per bank write bursts 57system.physmem.perBankRdBursts::9 303 # Per bank write bursts 58system.physmem.perBankRdBursts::10 3870 # Per bank write bursts 59system.physmem.perBankRdBursts::11 811 # Per bank write bursts 60system.physmem.perBankRdBursts::12 1141 # Per bank write bursts 61system.physmem.perBankRdBursts::13 693 # Per bank write bursts 62system.physmem.perBankRdBursts::14 638 # Per bank write bursts 63system.physmem.perBankRdBursts::15 563 # Per bank write bursts 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 82system.physmem.totGap 111753395000 # Total gap between requests 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) 89system.physmem.readPktSize::6 84617 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) 97system.physmem.rdQLenPdf::0 64967 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 17796 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 465 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 226 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 208 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 173 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 172 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 172 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 129system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 193system.physmem.bytesPerActivate::samples 21291 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 254.217463 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 213.921670 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 155.515771 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 2572 12.08% 12.08% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 7102 33.36% 45.44% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 8141 38.24% 83.67% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 1445 6.79% 90.46% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 1060 4.98% 95.44% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 699 3.28% 98.72% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 33 0.15% 98.88% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 27 0.13% 99.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 212 1.00% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 21291 # Bytes accessed per row activation 207system.physmem.totQLat 818886094 # Total ticks spent queuing 208system.physmem.totMemAccLat 2405454844 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 423085000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 9677.56 # Average queueing delay per DRAM burst 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 212system.physmem.avgMemAccLat 28427.56 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 48.46 # Average DRAM read bandwidth in MiByte/s 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 215system.physmem.avgRdBWSys 48.46 # Average system read bandwidth in MiByte/s 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 0.38 # Data bus utilization in percentage 219system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 221system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 63316 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes 225system.physmem.readRowHitRate 74.83 # Row buffer hit rate for reads 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 227system.physmem.avgGap 1320696.73 # Average gap between requests 228system.physmem.pageHitRate 74.83 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 137093040 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 74802750 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 595467600 # Energy for read commands per rank (pJ) 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) 234system.physmem_0.actBackEnergy 61580578995 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 13031079750 # Energy for precharge background per rank (pJ) 236system.physmem_0.totalEnergy 82717875255 # Total energy per rank (pJ) 237system.physmem_0.averagePower 740.214288 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 21327892271 # Time in different power states 239system.physmem_0.memoryStateTime::REF 3731520000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 241system.physmem_0.memoryStateTime::ACT 86689152979 # Time in different power states 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.physmem_1.actEnergy 23821560 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 12997875 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 64092600 # Energy for read commands per rank (pJ) 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 7298853120 # Energy for refresh commands per rank (pJ) 248system.physmem_1.actBackEnergy 10878672015 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 57506417250 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 75784854420 # Total energy per rank (pJ) 251system.physmem_1.averagePower 678.173227 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 95612479879 # Time in different power states 253system.physmem_1.memoryStateTime::REF 3731520000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.physmem_1.memoryStateTime::ACT 12405217621 # Time in different power states 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 35971731 # Number of BP lookups 258system.cpu.branchPred.condPredicted 19265386 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 984189 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 17894968 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 13923402 # Number of BTB hits 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 263system.cpu.branchPred.BTBHitPct 77.806241 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 6951964 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 4431 # Number of incorrect RAS predictions. 266system.cpu.branchPred.indirectLookups 2517343 # Number of indirect predictor lookups. 267system.cpu.branchPred.indirectHits 2473442 # Number of indirect target hits. 268system.cpu.branchPred.indirectMisses 43901 # Number of indirect misses. 269system.cpu.branchPredindirectMispredicted 128855 # Number of mispredicted indirect branches. 270system.cpu_clk_domain.clock 500 # Clock period in ticks 271system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 280system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 281system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 282system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 283system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 284system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 285system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 286system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 287system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 288system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 289system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 290system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 291system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 292system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 293system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 294system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 295system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 296system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 297system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 298system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 299system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.inst_hits 0 # ITB inst hits 309system.cpu.dtb.inst_misses 0 # ITB inst misses 310system.cpu.dtb.read_hits 0 # DTB read hits 311system.cpu.dtb.read_misses 0 # DTB read misses 312system.cpu.dtb.write_hits 0 # DTB write hits 313system.cpu.dtb.write_misses 0 # DTB write misses 314system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 315system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 316system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 317system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 318system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 319system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 320system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses 329system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 338system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 339system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 340system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 341system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 342system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 343system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 344system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 345system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 346system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 347system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 348system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 349system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 350system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 351system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 352system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 353system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 354system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 355system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 356system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 357system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 358system.cpu.itb.walker.walks 0 # Table walker walks requested 359system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.inst_hits 0 # ITB inst hits 367system.cpu.itb.inst_misses 0 # ITB inst misses 368system.cpu.itb.read_hits 0 # DTB read hits 369system.cpu.itb.read_misses 0 # DTB read misses 370system.cpu.itb.write_hits 0 # DTB write hits 371system.cpu.itb.write_misses 0 # DTB write misses 372system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 373system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 374system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 375system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 376system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 377system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 378system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 379system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 380system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 381system.cpu.itb.read_accesses 0 # DTB read accesses 382system.cpu.itb.write_accesses 0 # DTB write accesses 383system.cpu.itb.inst_accesses 0 # ITB inst accesses 384system.cpu.itb.hits 0 # DTB hits 385system.cpu.itb.misses 0 # DTB misses 386system.cpu.itb.accesses 0 # DTB accesses 387system.cpu.workload.num_syscalls 191 # Number of system calls 388system.cpu.numCycles 223507108 # number of cpu cycles simulated 389system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 390system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 391system.cpu.fetch.icacheStallCycles 12083599 # Number of cycles fetch is stalled on an Icache miss 392system.cpu.fetch.Insts 309381854 # Number of instructions fetch has processed 393system.cpu.fetch.Branches 35971731 # Number of branches that fetch encountered 394system.cpu.fetch.predictedBranches 23348808 # Number of branches that fetch has predicted taken 395system.cpu.fetch.Cycles 209499863 # Number of cycles fetch has run and was not squashing or blocked 396system.cpu.fetch.SquashCycles 1989645 # Number of cycles fetch has spent squashing 397system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 398system.cpu.fetch.PendingTrapStallCycles 93 # Number of stall cycles due to pending traps 399system.cpu.fetch.IcacheWaitRetryStallCycles 2666 # Number of stall cycles due to full MSHR 400system.cpu.fetch.CacheLines 82203342 # Number of cache lines fetched 401system.cpu.fetch.IcacheSquashes 33398 # Number of outstanding Icache misses that were squashed 402system.cpu.fetch.rateDist::samples 222582301 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::mean 1.671920 # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::stdev 1.267628 # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::0 62373241 28.02% 28.02% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::1 40203334 18.06% 46.08% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::2 28080746 12.62% 58.70% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::3 91924980 41.30% 100.00% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::total 222582301 # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.branchRate 0.160942 # Number of branch fetches per cycle 415system.cpu.fetch.rate 1.384215 # Number of inst fetches per cycle 416system.cpu.decode.IdleCycles 26238985 # Number of cycles decode is idle 417system.cpu.decode.BlockedCycles 73050782 # Number of cycles decode is blocked 418system.cpu.decode.RunCycles 98117127 # Number of cycles decode is running 419system.cpu.decode.UnblockCycles 24314460 # Number of cycles decode is unblocking 420system.cpu.decode.SquashCycles 860947 # Number of cycles decode is squashing 421system.cpu.decode.BranchResolved 6686817 # Number of times decode resolved a branch 422system.cpu.decode.BranchMispred 134221 # Number of times decode detected a branch misprediction 423system.cpu.decode.DecodedInsts 348541423 # Number of instructions handled by decode 424system.cpu.decode.SquashedInsts 3410145 # Number of squashed instructions handled by decode 425system.cpu.rename.SquashCycles 860947 # Number of cycles rename is squashing 426system.cpu.rename.IdleCycles 42548430 # Number of cycles rename is idle 427system.cpu.rename.BlockCycles 23450678 # Number of cycles rename is blocking 428system.cpu.rename.serializeStallCycles 285531 # count of cycles rename stalled for serializing inst 429system.cpu.rename.RunCycles 105165670 # Number of cycles rename is running 430system.cpu.rename.UnblockCycles 50271045 # Number of cycles rename is unblocking 431system.cpu.rename.RenamedInsts 344601348 # Number of instructions processed by rename 432system.cpu.rename.SquashedInsts 1453656 # Number of squashed instructions processed by rename 433system.cpu.rename.ROBFullEvents 7084396 # Number of times rename has blocked due to ROB full 434system.cpu.rename.IQFullEvents 85832 # Number of times rename has blocked due to IQ full 435system.cpu.rename.LQFullEvents 7483674 # Number of times rename has blocked due to LQ full 436system.cpu.rename.SQFullEvents 23725025 # Number of times rename has blocked due to SQ full 437system.cpu.rename.FullRegisterEvents 3279176 # Number of times there has been no free registers 438system.cpu.rename.RenamedOperands 394880845 # Number of destination operands rename has renamed 439system.cpu.rename.RenameLookups 2465405554 # Number of register rename lookups that rename has made 440system.cpu.rename.int_rename_lookups 335914250 # Number of integer rename lookups 441system.cpu.rename.fp_rename_lookups 192916662 # Number of floating rename lookups 442system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed 443system.cpu.rename.UndoneMaps 22650794 # Number of HB maps that are undone due to squashing 444system.cpu.rename.serializingInsts 11588 # count of serializing insts renamed 445system.cpu.rename.tempSerializingInsts 11554 # count of temporary serializing insts renamed 446system.cpu.rename.skidInsts 57533645 # count of insts added to the skid buffer 447system.cpu.memDep0.insertedLoads 89989968 # Number of loads inserted to the mem dependence unit. 448system.cpu.memDep0.insertedStores 84391268 # Number of stores inserted to the mem dependence unit. 449system.cpu.memDep0.conflictingLoads 1975718 # Number of conflicting loads. 450system.cpu.memDep0.conflictingStores 1902358 # Number of conflicting stores. 451system.cpu.iq.iqInstsAdded 343283622 # Number of instructions added to the IQ (excludes non-spec) 452system.cpu.iq.iqNonSpecInstsAdded 22608 # Number of non-speculative instructions added to the IQ 453system.cpu.iq.iqInstsIssued 339469619 # Number of instructions issued 454system.cpu.iq.iqSquashedInstsIssued 966789 # Number of squashed instructions issued 455system.cpu.iq.iqSquashedInstsExamined 15494628 # Number of squashed instructions iterated over during squash; mainly for profiling 456system.cpu.iq.iqSquashedOperandsExamined 40533427 # Number of squashed operands that are examined and possibly removed from graph 457system.cpu.iq.iqSquashedNonSpecRemoved 488 # Number of squashed non-spec instructions that were removed 458system.cpu.iq.issued_per_cycle::samples 222582301 # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::mean 1.525142 # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::stdev 1.109331 # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::0 42440680 19.07% 19.07% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::1 76122495 34.20% 53.27% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::2 59389973 26.68% 79.95% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::3 34692267 15.59% 95.54% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::4 9226095 4.15% 99.68% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::5 678749 0.30% 99.99% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::6 32042 0.01% 100.00% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::total 222582301 # Number of insts issued each cycle 475system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 476system.cpu.iq.fu_full::IntAlu 9228112 7.75% 7.75% # attempts to use FU when none available 477system.cpu.iq.fu_full::IntMult 7358 0.01% 7.75% # attempts to use FU when none available 478system.cpu.iq.fu_full::IntDiv 0 0.00% 7.75% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.75% # attempts to use FU when none available 480system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.75% # attempts to use FU when none available 481system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.75% # attempts to use FU when none available 482system.cpu.iq.fu_full::FloatMult 0 0.00% 7.75% # attempts to use FU when none available 483system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.75% # attempts to use FU when none available 484system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.75% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.75% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.75% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.75% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.75% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.75% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.75% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdMult 0 0.00% 7.75% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.75% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdShift 0 0.00% 7.75% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.75% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.75% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatAdd 237798 0.20% 7.95% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.95% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatCmp 147681 0.12% 8.08% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatCvt 70485 0.06% 8.14% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatDiv 67886 0.06% 8.19% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatMisc 638269 0.54% 8.73% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatMult 297789 0.25% 8.98% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatMultAcc 542439 0.46% 9.44% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available 505system.cpu.iq.fu_full::MemRead 51542568 43.28% 52.71% # attempts to use FU when none available 506system.cpu.iq.fu_full::MemWrite 56315471 47.29% 100.00% # attempts to use FU when none available 507system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 508system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 509system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 510system.cpu.iq.FU_type_0::IntAlu 108184507 31.87% 31.87% # Type of FU issued 511system.cpu.iq.FU_type_0::IntMult 2148145 0.63% 32.50% # Type of FU issued 512system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.50% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.50% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.50% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.50% # Type of FU issued 516system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.50% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.50% # Type of FU issued 518system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.50% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.50% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.50% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.50% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.50% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.50% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.50% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.50% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.50% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.50% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.50% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.50% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatAdd 6792731 2.00% 34.50% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.50% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatCmp 8635726 2.54% 37.05% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatCvt 3210403 0.95% 37.99% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatDiv 1592905 0.47% 38.46% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatMisc 20864008 6.15% 44.61% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatMult 7178651 2.11% 46.72% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatMultAcc 7141492 2.10% 48.83% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatSqrt 175295 0.05% 48.88% # Type of FU issued 539system.cpu.iq.FU_type_0::MemRead 90027492 26.52% 75.40% # Type of FU issued 540system.cpu.iq.FU_type_0::MemWrite 83518264 24.60% 100.00% # Type of FU issued 541system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 542system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 543system.cpu.iq.FU_type_0::total 339469619 # Type of FU issued 544system.cpu.iq.rate 1.518831 # Inst issue rate 545system.cpu.iq.fu_busy_cnt 119095856 # FU busy when requested 546system.cpu.iq.fu_busy_rate 0.350829 # FU busy rate (busy events/executed inst) 547system.cpu.iq.int_inst_queue_reads 738018306 # Number of integer instruction queue reads 548system.cpu.iq.int_inst_queue_writes 235153924 # Number of integer instruction queue writes 549system.cpu.iq.int_inst_queue_wakeup_accesses 219171367 # Number of integer instruction queue wakeup accesses 550system.cpu.iq.fp_inst_queue_reads 283565878 # Number of floating instruction queue reads 551system.cpu.iq.fp_inst_queue_writes 123658767 # Number of floating instruction queue writes 552system.cpu.iq.fp_inst_queue_wakeup_accesses 116921576 # Number of floating instruction queue wakeup accesses 553system.cpu.iq.int_alu_accesses 293614389 # Number of integer alu accesses 554system.cpu.iq.fp_alu_accesses 164951086 # Number of floating point alu accesses 555system.cpu.iew.lsq.thread0.forwLoads 5389138 # Number of loads that had data forwarded from stores 556system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 557system.cpu.iew.lsq.thread0.squashedLoads 4257693 # Number of loads squashed 558system.cpu.iew.lsq.thread0.ignoredResponses 7295 # Number of memory responses ignored because the instruction is squashed 559system.cpu.iew.lsq.thread0.memOrderViolation 11836 # Number of memory ordering violations 560system.cpu.iew.lsq.thread0.squashedStores 2015651 # Number of stores squashed 561system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 562system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 563system.cpu.iew.lsq.thread0.rescheduledLoads 126905 # Number of loads that were rescheduled 564system.cpu.iew.lsq.thread0.cacheBlocked 613909 # Number of times an access to memory failed due to the cache being blocked 565system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 566system.cpu.iew.iewSquashCycles 860947 # Number of cycles IEW is squashing 567system.cpu.iew.iewBlockCycles 1344821 # Number of cycles IEW is blocking 568system.cpu.iew.iewUnblockCycles 736472 # Number of cycles IEW is unblocking 569system.cpu.iew.iewDispatchedInsts 343307622 # Number of instructions dispatched to IQ 570system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 571system.cpu.iew.iewDispLoadInsts 89989968 # Number of dispatched load instructions 572system.cpu.iew.iewDispStoreInsts 84391268 # Number of dispatched store instructions 573system.cpu.iew.iewDispNonSpecInsts 11575 # Number of dispatched non-speculative instructions 574system.cpu.iew.iewIQFullEvents 7371 # Number of times the IQ has become full, causing a stall 575system.cpu.iew.iewLSQFullEvents 729404 # Number of times the LSQ has become full, causing a stall 576system.cpu.iew.memOrderViolationEvents 11836 # Number of memory order violations 577system.cpu.iew.predictedTakenIncorrect 437891 # Number of branches that were predicted taken incorrectly 578system.cpu.iew.predictedNotTakenIncorrect 454375 # Number of branches that were predicted not taken incorrectly 579system.cpu.iew.branchMispredicts 892266 # Number of branch mispredicts detected at execute 580system.cpu.iew.iewExecutedInsts 337441545 # Number of executed instructions 581system.cpu.iew.iewExecLoadInsts 89439870 # Number of load instructions executed 582system.cpu.iew.iewExecSquashedInsts 2028074 # Number of squashed instructions skipped in execute 583system.cpu.iew.exec_swp 0 # number of swp insts executed 584system.cpu.iew.exec_nop 1392 # number of nop insts executed 585system.cpu.iew.exec_refs 172567373 # number of memory reference insts executed 586system.cpu.iew.exec_branches 31555849 # Number of branches executed 587system.cpu.iew.exec_stores 83127503 # Number of stores executed 588system.cpu.iew.exec_rate 1.509758 # Inst execution rate 589system.cpu.iew.wb_sent 336239137 # cumulative count of insts sent to commit 590system.cpu.iew.wb_count 336092943 # cumulative count of insts written-back 591system.cpu.iew.wb_producers 151867680 # num instructions producing a value 592system.cpu.iew.wb_consumers 263704827 # num instructions consuming a value 593system.cpu.iew.wb_rate 1.503724 # insts written-back per cycle 594system.cpu.iew.wb_fanout 0.575900 # average fanout of values written-back 595system.cpu.commit.commitSquashedInsts 14172678 # The number of squashed insts skipped by commit 596system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 597system.cpu.commit.branchMispredicts 850314 # The number of times a branch was mispredicted 598system.cpu.commit.committed_per_cycle::samples 220392023 # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::mean 1.487405 # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::stdev 2.078236 # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::0 89247998 40.50% 40.50% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::1 67546822 30.65% 71.14% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::2 20918501 9.49% 80.64% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::3 13253983 6.01% 86.65% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::4 8642695 3.92% 90.57% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::5 4496391 2.04% 92.61% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::6 3033426 1.38% 93.99% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::7 2604506 1.18% 95.17% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::8 10647701 4.83% 100.00% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::total 220392023 # Number of insts commited each cycle 615system.cpu.commit.committedInsts 273037832 # Number of instructions committed 616system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed 617system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 618system.cpu.commit.refs 168107892 # Number of memory references committed 619system.cpu.commit.loads 85732275 # Number of loads committed 620system.cpu.commit.membars 11033 # Number of memory barriers committed 621system.cpu.commit.branches 30563526 # Number of branches committed 622system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 623system.cpu.commit.int_insts 258331704 # Number of committed integer instructions. 624system.cpu.commit.function_calls 6225114 # Number of function calls committed. 625system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 626system.cpu.commit.op_class_0::IntAlu 104312487 31.82% 31.82% # Class of committed instruction 627system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction 628system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 629system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 630system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 631system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 632system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction 633system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction 634system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction 635system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction 638system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction 639system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction 640system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction 641system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction 642system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction 643system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction 644system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction 645system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction 646system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction 647system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction 648system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction 649system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 655system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 656system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 657system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 658system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 659system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction 660system.cpu.commit.bw_lim_events 10647701 # number cycles where commit BW limit reached 661system.cpu.rob.rob_reads 551726691 # The number of ROB reads 662system.cpu.rob.rob_writes 686162246 # The number of ROB writes 663system.cpu.timesIdled 18335 # Number of times that the entire CPU went into an idle state and unscheduled itself 664system.cpu.idleCycles 924807 # Total number of cycles that the CPU has spent unscheduled due to idling 665system.cpu.committedInsts 273037220 # Number of Instructions Simulated 666system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated 667system.cpu.cpi 0.818596 # CPI: Cycles Per Instruction 668system.cpu.cpi_total 0.818596 # CPI: Total CPI of All Threads 669system.cpu.ipc 1.221604 # IPC: Instructions Per Cycle 670system.cpu.ipc_total 1.221604 # IPC: Total IPC of All Threads 671system.cpu.int_regfile_reads 325161919 # number of integer regfile reads 672system.cpu.int_regfile_writes 134094717 # number of integer regfile writes 673system.cpu.fp_regfile_reads 186641875 # number of floating regfile reads 674system.cpu.fp_regfile_writes 131668024 # number of floating regfile writes 675system.cpu.cc_regfile_reads 1279432977 # number of cc regfile reads 676system.cpu.cc_regfile_writes 80060950 # number of cc regfile writes 677system.cpu.misc_regfile_reads 1175447344 # number of misc regfile reads 678system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 679system.cpu.dcache.tags.replacements 1542955 # number of replacements 680system.cpu.dcache.tags.tagsinuse 511.836799 # Cycle average of tags in use 681system.cpu.dcache.tags.total_refs 162076726 # Total number of references to valid blocks. 682system.cpu.dcache.tags.sampled_refs 1543467 # Sample count of references to valid blocks. 683system.cpu.dcache.tags.avg_refs 105.008222 # Average number of references to valid blocks. 684system.cpu.dcache.tags.warmup_cycle 85416000 # Cycle when the warmup percentage was hit. 685system.cpu.dcache.tags.occ_blocks::cpu.data 511.836799 # Average occupied blocks per requestor 686system.cpu.dcache.tags.occ_percent::cpu.data 0.999681 # Average percentage of cache occupancy 687system.cpu.dcache.tags.occ_percent::total 0.999681 # Average percentage of cache occupancy 688system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 689system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 690system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id 691system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id 692system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 693system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 694system.cpu.dcache.tags.tag_accesses 333528119 # Number of tag accesses 695system.cpu.dcache.tags.data_accesses 333528119 # Number of data accesses 696system.cpu.dcache.ReadReq_hits::cpu.data 81065236 # number of ReadReq hits 697system.cpu.dcache.ReadReq_hits::total 81065236 # number of ReadReq hits 698system.cpu.dcache.WriteReq_hits::cpu.data 80920030 # number of WriteReq hits 699system.cpu.dcache.WriteReq_hits::total 80920030 # number of WriteReq hits 700system.cpu.dcache.SoftPFReq_hits::cpu.data 69611 # number of SoftPFReq hits 701system.cpu.dcache.SoftPFReq_hits::total 69611 # number of SoftPFReq hits 702system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits 703system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits 704system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 705system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 706system.cpu.dcache.demand_hits::cpu.data 161985266 # number of demand (read+write) hits 707system.cpu.dcache.demand_hits::total 161985266 # number of demand (read+write) hits 708system.cpu.dcache.overall_hits::cpu.data 162054877 # number of overall hits 709system.cpu.dcache.overall_hits::total 162054877 # number of overall hits 710system.cpu.dcache.ReadReq_misses::cpu.data 2782957 # number of ReadReq misses 711system.cpu.dcache.ReadReq_misses::total 2782957 # number of ReadReq misses 712system.cpu.dcache.WriteReq_misses::cpu.data 1132669 # number of WriteReq misses 713system.cpu.dcache.WriteReq_misses::total 1132669 # number of WriteReq misses 714system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses 715system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses 716system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 717system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses 718system.cpu.dcache.demand_misses::cpu.data 3915626 # number of demand (read+write) misses 719system.cpu.dcache.demand_misses::total 3915626 # number of demand (read+write) misses 720system.cpu.dcache.overall_misses::cpu.data 3915644 # number of overall misses 721system.cpu.dcache.overall_misses::total 3915644 # number of overall misses 722system.cpu.dcache.ReadReq_miss_latency::cpu.data 31092984500 # number of ReadReq miss cycles 723system.cpu.dcache.ReadReq_miss_latency::total 31092984500 # number of ReadReq miss cycles 724system.cpu.dcache.WriteReq_miss_latency::cpu.data 9127104911 # number of WriteReq miss cycles 725system.cpu.dcache.WriteReq_miss_latency::total 9127104911 # number of WriteReq miss cycles 726system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 182000 # number of LoadLockedReq miss cycles 727system.cpu.dcache.LoadLockedReq_miss_latency::total 182000 # number of LoadLockedReq miss cycles 728system.cpu.dcache.demand_miss_latency::cpu.data 40220089411 # number of demand (read+write) miss cycles 729system.cpu.dcache.demand_miss_latency::total 40220089411 # number of demand (read+write) miss cycles 730system.cpu.dcache.overall_miss_latency::cpu.data 40220089411 # number of overall miss cycles 731system.cpu.dcache.overall_miss_latency::total 40220089411 # number of overall miss cycles 732system.cpu.dcache.ReadReq_accesses::cpu.data 83848193 # number of ReadReq accesses(hits+misses) 733system.cpu.dcache.ReadReq_accesses::total 83848193 # number of ReadReq accesses(hits+misses) 734system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 735system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) 736system.cpu.dcache.SoftPFReq_accesses::cpu.data 69629 # number of SoftPFReq accesses(hits+misses) 737system.cpu.dcache.SoftPFReq_accesses::total 69629 # number of SoftPFReq accesses(hits+misses) 738system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) 739system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) 740system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 741system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 742system.cpu.dcache.demand_accesses::cpu.data 165900892 # number of demand (read+write) accesses 743system.cpu.dcache.demand_accesses::total 165900892 # number of demand (read+write) accesses 744system.cpu.dcache.overall_accesses::cpu.data 165970521 # number of overall (read+write) accesses 745system.cpu.dcache.overall_accesses::total 165970521 # number of overall (read+write) accesses 746system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033190 # miss rate for ReadReq accesses 747system.cpu.dcache.ReadReq_miss_rate::total 0.033190 # miss rate for ReadReq accesses 748system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013804 # miss rate for WriteReq accesses 749system.cpu.dcache.WriteReq_miss_rate::total 0.013804 # miss rate for WriteReq accesses 750system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000259 # miss rate for SoftPFReq accesses 751system.cpu.dcache.SoftPFReq_miss_rate::total 0.000259 # miss rate for SoftPFReq accesses 752system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses 753system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses 754system.cpu.dcache.demand_miss_rate::cpu.data 0.023602 # miss rate for demand accesses 755system.cpu.dcache.demand_miss_rate::total 0.023602 # miss rate for demand accesses 756system.cpu.dcache.overall_miss_rate::cpu.data 0.023592 # miss rate for overall accesses 757system.cpu.dcache.overall_miss_rate::total 0.023592 # miss rate for overall accesses 758system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804 # average ReadReq miss latency 759system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804 # average ReadReq miss latency 760system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8058.051303 # average WriteReq miss latency 761system.cpu.dcache.WriteReq_avg_miss_latency::total 8058.051303 # average WriteReq miss latency 762system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 45500 # average LoadLockedReq miss latency 763system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 45500 # average LoadLockedReq miss latency 764system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208 # average overall miss latency 765system.cpu.dcache.demand_avg_miss_latency::total 10271.688208 # average overall miss latency 766system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990 # average overall miss latency 767system.cpu.dcache.overall_avg_miss_latency::total 10271.640990 # average overall miss latency 768system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 769system.cpu.dcache.blocked_cycles::no_targets 1079488 # number of cycles access was blocked 770system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 771system.cpu.dcache.blocked::no_targets 136770 # number of cycles access was blocked 772system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 773system.cpu.dcache.avg_blocked_cycles::no_targets 7.892725 # average number of cycles each access was blocked 774system.cpu.dcache.writebacks::writebacks 1542955 # number of writebacks 775system.cpu.dcache.writebacks::total 1542955 # number of writebacks 776system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1460236 # number of ReadReq MSHR hits 777system.cpu.dcache.ReadReq_mshr_hits::total 1460236 # number of ReadReq MSHR hits 778system.cpu.dcache.WriteReq_mshr_hits::cpu.data 911920 # number of WriteReq MSHR hits 779system.cpu.dcache.WriteReq_mshr_hits::total 911920 # number of WriteReq MSHR hits 780system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 781system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 782system.cpu.dcache.demand_mshr_hits::cpu.data 2372156 # number of demand (read+write) MSHR hits 783system.cpu.dcache.demand_mshr_hits::total 2372156 # number of demand (read+write) MSHR hits 784system.cpu.dcache.overall_mshr_hits::cpu.data 2372156 # number of overall MSHR hits 785system.cpu.dcache.overall_mshr_hits::total 2372156 # number of overall MSHR hits 786system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322721 # number of ReadReq MSHR misses 787system.cpu.dcache.ReadReq_mshr_misses::total 1322721 # number of ReadReq MSHR misses 788system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220749 # number of WriteReq MSHR misses 789system.cpu.dcache.WriteReq_mshr_misses::total 220749 # number of WriteReq MSHR misses 790system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 791system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses 792system.cpu.dcache.demand_mshr_misses::cpu.data 1543470 # number of demand (read+write) MSHR misses 793system.cpu.dcache.demand_mshr_misses::total 1543470 # number of demand (read+write) MSHR misses 794system.cpu.dcache.overall_mshr_misses::cpu.data 1543481 # number of overall MSHR misses 795system.cpu.dcache.overall_mshr_misses::total 1543481 # number of overall MSHR misses 796system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15298451500 # number of ReadReq MSHR miss cycles 797system.cpu.dcache.ReadReq_mshr_miss_latency::total 15298451500 # number of ReadReq MSHR miss cycles 798system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1831859691 # number of WriteReq MSHR miss cycles 799system.cpu.dcache.WriteReq_mshr_miss_latency::total 1831859691 # number of WriteReq MSHR miss cycles 800system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 695500 # number of SoftPFReq MSHR miss cycles 801system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 695500 # number of SoftPFReq MSHR miss cycles 802system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17130311191 # number of demand (read+write) MSHR miss cycles 803system.cpu.dcache.demand_mshr_miss_latency::total 17130311191 # number of demand (read+write) MSHR miss cycles 804system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17131006691 # number of overall MSHR miss cycles 805system.cpu.dcache.overall_mshr_miss_latency::total 17131006691 # number of overall MSHR miss cycles 806system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015775 # mshr miss rate for ReadReq accesses 807system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015775 # mshr miss rate for ReadReq accesses 808system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses 809system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses 810system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000158 # mshr miss rate for SoftPFReq accesses 811system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000158 # mshr miss rate for SoftPFReq accesses 812system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009304 # mshr miss rate for demand accesses 813system.cpu.dcache.demand_mshr_miss_rate::total 0.009304 # mshr miss rate for demand accesses 814system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009300 # mshr miss rate for overall accesses 815system.cpu.dcache.overall_mshr_miss_rate::total 0.009300 # mshr miss rate for overall accesses 816system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471 # average ReadReq mshr miss latency 817system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471 # average ReadReq mshr miss latency 818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8298.382738 # average WriteReq mshr miss latency 819system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8298.382738 # average WriteReq mshr miss latency 820system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727 # average SoftPFReq mshr miss latency 821system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727 # average SoftPFReq mshr miss latency 822system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877 # average overall mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385 # average overall mshr miss latency 825system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385 # average overall mshr miss latency 826system.cpu.icache.tags.replacements 726201 # number of replacements 827system.cpu.icache.tags.tagsinuse 511.803602 # Cycle average of tags in use 828system.cpu.icache.tags.total_refs 81470529 # Total number of references to valid blocks. 829system.cpu.icache.tags.sampled_refs 726713 # Sample count of references to valid blocks. 830system.cpu.icache.tags.avg_refs 112.108259 # Average number of references to valid blocks. 831system.cpu.icache.tags.warmup_cycle 331355500 # Cycle when the warmup percentage was hit. 832system.cpu.icache.tags.occ_blocks::cpu.inst 511.803602 # Average occupied blocks per requestor 833system.cpu.icache.tags.occ_percent::cpu.inst 0.999616 # Average percentage of cache occupancy 834system.cpu.icache.tags.occ_percent::total 0.999616 # Average percentage of cache occupancy 835system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 836system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::2 242 # Occupied blocks per task id 839system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 840system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id 841system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 842system.cpu.icache.tags.tag_accesses 165133375 # Number of tag accesses 843system.cpu.icache.tags.data_accesses 165133375 # Number of data accesses 844system.cpu.icache.ReadReq_hits::cpu.inst 81470529 # number of ReadReq hits 845system.cpu.icache.ReadReq_hits::total 81470529 # number of ReadReq hits 846system.cpu.icache.demand_hits::cpu.inst 81470529 # number of demand (read+write) hits 847system.cpu.icache.demand_hits::total 81470529 # number of demand (read+write) hits 848system.cpu.icache.overall_hits::cpu.inst 81470529 # number of overall hits 849system.cpu.icache.overall_hits::total 81470529 # number of overall hits 850system.cpu.icache.ReadReq_misses::cpu.inst 732796 # number of ReadReq misses 851system.cpu.icache.ReadReq_misses::total 732796 # number of ReadReq misses 852system.cpu.icache.demand_misses::cpu.inst 732796 # number of demand (read+write) misses 853system.cpu.icache.demand_misses::total 732796 # number of demand (read+write) misses 854system.cpu.icache.overall_misses::cpu.inst 732796 # number of overall misses 855system.cpu.icache.overall_misses::total 732796 # number of overall misses 856system.cpu.icache.ReadReq_miss_latency::cpu.inst 6565806949 # number of ReadReq miss cycles 857system.cpu.icache.ReadReq_miss_latency::total 6565806949 # number of ReadReq miss cycles 858system.cpu.icache.demand_miss_latency::cpu.inst 6565806949 # number of demand (read+write) miss cycles 859system.cpu.icache.demand_miss_latency::total 6565806949 # number of demand (read+write) miss cycles 860system.cpu.icache.overall_miss_latency::cpu.inst 6565806949 # number of overall miss cycles 861system.cpu.icache.overall_miss_latency::total 6565806949 # number of overall miss cycles 862system.cpu.icache.ReadReq_accesses::cpu.inst 82203325 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.ReadReq_accesses::total 82203325 # number of ReadReq accesses(hits+misses) 864system.cpu.icache.demand_accesses::cpu.inst 82203325 # number of demand (read+write) accesses 865system.cpu.icache.demand_accesses::total 82203325 # number of demand (read+write) accesses 866system.cpu.icache.overall_accesses::cpu.inst 82203325 # number of overall (read+write) accesses 867system.cpu.icache.overall_accesses::total 82203325 # number of overall (read+write) accesses 868system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008914 # miss rate for ReadReq accesses 869system.cpu.icache.ReadReq_miss_rate::total 0.008914 # miss rate for ReadReq accesses 870system.cpu.icache.demand_miss_rate::cpu.inst 0.008914 # miss rate for demand accesses 871system.cpu.icache.demand_miss_rate::total 0.008914 # miss rate for demand accesses 872system.cpu.icache.overall_miss_rate::cpu.inst 0.008914 # miss rate for overall accesses 873system.cpu.icache.overall_miss_rate::total 0.008914 # miss rate for overall accesses 874system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8959.938303 # average ReadReq miss latency 875system.cpu.icache.ReadReq_avg_miss_latency::total 8959.938303 # average ReadReq miss latency 876system.cpu.icache.demand_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency 877system.cpu.icache.demand_avg_miss_latency::total 8959.938303 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::cpu.inst 8959.938303 # average overall miss latency 879system.cpu.icache.overall_avg_miss_latency::total 8959.938303 # average overall miss latency 880system.cpu.icache.blocked_cycles::no_mshrs 64284 # number of cycles access was blocked 881system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked 882system.cpu.icache.blocked::no_mshrs 3051 # number of cycles access was blocked 883system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 884system.cpu.icache.avg_blocked_cycles::no_mshrs 21.069813 # average number of cycles each access was blocked 885system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked 886system.cpu.icache.writebacks::writebacks 726201 # number of writebacks 887system.cpu.icache.writebacks::total 726201 # number of writebacks 888system.cpu.icache.ReadReq_mshr_hits::cpu.inst 6071 # number of ReadReq MSHR hits 889system.cpu.icache.ReadReq_mshr_hits::total 6071 # number of ReadReq MSHR hits 890system.cpu.icache.demand_mshr_hits::cpu.inst 6071 # number of demand (read+write) MSHR hits 891system.cpu.icache.demand_mshr_hits::total 6071 # number of demand (read+write) MSHR hits 892system.cpu.icache.overall_mshr_hits::cpu.inst 6071 # number of overall MSHR hits 893system.cpu.icache.overall_mshr_hits::total 6071 # number of overall MSHR hits 894system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726725 # number of ReadReq MSHR misses 895system.cpu.icache.ReadReq_mshr_misses::total 726725 # number of ReadReq MSHR misses 896system.cpu.icache.demand_mshr_misses::cpu.inst 726725 # number of demand (read+write) MSHR misses 897system.cpu.icache.demand_mshr_misses::total 726725 # number of demand (read+write) MSHR misses 898system.cpu.icache.overall_mshr_misses::cpu.inst 726725 # number of overall MSHR misses 899system.cpu.icache.overall_mshr_misses::total 726725 # number of overall MSHR misses 900system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6109081458 # number of ReadReq MSHR miss cycles 901system.cpu.icache.ReadReq_mshr_miss_latency::total 6109081458 # number of ReadReq MSHR miss cycles 902system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6109081458 # number of demand (read+write) MSHR miss cycles 903system.cpu.icache.demand_mshr_miss_latency::total 6109081458 # number of demand (read+write) MSHR miss cycles 904system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6109081458 # number of overall MSHR miss cycles 905system.cpu.icache.overall_mshr_miss_latency::total 6109081458 # number of overall MSHR miss cycles 906system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for ReadReq accesses 907system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008841 # mshr miss rate for ReadReq accesses 908system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for demand accesses 909system.cpu.icache.demand_mshr_miss_rate::total 0.008841 # mshr miss rate for demand accesses 910system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008841 # mshr miss rate for overall accesses 911system.cpu.icache.overall_mshr_miss_rate::total 0.008841 # mshr miss rate for overall accesses 912system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8406.318013 # average ReadReq mshr miss latency 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8406.318013 # average ReadReq mshr miss latency 914system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency 916system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8406.318013 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::total 8406.318013 # average overall mshr miss latency 918system.cpu.l2cache.prefetcher.num_hwpf_issued 402434 # number of hwpf issued 919system.cpu.l2cache.prefetcher.pfIdentified 402547 # number of prefetch candidates identified 920system.cpu.l2cache.prefetcher.pfBufferHit 102 # number of redundant prefetches already in prefetch queue 921system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 922system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 923system.cpu.l2cache.prefetcher.pfSpanPage 28085 # number of prefetches not generated due to page crossing 924system.cpu.l2cache.tags.replacements 0 # number of replacements 925system.cpu.l2cache.tags.tagsinuse 5603.177963 # Cycle average of tags in use 926system.cpu.l2cache.tags.total_refs 3041133 # Total number of references to valid blocks. 927system.cpu.l2cache.tags.sampled_refs 6750 # Sample count of references to valid blocks. 928system.cpu.l2cache.tags.avg_refs 450.538222 # Average number of references to valid blocks. 929system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 930system.cpu.l2cache.tags.occ_blocks::writebacks 5495.535708 # Average occupied blocks per requestor 931system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 107.642255 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_percent::writebacks 0.335421 # Average percentage of cache occupancy 933system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006570 # Average percentage of cache occupancy 934system.cpu.l2cache.tags.occ_percent::total 0.341991 # Average percentage of cache occupancy 935system.cpu.l2cache.tags.occ_task_id_blocks::1022 497 # Occupied blocks per task id 936system.cpu.l2cache.tags.occ_task_id_blocks::1024 6253 # Occupied blocks per task id 937system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id 938system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id 939system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id 940system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id 941system.cpu.l2cache.tags.age_task_id_blocks_1022::4 113 # Occupied blocks per task id 942system.cpu.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 943system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id 945system.cpu.l2cache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id 946system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5048 # Occupied blocks per task id 947system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030334 # Percentage of cache occupancy per task id 948system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381653 # Percentage of cache occupancy per task id 949system.cpu.l2cache.tags.tag_accesses 69530063 # Number of tag accesses 950system.cpu.l2cache.tags.data_accesses 69530063 # Number of data accesses 951system.cpu.l2cache.WritebackDirty_hits::writebacks 968360 # number of WritebackDirty hits 952system.cpu.l2cache.WritebackDirty_hits::total 968360 # number of WritebackDirty hits 953system.cpu.l2cache.WritebackClean_hits::writebacks 1046226 # number of WritebackClean hits 954system.cpu.l2cache.WritebackClean_hits::total 1046226 # number of WritebackClean hits 955system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 956system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 957system.cpu.l2cache.ReadExReq_hits::cpu.data 219964 # number of ReadExReq hits 958system.cpu.l2cache.ReadExReq_hits::total 219964 # number of ReadExReq hits 959system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 716938 # number of ReadCleanReq hits 960system.cpu.l2cache.ReadCleanReq_hits::total 716938 # number of ReadCleanReq hits 961system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1251135 # number of ReadSharedReq hits 962system.cpu.l2cache.ReadSharedReq_hits::total 1251135 # number of ReadSharedReq hits 963system.cpu.l2cache.demand_hits::cpu.inst 716938 # number of demand (read+write) hits 964system.cpu.l2cache.demand_hits::cpu.data 1471099 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::total 2188037 # number of demand (read+write) hits 966system.cpu.l2cache.overall_hits::cpu.inst 716938 # number of overall hits 967system.cpu.l2cache.overall_hits::cpu.data 1471099 # number of overall hits 968system.cpu.l2cache.overall_hits::total 2188037 # number of overall hits 969system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses 970system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses 971system.cpu.l2cache.ReadExReq_misses::cpu.data 781 # number of ReadExReq misses 972system.cpu.l2cache.ReadExReq_misses::total 781 # number of ReadExReq misses 973system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 9708 # number of ReadCleanReq misses 974system.cpu.l2cache.ReadCleanReq_misses::total 9708 # number of ReadCleanReq misses 975system.cpu.l2cache.ReadSharedReq_misses::cpu.data 71587 # number of ReadSharedReq misses 976system.cpu.l2cache.ReadSharedReq_misses::total 71587 # number of ReadSharedReq misses 977system.cpu.l2cache.demand_misses::cpu.inst 9708 # number of demand (read+write) misses 978system.cpu.l2cache.demand_misses::cpu.data 72368 # number of demand (read+write) misses 979system.cpu.l2cache.demand_misses::total 82076 # number of demand (read+write) misses 980system.cpu.l2cache.overall_misses::cpu.inst 9708 # number of overall misses 981system.cpu.l2cache.overall_misses::cpu.data 72368 # number of overall misses 982system.cpu.l2cache.overall_misses::total 82076 # number of overall misses 983system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 40000 # number of UpgradeReq miss cycles 984system.cpu.l2cache.UpgradeReq_miss_latency::total 40000 # number of UpgradeReq miss cycles 985system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56104500 # number of ReadExReq miss cycles 986system.cpu.l2cache.ReadExReq_miss_latency::total 56104500 # number of ReadExReq miss cycles 987system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 688634000 # number of ReadCleanReq miss cycles 988system.cpu.l2cache.ReadCleanReq_miss_latency::total 688634000 # number of ReadCleanReq miss cycles 989system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5061315000 # number of ReadSharedReq miss cycles 990system.cpu.l2cache.ReadSharedReq_miss_latency::total 5061315000 # number of ReadSharedReq miss cycles 991system.cpu.l2cache.demand_miss_latency::cpu.inst 688634000 # number of demand (read+write) miss cycles 992system.cpu.l2cache.demand_miss_latency::cpu.data 5117419500 # number of demand (read+write) miss cycles 993system.cpu.l2cache.demand_miss_latency::total 5806053500 # number of demand (read+write) miss cycles 994system.cpu.l2cache.overall_miss_latency::cpu.inst 688634000 # number of overall miss cycles 995system.cpu.l2cache.overall_miss_latency::cpu.data 5117419500 # number of overall miss cycles 996system.cpu.l2cache.overall_miss_latency::total 5806053500 # number of overall miss cycles 997system.cpu.l2cache.WritebackDirty_accesses::writebacks 968360 # number of WritebackDirty accesses(hits+misses) 998system.cpu.l2cache.WritebackDirty_accesses::total 968360 # number of WritebackDirty accesses(hits+misses) 999system.cpu.l2cache.WritebackClean_accesses::writebacks 1046226 # number of WritebackClean accesses(hits+misses) 1000system.cpu.l2cache.WritebackClean_accesses::total 1046226 # number of WritebackClean accesses(hits+misses) 1001system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) 1002system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) 1003system.cpu.l2cache.ReadExReq_accesses::cpu.data 220745 # number of ReadExReq accesses(hits+misses) 1004system.cpu.l2cache.ReadExReq_accesses::total 220745 # number of ReadExReq accesses(hits+misses) 1005system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726646 # number of ReadCleanReq accesses(hits+misses) 1006system.cpu.l2cache.ReadCleanReq_accesses::total 726646 # number of ReadCleanReq accesses(hits+misses) 1007system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1322722 # number of ReadSharedReq accesses(hits+misses) 1008system.cpu.l2cache.ReadSharedReq_accesses::total 1322722 # number of ReadSharedReq accesses(hits+misses) 1009system.cpu.l2cache.demand_accesses::cpu.inst 726646 # number of demand (read+write) accesses 1010system.cpu.l2cache.demand_accesses::cpu.data 1543467 # number of demand (read+write) accesses 1011system.cpu.l2cache.demand_accesses::total 2270113 # number of demand (read+write) accesses 1012system.cpu.l2cache.overall_accesses::cpu.inst 726646 # number of overall (read+write) accesses 1013system.cpu.l2cache.overall_accesses::cpu.data 1543467 # number of overall (read+write) accesses 1014system.cpu.l2cache.overall_accesses::total 2270113 # number of overall (read+write) accesses 1015system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.928571 # miss rate for UpgradeReq accesses 1016system.cpu.l2cache.UpgradeReq_miss_rate::total 0.928571 # miss rate for UpgradeReq accesses 1017system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003538 # miss rate for ReadExReq accesses 1018system.cpu.l2cache.ReadExReq_miss_rate::total 0.003538 # miss rate for ReadExReq accesses 1019system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013360 # miss rate for ReadCleanReq accesses 1020system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013360 # miss rate for ReadCleanReq accesses 1021system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.054121 # miss rate for ReadSharedReq accesses 1022system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.054121 # miss rate for ReadSharedReq accesses 1023system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013360 # miss rate for demand accesses 1024system.cpu.l2cache.demand_miss_rate::cpu.data 0.046887 # miss rate for demand accesses 1025system.cpu.l2cache.demand_miss_rate::total 0.036155 # miss rate for demand accesses 1026system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013360 # miss rate for overall accesses 1027system.cpu.l2cache.overall_miss_rate::cpu.data 0.046887 # miss rate for overall accesses 1028system.cpu.l2cache.overall_miss_rate::total 0.036155 # miss rate for overall accesses 1029system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3076.923077 # average UpgradeReq miss latency 1030system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3076.923077 # average UpgradeReq miss latency 1031system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71836.747759 # average ReadExReq miss latency 1032system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71836.747759 # average ReadExReq miss latency 1033system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70934.693037 # average ReadCleanReq miss latency 1034system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70934.693037 # average ReadCleanReq miss latency 1035system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70701.593865 # average ReadSharedReq miss latency 1036system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70701.593865 # average ReadSharedReq miss latency 1037system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency 1038system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency 1039system.cpu.l2cache.demand_avg_miss_latency::total 70739.966616 # average overall miss latency 1040system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70934.693037 # average overall miss latency 1041system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70713.844517 # average overall miss latency 1042system.cpu.l2cache.overall_avg_miss_latency::total 70739.966616 # average overall miss latency 1043system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1044system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1045system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1046system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1047system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1048system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1049system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 51 # number of ReadExReq MSHR hits 1050system.cpu.l2cache.ReadExReq_mshr_hits::total 51 # number of ReadExReq MSHR hits 1051system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits 1052system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits 1053system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits 1054system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits 1055system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 1056system.cpu.l2cache.demand_mshr_hits::cpu.data 85 # number of demand (read+write) MSHR hits 1057system.cpu.l2cache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits 1058system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits 1059system.cpu.l2cache.overall_mshr_hits::cpu.data 85 # number of overall MSHR hits 1060system.cpu.l2cache.overall_mshr_hits::total 97 # number of overall MSHR hits 1061system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51651 # number of HardPFReq MSHR misses 1062system.cpu.l2cache.HardPFReq_mshr_misses::total 51651 # number of HardPFReq MSHR misses 1063system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses 1064system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses 1065system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 730 # number of ReadExReq MSHR misses 1066system.cpu.l2cache.ReadExReq_mshr_misses::total 730 # number of ReadExReq MSHR misses 1067system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9696 # number of ReadCleanReq MSHR misses 1068system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9696 # number of ReadCleanReq MSHR misses 1069system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 71553 # number of ReadSharedReq MSHR misses 1070system.cpu.l2cache.ReadSharedReq_mshr_misses::total 71553 # number of ReadSharedReq MSHR misses 1071system.cpu.l2cache.demand_mshr_misses::cpu.inst 9696 # number of demand (read+write) MSHR misses 1072system.cpu.l2cache.demand_mshr_misses::cpu.data 72283 # number of demand (read+write) MSHR misses 1073system.cpu.l2cache.demand_mshr_misses::total 81979 # number of demand (read+write) MSHR misses 1074system.cpu.l2cache.overall_mshr_misses::cpu.inst 9696 # number of overall MSHR misses 1075system.cpu.l2cache.overall_mshr_misses::cpu.data 72283 # number of overall MSHR misses 1076system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51651 # number of overall MSHR misses 1077system.cpu.l2cache.overall_mshr_misses::total 133630 # number of overall MSHR misses 1078system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of HardPFReq MSHR miss cycles 1079system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 178131300 # number of HardPFReq MSHR miss cycles 1080system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 187000 # number of UpgradeReq MSHR miss cycles 1081system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 187000 # number of UpgradeReq MSHR miss cycles 1082system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50303500 # number of ReadExReq MSHR miss cycles 1083system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50303500 # number of ReadExReq MSHR miss cycles 1084system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 629910500 # number of ReadCleanReq MSHR miss cycles 1085system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 629910500 # number of ReadCleanReq MSHR miss cycles 1086system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4630072500 # number of ReadSharedReq MSHR miss cycles 1087system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4630072500 # number of ReadSharedReq MSHR miss cycles 1088system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 629910500 # number of demand (read+write) MSHR miss cycles 1089system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4680376000 # number of demand (read+write) MSHR miss cycles 1090system.cpu.l2cache.demand_mshr_miss_latency::total 5310286500 # number of demand (read+write) MSHR miss cycles 1091system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 629910500 # number of overall MSHR miss cycles 1092system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4680376000 # number of overall MSHR miss cycles 1093system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 178131300 # number of overall MSHR miss cycles 1094system.cpu.l2cache.overall_mshr_miss_latency::total 5488417800 # number of overall MSHR miss cycles 1095system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1096system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1097system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.928571 # mshr miss rate for UpgradeReq accesses 1098system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.928571 # mshr miss rate for UpgradeReq accesses 1099system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003307 # mshr miss rate for ReadExReq accesses 1100system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003307 # mshr miss rate for ReadExReq accesses 1101system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for ReadCleanReq accesses 1102system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013343 # mshr miss rate for ReadCleanReq accesses 1103system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054095 # mshr miss rate for ReadSharedReq accesses 1104system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054095 # mshr miss rate for ReadSharedReq accesses 1105system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for demand accesses 1106system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for demand accesses 1107system.cpu.l2cache.demand_mshr_miss_rate::total 0.036112 # mshr miss rate for demand accesses 1108system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013343 # mshr miss rate for overall accesses 1109system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.046832 # mshr miss rate for overall accesses 1110system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1111system.cpu.l2cache.overall_mshr_miss_rate::total 0.058865 # mshr miss rate for overall accesses 1112system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average HardPFReq mshr miss latency 1113system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3448.748330 # average HardPFReq mshr miss latency 1114system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385 # average UpgradeReq mshr miss latency 1115system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385 # average UpgradeReq mshr miss latency 1116system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110 # average ReadExReq mshr miss latency 1117system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110 # average ReadExReq mshr miss latency 1118system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914 # average ReadCleanReq mshr miss latency 1119system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914 # average ReadCleanReq mshr miss latency 1120system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153 # average ReadSharedReq mshr miss latency 1121system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153 # average ReadSharedReq mshr miss latency 1122system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency 1123system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency 1124system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485 # average overall mshr miss latency 1125system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914 # average overall mshr miss latency 1126system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936 # average overall mshr miss latency 1127system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3448.748330 # average overall mshr miss latency 1128system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859 # average overall mshr miss latency 1129system.cpu.toL2Bus.snoop_filter.tot_requests 4539362 # Total number of requests made to the snoop filter. 1130system.cpu.toL2Bus.snoop_filter.hit_single_requests 2269187 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1131system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1132system.cpu.toL2Bus.snoop_filter.tot_snoops 130262 # Total number of snoops made to the snoop filter. 1133system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52910 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1134system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77352 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1135system.cpu.toL2Bus.trans_dist::ReadResp 2049447 # Transaction distribution 1136system.cpu.toL2Bus.trans_dist::WritebackDirty 968360 # Transaction distribution 1137system.cpu.toL2Bus.trans_dist::WritebackClean 1300796 # Transaction distribution 1138system.cpu.toL2Bus.trans_dist::CleanEvict 81249 # Transaction distribution 1139system.cpu.toL2Bus.trans_dist::HardPFReq 53022 # Transaction distribution 1140system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution 1141system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution 1142system.cpu.toL2Bus.trans_dist::ReadExReq 220745 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::ReadExResp 220745 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::ReadCleanReq 726725 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322722 # Transaction distribution 1146system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2179572 # Packet count per connected master and slave (bytes) 1147system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629917 # Packet count per connected master and slave (bytes) 1148system.cpu.toL2Bus.pkt_count::total 6809489 # Packet count per connected master and slave (bytes) 1149system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92982208 # Cumulative packet size per connected master and slave (bytes) 1150system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197531008 # Cumulative packet size per connected master and slave (bytes) 1151system.cpu.toL2Bus.pkt_size::total 290513216 # Cumulative packet size per connected master and slave (bytes) 1152system.cpu.toL2Bus.snoops 134350 # Total snoops (count) 1153system.cpu.toL2Bus.snoop_fanout::samples 2404477 # Request fanout histogram 1154system.cpu.toL2Bus.snoop_fanout::mean 0.192237 # Request fanout histogram 1155system.cpu.toL2Bus.snoop_fanout::stdev 0.468638 # Request fanout histogram 1156system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1157system.cpu.toL2Bus.snoop_fanout::0 2019600 83.99% 83.99% # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::1 307525 12.79% 96.78% # Request fanout histogram 1159system.cpu.toL2Bus.snoop_fanout::2 77352 3.22% 100.00% # Request fanout histogram 1160system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::total 2404477 # Request fanout histogram 1164system.cpu.toL2Bus.reqLayer0.occupancy 4538837000 # Layer occupancy (ticks) 1165system.cpu.toL2Bus.reqLayer0.utilization 4.1 # Layer utilization (%) 1166system.cpu.toL2Bus.respLayer0.occupancy 1090392888 # Layer occupancy (ticks) 1167system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 1168system.cpu.toL2Bus.respLayer1.occupancy 2315538337 # Layer occupancy (ticks) 1169system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) 1170system.membus.trans_dist::ReadResp 83887 # Transaction distribution 1171system.membus.trans_dist::UpgradeReq 13 # Transaction distribution 1172system.membus.trans_dist::ReadExReq 730 # Transaction distribution 1173system.membus.trans_dist::ReadExResp 730 # Transaction distribution 1174system.membus.trans_dist::ReadSharedReq 83887 # Transaction distribution 1175system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169247 # Packet count per connected master and slave (bytes) 1176system.membus.pkt_count::total 169247 # Packet count per connected master and slave (bytes) 1177system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5415488 # Cumulative packet size per connected master and slave (bytes) 1178system.membus.pkt_size::total 5415488 # Cumulative packet size per connected master and slave (bytes) 1179system.membus.snoops 0 # Total snoops (count) 1180system.membus.snoop_fanout::samples 84630 # Request fanout histogram 1181system.membus.snoop_fanout::mean 0 # Request fanout histogram 1182system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1183system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1184system.membus.snoop_fanout::0 84630 100.00% 100.00% # Request fanout histogram 1185system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1186system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1187system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1188system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1189system.membus.snoop_fanout::total 84630 # Request fanout histogram 1190system.membus.reqLayer0.occupancy 108151910 # Layer occupancy (ticks) 1191system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 1192system.membus.respLayer1.occupancy 445724357 # Layer occupancy (ticks) 1193system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 1194 1195---------- End Simulation Statistics ---------- 1196