stats.txt revision 10798
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 310726Sandreas.hansson@arm.comsim_seconds 0.112554 # Number of seconds simulated 410726Sandreas.hansson@arm.comsim_ticks 112553814500 # Number of ticks simulated 510726Sandreas.hansson@arm.comfinal_tick 112553814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710798Ssteve.reinhardt@amd.comhost_inst_rate 123079 # Simulator instruction rate (inst/s) 810798Ssteve.reinhardt@amd.comhost_op_rate 147770 # Simulator op (including micro ops) rate (op/s) 910798Ssteve.reinhardt@amd.comhost_tick_rate 50736526 # Simulator tick rate (ticks/s) 1010798Ssteve.reinhardt@amd.comhost_mem_usage 257068 # Number of bytes of host memory used 1110798Ssteve.reinhardt@amd.comhost_seconds 2218.40 # Real time elapsed on the host 1210409Sandreas.hansson@arm.comsim_insts 273037219 # Number of instructions simulated 1310409Sandreas.hansson@arm.comsim_ops 327811601 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 187136 # Number of bytes read from this memory 1710726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 114176 # Number of bytes read from this memory 1810726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 167616 # Number of bytes read from this memory 1910726Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 468928 # Number of bytes read from this memory 2010726Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 187136 # Number of instructions bytes read from this memory 2110726Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 187136 # Number of instructions bytes read from this memory 2210726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 2924 # Number of read requests responded to by this memory 2310726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1784 # Number of read requests responded to by this memory 2410726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 2619 # Number of read requests responded to by this memory 2510726Sandreas.hansson@arm.comsystem.physmem.num_reads::total 7327 # Number of read requests responded to by this memory 2610726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1662636 # Total read bandwidth from this memory (bytes/s) 2710726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 1014413 # Total read bandwidth from this memory (bytes/s) 2810726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 1489208 # Total read bandwidth from this memory (bytes/s) 2910726Sandreas.hansson@arm.comsystem.physmem.bw_read::total 4166256 # Total read bandwidth from this memory (bytes/s) 3010726Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1662636 # Instruction read bandwidth from this memory (bytes/s) 3110726Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1662636 # Instruction read bandwidth from this memory (bytes/s) 3210726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1662636 # Total bandwidth to/from this memory (bytes/s) 3310726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 1014413 # Total bandwidth to/from this memory (bytes/s) 3410726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 1489208 # Total bandwidth to/from this memory (bytes/s) 3510726Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4166256 # Total bandwidth to/from this memory (bytes/s) 3610726Sandreas.hansson@arm.comsystem.physmem.readReqs 7327 # Number of read requests accepted 379978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3810726Sandreas.hansson@arm.comsystem.physmem.readBursts 7327 # Number of DRAM read bursts, including those serviced by the write queue 399978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 4010726Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 468928 # Total number of bytes read from DRAM 419978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 429978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4310726Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 468928 # Total read bytes from the system interface side 449978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 459978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 469978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4710409Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write 4810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 589 # Per bank write bursts 4910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 789 # Per bank write bursts 5010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 601 # Per bank write bursts 5110726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 520 # Per bank write bursts 5210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 444 # Per bank write bursts 5310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 346 # Per bank write bursts 5410628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 153 # Per bank write bursts 5510726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 255 # Per bank write bursts 5610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 219 # Per bank write bursts 5710726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 290 # Per bank write bursts 5810726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 315 # Per bank write bursts 5910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 411 # Per bank write bursts 6010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 547 # Per bank write bursts 6110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 678 # Per bank write bursts 6210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 615 # Per bank write bursts 6310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 555 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 789978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 799978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 809978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 819978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8210726Sandreas.hansson@arm.comsystem.physmem.totGap 112553656000 # Total gap between requests 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8910726Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 7327 # Read request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 969978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9710726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 3994 # What read queue length does an incoming req see 9810726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see 9910726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 473 # What read queue length does an incoming req see 10010726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see 10110726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 246 # What read queue length does an incoming req see 10210726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 203 # What read queue length does an incoming req see 10310726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see 10410726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 150 # What read queue length does an incoming req see 10510726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 184 # What read queue length does an incoming req see 10610726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see 10710726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see 10810726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see 10910726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see 11010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see 11110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19310726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1397 # Bytes accessed per row activation 19410726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 334.064424 # Bytes accessed per row activation 19510726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 193.482672 # Bytes accessed per row activation 19610726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 348.087808 # Bytes accessed per row activation 19710726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 504 36.08% 36.08% # Bytes accessed per row activation 19810726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 315 22.55% 58.63% # Bytes accessed per row activation 19910726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 145 10.38% 69.01% # Bytes accessed per row activation 20010726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 78 5.58% 74.59% # Bytes accessed per row activation 20110726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 51 3.65% 78.24% # Bytes accessed per row activation 20210726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 45 3.22% 81.46% # Bytes accessed per row activation 20310726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 28 2.00% 83.46% # Bytes accessed per row activation 20410726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 21 1.50% 84.97% # Bytes accessed per row activation 20510726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 210 15.03% 100.00% # Bytes accessed per row activation 20610726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1397 # Bytes accessed per row activation 20710726Sandreas.hansson@arm.comsystem.physmem.totQLat 96387273 # Total ticks spent queuing 20810726Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 233768523 # Total ticks spent from burst creation until serviced by the DRAM 20910726Sandreas.hansson@arm.comsystem.physmem.totBusLat 36635000 # Total ticks spent in databus transfers 21010726Sandreas.hansson@arm.comsystem.physmem.avgQLat 13155.08 # Average queueing delay per DRAM burst 2119978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 21210726Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 31905.08 # Average memory access latency per DRAM burst 21310628Sandreas.hansson@arm.comsystem.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s 2149978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21510628Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s 2169978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2179978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21810628Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 21910628Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 2209978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 22110726Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing 2229978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22310726Sandreas.hansson@arm.comsystem.physmem.readRowHits 5921 # Number of row buffer hits during reads 2249312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22510726Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads 2269312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22710726Sandreas.hansson@arm.comsystem.physmem.avgGap 15361492.56 # Average gap between requests 22810726Sandreas.hansson@arm.comsystem.physmem.pageHitRate 80.81 # Row buffer hit rate, read and write combined 22910726Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) 23010726Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) 23110628Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) 23210628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23310726Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) 23410726Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 3253381020 # Energy for active background per rank (pJ) 23510726Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 64676459250 # Energy for precharge background per rank (pJ) 23610726Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 75317311980 # Total energy per rank (pJ) 23710726Sandreas.hansson@arm.comsystem.physmem_0.averagePower 669.186805 # Core power per rank (mW) 23810726Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 107592163396 # Time in different power states 23910726Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states 24010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 24110726Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 1200480604 # Time in different power states 24210628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 24310726Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) 24410726Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) 24510726Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 28158000 # Energy for read commands per rank (pJ) 24610628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24710726Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) 24810726Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 3298234320 # Energy for active background per rank (pJ) 24910726Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 64637123250 # Energy for precharge background per rank (pJ) 25010726Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 75323490750 # Total energy per rank (pJ) 25110726Sandreas.hansson@arm.comsystem.physmem_1.averagePower 669.241613 # Core power per rank (mW) 25210726Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 107525247142 # Time in different power states 25310726Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states 25410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25510726Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 1266984612 # Time in different power states 25610628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25710726Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 37745757 # Number of BP lookups 25810726Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 20165080 # Number of conditional branches predicted 25910726Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 1746215 # Number of conditional branches incorrect 26010726Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 18666199 # Number of BTB lookups 26110726Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 17299874 # Number of BTB hits 26210628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26310726Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 92.680218 # BTB Hit Percentage 26410726Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 7225607 # Number of times the RAS was used to get a target. 26510726Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. 26610036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 26810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 26910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 27010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 27110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 27210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 27310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 27710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 27810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 27910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 28010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 28110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 28710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 28810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 28910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 29310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 29610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 29710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 29910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3048317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3058317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3068317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3078317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3088317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3098317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3107860SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3117860SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3127860SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3138317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3148317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3158317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3168317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3178317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3188317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3198317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3208317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3218317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3227860SN/Asystem.cpu.dtb.hits 0 # DTB hits 3237860SN/Asystem.cpu.dtb.misses 0 # DTB misses 3248317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 32510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 32610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 32810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 32910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 33610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 33710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 33810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 33910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 34710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 34910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 35510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3628317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3638317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3648317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3658317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3668317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3678317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3688317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 3698317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3708317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3718317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3728317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3738317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3748317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3758317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3768317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3778317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3788317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3798317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 3808317SN/Asystem.cpu.itb.hits 0 # DTB hits 3818317SN/Asystem.cpu.itb.misses 0 # DTB misses 3828317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 3838317SN/Asystem.cpu.workload.num_syscalls 191 # Number of system calls 38410726Sandreas.hansson@arm.comsystem.cpu.numCycles 225107630 # number of cpu cycles simulated 3858317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3868317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38710726Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 12251626 # Number of cycles fetch is stalled on an Icache miss 38810726Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 334050460 # Number of instructions fetch has processed 38910726Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 37745757 # Number of branches that fetch encountered 39010726Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 24525481 # Number of branches that fetch has predicted taken 39110726Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 210773788 # Number of cycles fetch has run and was not squashing or blocked 39210726Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 3510701 # Number of cycles fetch has spent squashing 39310726Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 1259 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 39410726Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 2425 # Number of stall cycles due to full MSHR 39510726Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 89095014 # Number of cache lines fetched 39610726Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 21830 # Number of outstanding Icache misses that were squashed 39710726Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 224784448 # Number of instructions fetched each cycle (Total) 39810726Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.802641 # Number of instructions fetched each cycle (Total) 39910726Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.228554 # Number of instructions fetched each cycle (Total) 4007860SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 40110726Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 51100209 22.73% 22.73% # Number of instructions fetched each cycle (Total) 40210726Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 42897495 19.08% 41.82% # Number of instructions fetched each cycle (Total) 40310726Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 30052167 13.37% 55.19% # Number of instructions fetched each cycle (Total) 40410726Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 100734577 44.81% 100.00% # Number of instructions fetched each cycle (Total) 4057860SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4067860SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 40710409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 40810726Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 224784448 # Number of instructions fetched each cycle (Total) 40910726Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.167679 # Number of branch fetches per cycle 41010726Sandreas.hansson@arm.comsystem.cpu.fetch.rate 1.483959 # Number of inst fetches per cycle 41110726Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 27670459 # Number of cycles decode is idle 41210726Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 63847459 # Number of cycles decode is blocked 41310726Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 108576617 # Number of cycles decode is running 41410726Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 23069322 # Number of cycles decode is unblocking 41510726Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1620591 # Number of cycles decode is squashing 41610726Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 6880031 # Number of times decode resolved a branch 41710726Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction 41810726Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 363530052 # Number of instructions handled by decode 41910726Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 6167703 # Number of squashed instructions handled by decode 42010726Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1620591 # Number of cycles rename is squashing 42110726Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 44985233 # Number of cycles rename is idle 42210726Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 17899875 # Number of cycles rename is blocking 42310726Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 341878 # count of cycles rename stalled for serializing inst 42410726Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 113387886 # Number of cycles rename is running 42510726Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 46548985 # Number of cycles rename is unblocking 42610726Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 355747640 # Number of instructions processed by rename 42710726Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 2899285 # Number of squashed instructions processed by rename 42810726Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 6598470 # Number of times rename has blocked due to ROB full 42910726Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 195112 # Number of times rename has blocked due to IQ full 43010726Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 7751940 # Number of times rename has blocked due to LQ full 43110726Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 21223571 # Number of times rename has blocked due to SQ full 43210726Sandreas.hansson@arm.comsystem.cpu.rename.FullRegisterEvents 2892429 # Number of times there has been no free registers 43310726Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 403401871 # Number of destination operands rename has renamed 43410726Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 2533892950 # Number of register rename lookups that rename has made 43510726Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 350207607 # Number of integer rename lookups 43610726Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 194891234 # Number of floating rename lookups 43710409Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed 43810726Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 31171820 # Number of HB maps that are undone due to squashing 43910726Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 17015 # count of serializing insts renamed 44010726Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed 44110726Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 55320329 # count of insts added to the skid buffer 44210726Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 92416671 # Number of loads inserted to the mem dependence unit. 44310726Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 88482299 # Number of stores inserted to the mem dependence unit. 44410726Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1659115 # Number of conflicting loads. 44510726Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 1844729 # Number of conflicting stores. 44610726Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 353235129 # Number of instructions added to the IQ (excludes non-spec) 44710726Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ 44810726Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 346404668 # Number of instructions issued 44910726Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 2300304 # Number of squashed instructions issued 45010798Ssteve.reinhardt@amd.comsystem.cpu.iq.iqSquashedInstsExamined 25451552 # Number of squashed instructions iterated over during squash; mainly for profiling 45110726Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 73599170 # Number of squashed operands that are examined and possibly removed from graph 45210726Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed 45310726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 224784448 # Number of insts issued each cycle 45410726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.541053 # Number of insts issued each cycle 45510726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.099675 # Number of insts issued each cycle 4568317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 45710726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 40431348 17.99% 17.99% # Number of insts issued each cycle 45810726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 78272117 34.82% 52.81% # Number of insts issued each cycle 45910726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 61035980 27.15% 79.96% # Number of insts issued each cycle 46010726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 34788778 15.48% 95.44% # Number of insts issued each cycle 46110726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 9595638 4.27% 99.71% # Number of insts issued each cycle 46210726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 651817 0.29% 100.00% # Number of insts issued each cycle 46310726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 8770 0.00% 100.00% # Number of insts issued each cycle 46410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 46510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 4668317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4678317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 46810409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 46910726Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 224784448 # Number of insts issued each cycle 4708241SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 47110726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 9471276 7.62% 7.62% # attempts to use FU when none available 47210726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 7330 0.01% 7.63% # attempts to use FU when none available 47310726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available 47410726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available 47510726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available 47610726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available 47710726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available 47810726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available 47910726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available 48010726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available 48110726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available 48210726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available 48310726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available 48410726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available 48510726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available 48610726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available 48710726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available 48810726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available 48910726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available 49010726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available 49110726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 257049 0.21% 7.83% # attempts to use FU when none available 49210726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available 49310726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 126990 0.10% 7.94% # attempts to use FU when none available 49410726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 92940 0.07% 8.01% # attempts to use FU when none available 49510726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 68000 0.05% 8.06% # attempts to use FU when none available 49610726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 719474 0.58% 8.64% # attempts to use FU when none available 49710726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 316340 0.25% 8.90% # attempts to use FU when none available 49810726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 682824 0.55% 9.45% # attempts to use FU when none available 49910726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available 50010726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 53604156 43.13% 52.57% # attempts to use FU when none available 50110726Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 58946138 47.43% 100.00% # attempts to use FU when none available 5028241SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5038241SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5048317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 50510726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 110656025 31.94% 31.94% # Type of FU issued 50610726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 2148357 0.62% 32.56% # Type of FU issued 50710726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued 50810726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued 50910726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued 51010726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued 51110726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued 51210726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued 51310726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued 51410726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued 51510726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued 51610726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued 51710726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued 51810726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued 51910726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued 52010726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued 52110726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued 52210726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued 52310726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued 52410726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued 52510726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 6798490 1.96% 34.53% # Type of FU issued 52610726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued 52710726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 8668315 2.50% 37.03% # Type of FU issued 52810726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 3332477 0.96% 37.99% # Type of FU issued 52910726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 1592461 0.46% 38.45% # Type of FU issued 53010726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 20930112 6.04% 44.49% # Type of FU issued 53110726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 7182294 2.07% 46.57% # Type of FU issued 53210726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 7148952 2.06% 48.63% # Type of FU issued 53310726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued 53410726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 91886799 26.53% 75.21% # Type of FU issued 53510726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 85885100 24.79% 100.00% # Type of FU issued 5368317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5378317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 53810726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 346404668 # Type of FU issued 53910726Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.538840 # Inst issue rate 54010726Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 124292517 # FU busy when requested 54110726Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.358807 # FU busy rate (busy events/executed inst) 54210726Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 756686876 # Number of integer instruction queue reads 54310798Ssteve.reinhardt@amd.comsystem.cpu.iq.int_inst_queue_writes 251708205 # Number of integer instruction queue writes 54410726Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 223263085 # Number of integer instruction queue wakeup accesses 54510726Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 287499729 # Number of floating instruction queue reads 54610798Ssteve.reinhardt@amd.comsystem.cpu.iq.fp_inst_queue_writes 127016687 # Number of floating instruction queue writes 54710726Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 117424806 # Number of floating instruction queue wakeup accesses 54810726Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 303164482 # Number of integer alu accesses 54910726Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 167532703 # Number of floating point alu accesses 55010726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 5066223 # Number of loads that had data forwarded from stores 5518317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 55210726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 6684396 # Number of loads squashed 55310726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 13685 # Number of memory responses ignored because the instruction is squashed 55410726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10191 # Number of memory ordering violations 55510726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 6106682 # Number of stores squashed 5568317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5578317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 55810726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 154303 # Number of loads that were rescheduled 55910726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 567640 # Number of times an access to memory failed due to the cache being blocked 5608317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 56110726Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1620591 # Number of cycles IEW is squashing 56210726Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 2121620 # Number of cycles IEW is blocking 56310726Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 330440 # Number of cycles IEW is unblocking 56410726Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 353264020 # Number of instructions dispatched to IQ 56510409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 56610726Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 92416671 # Number of dispatched load instructions 56710726Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 88482299 # Number of dispatched store instructions 56810726Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions 56910726Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 8046 # Number of times the IQ has become full, causing a stall 57010726Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 336925 # Number of times the LSQ has become full, causing a stall 57110726Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 10191 # Number of memory order violations 57210726Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 1220622 # Number of branches that were predicted taken incorrectly 57310726Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 439103 # Number of branches that were predicted not taken incorrectly 57410726Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 1659725 # Number of branch mispredicts detected at execute 57510726Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 342414286 # Number of executed instructions 57610726Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 90666955 # Number of load instructions executed 57710726Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 3990382 # Number of squashed instructions skipped in execute 5788317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 57910726Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 867 # number of nop insts executed 58010726Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 175255989 # number of memory reference insts executed 58110726Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 31752931 # Number of branches executed 58210726Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 84589034 # Number of stores executed 58310726Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.521114 # Inst execution rate 58410726Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 340946352 # cumulative count of insts sent to commit 58510726Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 340687891 # cumulative count of insts written-back 58610726Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 153731206 # num instructions producing a value 58710726Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 266896125 # num instructions consuming a value 5888317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 58910726Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.513444 # insts written-back per cycle 59010726Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.575996 # average fanout of values written-back 5918317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 59210726Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 23077118 # The number of squashed insts skipped by commit 5939459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 59410726Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 1611456 # The number of times a branch was mispredicted 59510726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 221059297 # Number of insts commited each cycle 59610726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.482915 # Number of insts commited each cycle 59710726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.052167 # Number of insts commited each cycle 5988317SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 59910726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 87356112 39.52% 39.52% # Number of insts commited each cycle 60010726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 70369552 31.83% 71.35% # Number of insts commited each cycle 60110726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 20804455 9.41% 80.76% # Number of insts commited each cycle 60210726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 13442204 6.08% 86.84% # Number of insts commited each cycle 60310726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 8808979 3.98% 90.83% # Number of insts commited each cycle 60410726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 4514912 2.04% 92.87% # Number of insts commited each cycle 60510726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 2991653 1.35% 94.22% # Number of insts commited each cycle 60610726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 2424695 1.10% 95.32% # Number of insts commited each cycle 60710726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 10346735 4.68% 100.00% # Number of insts commited each cycle 6088317SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6098317SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6108317SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 61110726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 221059297 # Number of insts commited each cycle 61210409Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 273037831 # Number of instructions committed 61310409Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed 6148317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 61510409Sandreas.hansson@arm.comsystem.cpu.commit.refs 168107892 # Number of memory references committed 61610409Sandreas.hansson@arm.comsystem.cpu.commit.loads 85732275 # Number of loads committed 6178317SN/Asystem.cpu.commit.membars 11033 # Number of memory barriers committed 61810409Sandreas.hansson@arm.comsystem.cpu.commit.branches 30563525 # Number of branches committed 6198317SN/Asystem.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 62010409Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 258331704 # Number of committed integer instructions. 62110409Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 6225114 # Number of function calls committed. 62210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 62310409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction 62410409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction 62510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 62610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 62710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 62810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 62910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction 63010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction 63110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction 63210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction 63310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction 63410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction 63510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction 63610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction 63710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction 63810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction 63910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction 64010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction 64110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction 64210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction 64310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction 64410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction 64510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction 64610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction 64710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction 64810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction 64910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 65010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 65110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 65210409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 65310409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 65410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 65510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 65610409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 327812213 # Class of committed instruction 65710726Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached 65810726Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 561599370 # The number of ROB reads 65910726Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 705507733 # The number of ROB writes 66010726Sandreas.hansson@arm.comsystem.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself 66110726Sandreas.hansson@arm.comsystem.cpu.idleCycles 323182 # Total number of cycles that the CPU has spent unscheduled due to idling 66210409Sandreas.hansson@arm.comsystem.cpu.committedInsts 273037219 # Number of Instructions Simulated 66310409Sandreas.hansson@arm.comsystem.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated 66410726Sandreas.hansson@arm.comsystem.cpu.cpi 0.824458 # CPI: Cycles Per Instruction 66510726Sandreas.hansson@arm.comsystem.cpu.cpi_total 0.824458 # CPI: Total CPI of All Threads 66610726Sandreas.hansson@arm.comsystem.cpu.ipc 1.212919 # IPC: Instructions Per Cycle 66710726Sandreas.hansson@arm.comsystem.cpu.ipc_total 1.212919 # IPC: Total IPC of All Threads 66810726Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 331300708 # number of integer regfile reads 66910726Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 136940215 # number of integer regfile writes 67010726Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 187107289 # number of floating regfile reads 67110726Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 132177847 # number of floating regfile writes 67210726Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 1297030245 # number of cc regfile reads 67310726Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 80242169 # number of cc regfile writes 67410726Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 1182847920 # number of misc regfile reads 6759459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 67610726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1533856 # number of replacements 67710726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.843197 # Cycle average of tags in use 67810726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 163689216 # Total number of references to valid blocks. 67910726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks. 68010726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 106.681849 # Average number of references to valid blocks. 68110726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 83394000 # Cycle when the warmup percentage was hit. 68210726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.843197 # Average occupied blocks per requestor 68310726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy 68410726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy 68510409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 68610726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 68710628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 68810726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id 68910409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 69010409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 69110726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 336633502 # Number of tag accesses 69210726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 336633502 # Number of data accesses 69310726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 82631348 # number of ReadReq hits 69410726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 82631348 # number of ReadReq hits 69510726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 80965582 # number of WriteReq hits 69610726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 80965582 # number of WriteReq hits 69710726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 70480 # number of SoftPFReq hits 69810726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 70480 # number of SoftPFReq hits 69910726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits 70010726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits 7019459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 7029459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 70310726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 163596930 # number of demand (read+write) hits 70410726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 163596930 # number of demand (read+write) hits 70510726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 163667410 # number of overall hits 70610726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 163667410 # number of overall hits 70710726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 2773213 # number of ReadReq misses 70810726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 2773213 # number of ReadReq misses 70910726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1087117 # number of WriteReq misses 71010726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1087117 # number of WriteReq misses 71110726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses 71210726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses 71310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses 71410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses 71510726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3860330 # number of demand (read+write) misses 71610726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3860330 # number of demand (read+write) misses 71710726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3860348 # number of overall misses 71810726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3860348 # number of overall misses 71910726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 22349106216 # number of ReadReq miss cycles 72010726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 22349106216 # number of ReadReq miss cycles 72110726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 8902471046 # number of WriteReq miss cycles 72210726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 8902471046 # number of WriteReq miss cycles 72310726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles 72410726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles 72510726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 31251577262 # number of demand (read+write) miss cycles 72610726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 31251577262 # number of demand (read+write) miss cycles 72710726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 31251577262 # number of overall miss cycles 72810726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 31251577262 # number of overall miss cycles 72910726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 85404561 # number of ReadReq accesses(hits+misses) 73010726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 85404561 # number of ReadReq accesses(hits+misses) 73110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 73210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) 73310726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 70498 # number of SoftPFReq accesses(hits+misses) 73410726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 70498 # number of SoftPFReq accesses(hits+misses) 73510726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) 73610726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) 7379459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 7389459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 73910726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 167457260 # number of demand (read+write) accesses 74010726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 167457260 # number of demand (read+write) accesses 74110726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 167527758 # number of overall (read+write) accesses 74210726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 167527758 # number of overall (read+write) accesses 74310726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032471 # miss rate for ReadReq accesses 74410726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.032471 # miss rate for ReadReq accesses 74510726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses 74610726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses 74710726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses 74810726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses 74910409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses 75010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses 75110726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses 75210726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses 75310726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses 75410726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses 75510726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8058.921625 # average ReadReq miss latency 75610726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 8058.921625 # average ReadReq miss latency 75710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8189.064329 # average WriteReq miss latency 75810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 8189.064329 # average WriteReq miss latency 75910726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency 76010726Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency 76110726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 8095.571431 # average overall miss latency 76210726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 8095.571431 # average overall miss latency 76310726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 8095.533683 # average overall miss latency 76410726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 8095.533683 # average overall miss latency 76510628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 76610726Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 918314 # number of cycles access was blocked 76710628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 76810726Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 117385 # number of cycles access was blocked 76910628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 77010726Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 7.823095 # average number of cycles each access was blocked 7719449SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 7729449SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 77310726Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 966341 # number of writebacks 77410726Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 966341 # number of writebacks 77510726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459499 # number of ReadReq MSHR hits 77610726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 1459499 # number of ReadReq MSHR hits 77710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 866472 # number of WriteReq MSHR hits 77810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 866472 # number of WriteReq MSHR hits 77910409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits 78010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits 78110726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2325971 # number of demand (read+write) MSHR hits 78210726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2325971 # number of demand (read+write) MSHR hits 78310726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2325971 # number of overall MSHR hits 78410726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2325971 # number of overall MSHR hits 78510726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses 78610726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses 78710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses 78810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses 78910409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 79010409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses 79110726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses 79210726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses 79310726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses 79410726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses 79510726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9969290033 # number of ReadReq MSHR miss cycles 79610726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 9969290033 # number of ReadReq MSHR miss cycles 79710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717345064 # number of WriteReq MSHR miss cycles 79810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1717345064 # number of WriteReq MSHR miss cycles 79910726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1161750 # number of SoftPFReq MSHR miss cycles 80010726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1161750 # number of SoftPFReq MSHR miss cycles 80110726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686635097 # number of demand (read+write) MSHR miss cycles 80210726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 11686635097 # number of demand (read+write) MSHR miss cycles 80310726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 11687796847 # number of overall MSHR miss cycles 80410726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 11687796847 # number of overall MSHR miss cycles 80510726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses 80610726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses 80710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses 80810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses 80910409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses 81010409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses 81110726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses 81210726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses 81310726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses 81410726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses 81510726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7588.630427 # average ReadReq mshr miss latency 81610726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7588.630427 # average ReadReq mshr miss latency 81710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7783.294722 # average WriteReq mshr miss latency 81810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7783.294722 # average WriteReq mshr miss latency 81910726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 105613.636364 # average SoftPFReq mshr miss latency 82010726Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 105613.636364 # average SoftPFReq mshr miss latency 82110726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7616.623683 # average overall mshr miss latency 82210726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 7616.623683 # average overall mshr miss latency 82310726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7617.326230 # average overall mshr miss latency 82410726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 7617.326230 # average overall mshr miss latency 8259449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 82610726Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 715719 # number of replacements 82710726Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.828705 # Cycle average of tags in use 82810726Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 88373879 # Total number of references to valid blocks. 82910726Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 716231 # Sample count of references to valid blocks. 83010726Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 123.387397 # Average number of references to valid blocks. 83110726Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 326261250 # Cycle when the warmup percentage was hit. 83210726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.828705 # Average occupied blocks per requestor 83310726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999665 # Average percentage of cache occupancy 83410726Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999665 # Average percentage of cache occupancy 83510628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 83610628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 83710726Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 83810726Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id 83910726Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 84010726Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id 84110628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 84210726Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 178906226 # Number of tag accesses 84310726Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 178906226 # Number of data accesses 84410726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 88373879 # number of ReadReq hits 84510726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 88373879 # number of ReadReq hits 84610726Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 88373879 # number of demand (read+write) hits 84710726Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 88373879 # number of demand (read+write) hits 84810726Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 88373879 # number of overall hits 84910726Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 88373879 # number of overall hits 85010726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 721118 # number of ReadReq misses 85110726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 721118 # number of ReadReq misses 85210726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 721118 # number of demand (read+write) misses 85310726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 721118 # number of demand (read+write) misses 85410726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 721118 # number of overall misses 85510726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 721118 # number of overall misses 85610726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 5972962690 # number of ReadReq miss cycles 85710726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 5972962690 # number of ReadReq miss cycles 85810726Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 5972962690 # number of demand (read+write) miss cycles 85910726Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 5972962690 # number of demand (read+write) miss cycles 86010726Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 5972962690 # number of overall miss cycles 86110726Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 5972962690 # number of overall miss cycles 86210726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 89094997 # number of ReadReq accesses(hits+misses) 86310726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 89094997 # number of ReadReq accesses(hits+misses) 86410726Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 89094997 # number of demand (read+write) accesses 86510726Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 89094997 # number of demand (read+write) accesses 86610726Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 89094997 # number of overall (read+write) accesses 86710726Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 89094997 # number of overall (read+write) accesses 86810726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses 86910726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses 87010726Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses 87110726Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses 87210726Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses 87310726Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses 87410726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8282.919980 # average ReadReq miss latency 87510726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 8282.919980 # average ReadReq miss latency 87610726Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency 87710726Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 8282.919980 # average overall miss latency 87810726Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency 87910726Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 8282.919980 # average overall miss latency 88010726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 60262 # number of cycles access was blocked 88110726Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked 88210726Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 2026 # number of cycles access was blocked 88310628Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked 88410726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 29.744324 # average number of cycles each access was blocked 88510726Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked 88610628Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 88710628Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 88810726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits 88910726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits 89010726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits 89110726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits 89210726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits 89310726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits 89410726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 716232 # number of ReadReq MSHR misses 89510726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 716232 # number of ReadReq MSHR misses 89610726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 716232 # number of demand (read+write) MSHR misses 89710726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 716232 # number of demand (read+write) MSHR misses 89810726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 716232 # number of overall MSHR misses 89910726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 716232 # number of overall MSHR misses 90010726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5192936459 # number of ReadReq MSHR miss cycles 90110726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 5192936459 # number of ReadReq MSHR miss cycles 90210726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 5192936459 # number of demand (read+write) MSHR miss cycles 90310726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 5192936459 # number of demand (read+write) MSHR miss cycles 90410726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 5192936459 # number of overall MSHR miss cycles 90510726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 5192936459 # number of overall MSHR miss cycles 90610726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses 90710726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses 90810726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses 90910726Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses 91010726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses 91110726Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses 91210726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7250.355275 # average ReadReq mshr miss latency 91310726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7250.355275 # average ReadReq mshr miss latency 91410726Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency 91510726Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency 91610726Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency 91710726Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency 91810628Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 91910726Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 404550 # number of hwpf issued 92010726Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 404804 # number of prefetch candidates identified 92110726Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 188 # number of redundant prefetches already in prefetch queue 92210628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 92310628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 92410726Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 28140 # number of prefetches not generated due to page crossing 92510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 92610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 5993.813794 # Cycle average of tags in use 92710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2806615 # Total number of references to valid blocks. 92810726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 7301 # Sample count of references to valid blocks. 92910726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 384.415149 # Average number of references to valid blocks. 93010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93110726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 2575.149913 # Average occupied blocks per requestor 93210726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2681.614006 # Average occupied blocks per requestor 93310726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 610.589138 # Average occupied blocks per requestor 93410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 126.460737 # Average occupied blocks per requestor 93510726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.157175 # Average percentage of cache occupancy 93610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.163673 # Average percentage of cache occupancy 93710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.037267 # Average percentage of cache occupancy 93810726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007719 # Average percentage of cache occupancy 93910726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.365833 # Average percentage of cache occupancy 94010726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 517 # Occupied blocks per task id 94110726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 6784 # Occupied blocks per task id 94210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id 94310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id 94410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id 94510726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 135 # Occupied blocks per task id 94610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 94710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 94810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 775 # Occupied blocks per task id 94910726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 126 # Occupied blocks per task id 95010726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 5743 # Occupied blocks per task id 95110726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.031555 # Percentage of cache occupancy per task id 95210726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.414062 # Percentage of cache occupancy per task id 95310726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 51684538 # Number of tag accesses 95410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 51684538 # Number of data accesses 95510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 712391 # number of ReadReq hits 95610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 1312672 # number of ReadReq hits 95710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2025063 # number of ReadReq hits 95810726Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 966341 # number of Writeback hits 95910726Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 966341 # number of Writeback hits 96010628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 96110628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 96210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 219831 # number of ReadExReq hits 96310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 219831 # number of ReadExReq hits 96410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 712391 # number of demand (read+write) hits 96510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1532503 # number of demand (read+write) hits 96610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2244894 # number of demand (read+write) hits 96710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 712391 # number of overall hits 96810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1532503 # number of overall hits 96910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2244894 # number of overall hits 97010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 2935 # number of ReadReq misses 97110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 1053 # number of ReadReq misses 97210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 3988 # number of ReadReq misses 97310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 97410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 97510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 812 # number of ReadExReq misses 97610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 812 # number of ReadExReq misses 97710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2935 # number of demand (read+write) misses 97810726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1865 # number of demand (read+write) misses 97910726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 4800 # number of demand (read+write) misses 98010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2935 # number of overall misses 98110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1865 # number of overall misses 98210726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 4800 # number of overall misses 98310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200800474 # number of ReadReq miss cycles 98410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 76846248 # number of ReadReq miss cycles 98510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 277646722 # number of ReadReq miss cycles 98610726Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles 98710726Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles 98810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57691250 # number of ReadExReq miss cycles 98910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 57691250 # number of ReadExReq miss cycles 99010726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 200800474 # number of demand (read+write) miss cycles 99110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 134537498 # number of demand (read+write) miss cycles 99210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 335337972 # number of demand (read+write) miss cycles 99310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 200800474 # number of overall miss cycles 99410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 134537498 # number of overall miss cycles 99510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 335337972 # number of overall miss cycles 99610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 715326 # number of ReadReq accesses(hits+misses) 99710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1313725 # number of ReadReq accesses(hits+misses) 99810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2029051 # number of ReadReq accesses(hits+misses) 99910726Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 966341 # number of Writeback accesses(hits+misses) 100010726Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 966341 # number of Writeback accesses(hits+misses) 100110628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 100210628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 100310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 220643 # number of ReadExReq accesses(hits+misses) 100410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 220643 # number of ReadExReq accesses(hits+misses) 100510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 715326 # number of demand (read+write) accesses 100610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1534368 # number of demand (read+write) accesses 100710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2249694 # number of demand (read+write) accesses 100810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 715326 # number of overall (read+write) accesses 100910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1534368 # number of overall (read+write) accesses 101010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2249694 # number of overall (read+write) accesses 101110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004103 # miss rate for ReadReq accesses 101210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000802 # miss rate for ReadReq accesses 101310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.001965 # miss rate for ReadReq accesses 101410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 101510628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses 101610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003680 # miss rate for ReadExReq accesses 101710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.003680 # miss rate for ReadExReq accesses 101810726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.004103 # miss rate for demand accesses 101910726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.001215 # miss rate for demand accesses 102010726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.002134 # miss rate for demand accesses 102110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.004103 # miss rate for overall accesses 102210726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.001215 # miss rate for overall accesses 102310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.002134 # miss rate for overall accesses 102410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68415.834412 # average ReadReq miss latency 102510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72978.393162 # average ReadReq miss latency 102610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 69620.542126 # average ReadReq miss latency 102710726Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23499 # average UpgradeReq miss latency 102810726Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23499 # average UpgradeReq miss latency 102910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71048.337438 # average ReadExReq miss latency 103010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 71048.337438 # average ReadExReq miss latency 103110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency 103210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency 103310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 69862.077500 # average overall miss latency 103410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency 103510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency 103610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 69862.077500 # average overall miss latency 103710628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 103810628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 103910628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 104010628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 104110628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 104210628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 104310628Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 104410628Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 104510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 104610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits 104710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits 104810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 47 # number of ReadExReq MSHR hits 104910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 47 # number of ReadExReq MSHR hits 105010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 105110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits 105210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits 105310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 105410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits 105510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 92 # number of overall MSHR hits 105610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2924 # number of ReadReq MSHR misses 105710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1019 # number of ReadReq MSHR misses 105810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 3943 # number of ReadReq MSHR misses 105910726Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30395 # number of HardPFReq MSHR misses 106010726Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 30395 # number of HardPFReq MSHR misses 106110628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 106210628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 106310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 765 # number of ReadExReq MSHR misses 106410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 765 # number of ReadExReq MSHR misses 106510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2924 # number of demand (read+write) MSHR misses 106610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1784 # number of demand (read+write) MSHR misses 106710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 4708 # number of demand (read+write) MSHR misses 106810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2924 # number of overall MSHR misses 106910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1784 # number of overall MSHR misses 107010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30395 # number of overall MSHR misses 107110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 35103 # number of overall MSHR misses 107210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175338026 # number of ReadReq MSHR miss cycles 107310726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 66096002 # number of ReadReq MSHR miss cycles 107410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 241434028 # number of ReadReq MSHR miss cycles 107510726Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of HardPFReq MSHR miss cycles 107610726Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 176500042 # number of HardPFReq MSHR miss cycles 107710726Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14001 # number of UpgradeReq MSHR miss cycles 107810726Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14001 # number of UpgradeReq MSHR miss cycles 107910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49863251 # number of ReadExReq MSHR miss cycles 108010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49863251 # number of ReadExReq MSHR miss cycles 108110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175338026 # number of demand (read+write) MSHR miss cycles 108210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115959253 # number of demand (read+write) MSHR miss cycles 108310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 291297279 # number of demand (read+write) MSHR miss cycles 108410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175338026 # number of overall MSHR miss cycles 108510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115959253 # number of overall MSHR miss cycles 108610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of overall MSHR miss cycles 108710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 467797321 # number of overall MSHR miss cycles 108810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for ReadReq accesses 108910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000776 # mshr miss rate for ReadReq accesses 109010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001943 # mshr miss rate for ReadReq accesses 109110628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 109210628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 109310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 109410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 109510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003467 # mshr miss rate for ReadExReq accesses 109610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003467 # mshr miss rate for ReadExReq accesses 109710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for demand accesses 109810726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for demand accesses 109910726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.002093 # mshr miss rate for demand accesses 110010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for overall accesses 110110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for overall accesses 110210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 110310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.015603 # mshr miss rate for overall accesses 110410726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59965.125171 # average ReadReq mshr miss latency 110510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64863.593719 # average ReadReq mshr miss latency 110610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61231.049455 # average ReadReq mshr miss latency 110710726Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average HardPFReq mshr miss latency 110810726Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5806.877513 # average HardPFReq mshr miss latency 110910726Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency 111010726Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency 111110726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65180.720261 # average ReadExReq mshr miss latency 111210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65180.720261 # average ReadExReq mshr miss latency 111310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency 111410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency 111510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 61872.829014 # average overall mshr miss latency 111610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency 111710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency 111810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average overall mshr miss latency 111910726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 13326.419993 # average overall mshr miss latency 112010628Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 112110726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2029957 # Transaction distribution 112210726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2029957 # Transaction distribution 112310726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution 112410726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 31800 # Transaction distribution 112510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 112610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 112710726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution 112810726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution 112910726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431558 # Packet count per connected master and slave (bytes) 113010726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes) 113110726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 5466639 # Packet count per connected master and slave (bytes) 113210726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780864 # Cumulative packet size per connected master and slave (bytes) 113310726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes) 113410726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 205826240 # Cumulative packet size per connected master and slave (bytes) 113510726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 32706 # Total snoops (count) 113610726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 3248743 # Request fanout histogram 113710726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 3.009788 # Request fanout histogram 113810726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.098451 # Request fanout histogram 113910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 114010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 114110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 114210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 114310726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 3216943 99.02% 99.02% # Request fanout histogram 114410726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 31800 0.98% 100.00% # Request fanout histogram 114510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 114610726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 114710726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 114810726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 3248743 # Request fanout histogram 114910726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2574812500 # Layer occupancy (ticks) 115010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) 115110726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1075185997 # Layer occupancy (ticks) 115210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 115310726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2301792968 # Layer occupancy (ticks) 115410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) 115510726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 6562 # Transaction distribution 115610726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 6562 # Transaction distribution 115710628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 1 # Transaction distribution 115810628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 1 # Transaction distribution 115910726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 765 # Transaction distribution 116010726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 765 # Transaction distribution 116110726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes) 116210726Sandreas.hansson@arm.comsystem.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes) 116310726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468928 # Cumulative packet size per connected master and slave (bytes) 116410726Sandreas.hansson@arm.comsystem.membus.pkt_size::total 468928 # Cumulative packet size per connected master and slave (bytes) 116510628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 116610726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 7328 # Request fanout histogram 116710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 116810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 116910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 117010726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 7328 100.00% 100.00% # Request fanout histogram 117110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 117210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 117310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 117410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 117510726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 7328 # Request fanout histogram 117610726Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 9247379 # Layer occupancy (ticks) 117710628Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 117810726Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 38369962 # Layer occupancy (ticks) 117910726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.0 # Layer utilization (%) 11807860SN/A 11817860SN/A---------- End Simulation Statistics ---------- 1182