stats.txt revision 10515
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 0.112541 # Number of seconds simulated 410409Sandreas.hansson@arm.comsim_ticks 112540655000 # Number of ticks simulated 510409Sandreas.hansson@arm.comfinal_tick 112540655000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710433Sandreas.hansson@arm.comhost_inst_rate 132153 # Simulator instruction rate (inst/s) 810433Sandreas.hansson@arm.comhost_op_rate 158665 # Simulator op (including micro ops) rate (op/s) 910433Sandreas.hansson@arm.comhost_tick_rate 54470958 # Simulator tick rate (ticks/s) 1010433Sandreas.hansson@arm.comhost_mem_usage 270904 # Number of bytes of host memory used 1110433Sandreas.hansson@arm.comhost_seconds 2066.07 # Real time elapsed on the host 1210409Sandreas.hansson@arm.comsim_insts 273037219 # Number of instructions simulated 1310409Sandreas.hansson@arm.comsim_ops 327811601 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 30592 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 80768 # Number of bytes read from this memory 1810409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 512320 # Number of bytes read from this memory 1910409Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 623680 # Number of bytes read from this memory 2010409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 30592 # Number of instructions bytes read from this memory 2110409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 30592 # Number of instructions bytes read from this memory 2210409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 478 # Number of read requests responded to by this memory 2310409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1262 # Number of read requests responded to by this memory 2410409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 8005 # Number of read requests responded to by this memory 2510409Sandreas.hansson@arm.comsystem.physmem.num_reads::total 9745 # Number of read requests responded to by this memory 2610409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 271831 # Total read bandwidth from this memory (bytes/s) 2710409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 717678 # Total read bandwidth from this memory (bytes/s) 2810409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 4552310 # Total read bandwidth from this memory (bytes/s) 2910409Sandreas.hansson@arm.comsystem.physmem.bw_read::total 5541820 # Total read bandwidth from this memory (bytes/s) 3010409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 271831 # Instruction read bandwidth from this memory (bytes/s) 3110409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 271831 # Instruction read bandwidth from this memory (bytes/s) 3210409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 271831 # Total bandwidth to/from this memory (bytes/s) 3310409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 717678 # Total bandwidth to/from this memory (bytes/s) 3410409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 4552310 # Total bandwidth to/from this memory (bytes/s) 3510409Sandreas.hansson@arm.comsystem.physmem.bw_total::total 5541820 # Total bandwidth to/from this memory (bytes/s) 3610409Sandreas.hansson@arm.comsystem.physmem.readReqs 9745 # Number of read requests accepted 379978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3810409Sandreas.hansson@arm.comsystem.physmem.readBursts 9745 # Number of DRAM read bursts, including those serviced by the write queue 399978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 4010409Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 623680 # Total number of bytes read from DRAM 419978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 429978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4310409Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 623680 # Total read bytes from the system interface side 449978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 459978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 469978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4710409Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write 4810409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 803 # Per bank write bursts 4910409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 999 # Per bank write bursts 5010409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 769 # Per bank write bursts 5110409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 645 # Per bank write bursts 5210409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 618 # Per bank write bursts 5310409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 484 # Per bank write bursts 5410409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 251 # Per bank write bursts 5510409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 363 # Per bank write bursts 5610409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 300 # Per bank write bursts 5710409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 432 # Per bank write bursts 5810409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 486 # Per bank write bursts 5910409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 534 # Per bank write bursts 6010409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 696 # Per bank write bursts 6110409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 850 # Per bank write bursts 6210409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 782 # Per bank write bursts 6310409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 733 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 789978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 799978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 809978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 819978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8210409Sandreas.hansson@arm.comsystem.physmem.totGap 112540488500 # Total gap between requests 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8910409Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 9745 # Read request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 969978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9710409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 2266 # What read queue length does an incoming req see 9810409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 1763 # What read queue length does an incoming req see 9910409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 1065 # What read queue length does an incoming req see 10010409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 847 # What read queue length does an incoming req see 10110409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 758 # What read queue length does an incoming req see 10210409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 667 # What read queue length does an incoming req see 10310409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 627 # What read queue length does an incoming req see 10410409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 603 # What read queue length does an incoming req see 10510409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 528 # What read queue length does an incoming req see 10610409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 248 # What read queue length does an incoming req see 10710409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 140 # What read queue length does an incoming req see 10810409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 95 # What read queue length does an incoming req see 10910409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 46 # What read queue length does an incoming req see 11010409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 36 # What read queue length does an incoming req see 11110409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 31 # What read queue length does an incoming req see 11210409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 25 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19310409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1235 # Bytes accessed per row activation 19410409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 501.635628 # Bytes accessed per row activation 19510409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 310.924046 # Bytes accessed per row activation 19610409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 394.932906 # Bytes accessed per row activation 19710409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 290 23.48% 23.48% # Bytes accessed per row activation 19810409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 197 15.95% 39.43% # Bytes accessed per row activation 19910409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 103 8.34% 47.77% # Bytes accessed per row activation 20010409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 73 5.91% 53.68% # Bytes accessed per row activation 20110409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 78 6.32% 60.00% # Bytes accessed per row activation 20210409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 75 6.07% 66.07% # Bytes accessed per row activation 20310409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 32 2.59% 68.66% # Bytes accessed per row activation 20410409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 38 3.08% 71.74% # Bytes accessed per row activation 20510409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 349 28.26% 100.00% # Bytes accessed per row activation 20610409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1235 # Bytes accessed per row activation 20710409Sandreas.hansson@arm.comsystem.physmem.totQLat 248191131 # Total ticks spent queuing 20810409Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 430909881 # Total ticks spent from burst creation until serviced by the DRAM 20910409Sandreas.hansson@arm.comsystem.physmem.totBusLat 48725000 # Total ticks spent in databus transfers 21010409Sandreas.hansson@arm.comsystem.physmem.avgQLat 25468.56 # Average queueing delay per DRAM burst 2119978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 21210409Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 44218.56 # Average memory access latency per DRAM burst 21310409Sandreas.hansson@arm.comsystem.physmem.avgRdBW 5.54 # Average DRAM read bandwidth in MiByte/s 2149978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21510409Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 5.54 # Average system read bandwidth in MiByte/s 2169978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2179978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21810409Sandreas.hansson@arm.comsystem.physmem.busUtil 0.04 # Data bus utilization in percentage 21910409Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads 2209978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 22110409Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing 2229978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22310409Sandreas.hansson@arm.comsystem.physmem.readRowHits 8500 # Number of row buffer hits during reads 2249312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22510409Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 87.22 # Row buffer hit rate for reads 2269312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22710409Sandreas.hansson@arm.comsystem.physmem.avgGap 11548536.53 # Average gap between requests 22810409Sandreas.hansson@arm.comsystem.physmem.pageHitRate 87.22 # Row buffer hit rate, read and write combined 22910409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 107209849499 # Time in different power states 23010409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 3757780000 # Time in different power states 23110220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 23210409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 1567991501 # Time in different power states 23310220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 23410433Sandreas.hansson@arm.comsystem.physmem.actEnergy::0 4460400 # Energy for activate commands per rank (pJ) 23510433Sandreas.hansson@arm.comsystem.physmem.actEnergy::1 4845960 # Energy for activate commands per rank (pJ) 23610433Sandreas.hansson@arm.comsystem.physmem.preEnergy::0 2433750 # Energy for precharge commands per rank (pJ) 23710433Sandreas.hansson@arm.comsystem.physmem.preEnergy::1 2644125 # Energy for precharge commands per rank (pJ) 23810433Sandreas.hansson@arm.comsystem.physmem.readEnergy::0 38220000 # Energy for read commands per rank (pJ) 23910433Sandreas.hansson@arm.comsystem.physmem.readEnergy::1 37221600 # Energy for read commands per rank (pJ) 24010433Sandreas.hansson@arm.comsystem.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 24110433Sandreas.hansson@arm.comsystem.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 24210433Sandreas.hansson@arm.comsystem.physmem.refreshEnergy::0 7350217680 # Energy for refresh commands per rank (pJ) 24310433Sandreas.hansson@arm.comsystem.physmem.refreshEnergy::1 7350217680 # Energy for refresh commands per rank (pJ) 24410433Sandreas.hansson@arm.comsystem.physmem.actBackEnergy::0 3071428470 # Energy for active background per rank (pJ) 24510433Sandreas.hansson@arm.comsystem.physmem.actBackEnergy::1 3094710975 # Energy for active background per rank (pJ) 24610433Sandreas.hansson@arm.comsystem.physmem.preBackEnergy::0 64826723250 # Energy for precharge background per rank (pJ) 24710433Sandreas.hansson@arm.comsystem.physmem.preBackEnergy::1 64806300000 # Energy for precharge background per rank (pJ) 24810433Sandreas.hansson@arm.comsystem.physmem.totalEnergy::0 75293483550 # Total energy per rank (pJ) 24910433Sandreas.hansson@arm.comsystem.physmem.totalEnergy::1 75295940340 # Total energy per rank (pJ) 25010433Sandreas.hansson@arm.comsystem.physmem.averagePower::0 669.067664 # Core power per rank (mW) 25110433Sandreas.hansson@arm.comsystem.physmem.averagePower::1 669.089495 # Core power per rank (mW) 25210409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 9170 # Transaction distribution 25310409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 9170 # Transaction distribution 25410409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 1 # Transaction distribution 25510409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 1 # Transaction distribution 25610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 575 # Transaction distribution 25710409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 575 # Transaction distribution 25810409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 19492 # Packet count per connected master and slave (bytes) 25910409Sandreas.hansson@arm.comsystem.membus.pkt_count::total 19492 # Packet count per connected master and slave (bytes) 26010409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 623680 # Cumulative packet size per connected master and slave (bytes) 26110409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 623680 # Cumulative packet size per connected master and slave (bytes) 26210409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 26310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 9746 # Request fanout histogram 26410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 26510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 26610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 26710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 9746 100.00% 100.00% # Request fanout histogram 26810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 26910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 27010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 27110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 27210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 9746 # Request fanout histogram 27310409Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 11064261 # Layer occupancy (ticks) 2749729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 27510409Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 88934700 # Layer occupancy (ticks) 2769729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 27710036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 27810409Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 37763717 # Number of BP lookups 27910409Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 20179624 # Number of conditional branches predicted 28010409Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 1746237 # Number of conditional branches incorrect 28110409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 18664531 # Number of BTB lookups 28210409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 17302092 # Number of BTB hits 2839481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 28410409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 92.700384 # BTB Hit Percentage 28510409Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 7228871 # Number of times the RAS was used to get a target. 28610409Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. 28710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 28810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 28910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 29010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 29110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 29210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 29310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 29410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 29510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 29610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 29710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 29810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 29910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 30010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 30110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 30210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 30310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 30410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 30510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 30610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 30710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3088317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3098317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3108317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3118317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3128317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3138317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3147860SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3157860SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3167860SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3178317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3188317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3198317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3208317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3218317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3228317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3238317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3248317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3258317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3267860SN/Asystem.cpu.dtb.hits 0 # DTB hits 3277860SN/Asystem.cpu.dtb.misses 0 # DTB misses 3288317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 32910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 33110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 33210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 33310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 33410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 33510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 33610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 33710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 34110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 34210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 34310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 34510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 34610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 34710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 34810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 34910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3508317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3518317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3528317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3538317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3548317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3558317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3568317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 3578317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3588317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3598317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3608317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3618317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3628317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3638317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3648317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3658317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3668317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3678317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 3688317SN/Asystem.cpu.itb.hits 0 # DTB hits 3698317SN/Asystem.cpu.itb.misses 0 # DTB misses 3708317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 3718317SN/Asystem.cpu.workload.num_syscalls 191 # Number of system calls 37210409Sandreas.hansson@arm.comsystem.cpu.numCycles 225081311 # number of cpu cycles simulated 3738317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3748317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 37510409Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 12228964 # Number of cycles fetch is stalled on an Icache miss 37610409Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 334152318 # Number of instructions fetch has processed 37710409Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 37763717 # Number of branches that fetch encountered 37810409Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 24530963 # Number of branches that fetch has predicted taken 37910409Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 210956137 # Number of cycles fetch has run and was not squashing or blocked 38010488Snilay@cs.wisc.edusystem.cpu.fetch.SquashCycles 3511517 # Number of cycles fetch has spent squashing 38110409Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 38210409Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps 38310409Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 514 # Number of stall cycles due to full MSHR 38410409Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 89111612 # Number of cache lines fetched 38510409Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 21313 # Number of outstanding Icache misses that were squashed 38610409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 224941514 # Number of instructions fetched each cycle (Total) 38710409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.801835 # Number of instructions fetched each cycle (Total) 38810409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.228393 # Number of instructions fetched each cycle (Total) 3897860SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 39010409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 51202945 22.76% 22.76% # Number of instructions fetched each cycle (Total) 39110409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 42808370 19.03% 41.79% # Number of instructions fetched each cycle (Total) 39210409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 30291484 13.47% 55.26% # Number of instructions fetched each cycle (Total) 39310409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 100638715 44.74% 100.00% # Number of instructions fetched each cycle (Total) 3947860SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3957860SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 39610409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 39710409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 224941514 # Number of instructions fetched each cycle (Total) 39810409Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.167778 # Number of branch fetches per cycle 39910409Sandreas.hansson@arm.comsystem.cpu.fetch.rate 1.484585 # Number of inst fetches per cycle 40010409Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 27726149 # Number of cycles decode is idle 40110409Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 64007988 # Number of cycles decode is blocked 40210409Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 108311612 # Number of cycles decode is running 40310409Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 23274772 # Number of cycles decode is unblocking 40410409Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1620993 # Number of cycles decode is squashing 40510409Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 6880386 # Number of times decode resolved a branch 40610409Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 135232 # Number of times decode detected a branch misprediction 40710409Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 363491063 # Number of instructions handled by decode 40810409Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 6273375 # Number of squashed instructions handled by decode 40910409Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1620993 # Number of cycles rename is squashing 41010409Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 45185790 # Number of cycles rename is idle 41110409Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 13191872 # Number of cycles rename is blocking 41210409Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 337791 # count of cycles rename stalled for serializing inst 41310409Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 113472399 # Number of cycles rename is running 41410409Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 51132669 # Number of cycles rename is unblocking 41510409Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 355733781 # Number of instructions processed by rename 41610409Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 2913620 # Number of squashed instructions processed by rename 41710409Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 6683703 # Number of times rename has blocked due to ROB full 41810409Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 151097 # Number of times rename has blocked due to IQ full 41910409Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 7653475 # Number of times rename has blocked due to LQ full 42010409Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 21162184 # Number of times rename has blocked due to SQ full 42110409Sandreas.hansson@arm.comsystem.cpu.rename.FullRegisterEvents 7934136 # Number of times there has been no free registers 42210409Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 403386511 # Number of destination operands rename has renamed 42310409Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 2533827094 # Number of register rename lookups that rename has made 42410409Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 350198229 # Number of integer rename lookups 42510409Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 194873795 # Number of floating rename lookups 42610409Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed 42710409Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 31156460 # Number of HB maps that are undone due to squashing 42810409Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 17017 # count of serializing insts renamed 42910409Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 17054 # count of temporary serializing insts renamed 43010409Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 55398119 # count of insts added to the skid buffer 43110409Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 92429190 # Number of loads inserted to the mem dependence unit. 43210409Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 88465233 # Number of stores inserted to the mem dependence unit. 43310409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1673754 # Number of conflicting loads. 43410409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 1845335 # Number of conflicting stores. 43510409Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 353207304 # Number of instructions added to the IQ (excludes non-spec) 43610409Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ 43710409Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 346267862 # Number of instructions issued 43810409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 2344729 # Number of squashed instructions issued 43910409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 24807728 # Number of squashed instructions iterated over during squash; mainly for profiling 44010409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 73571108 # Number of squashed operands that are examined and possibly removed from graph 44110409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed 44210409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 224941514 # Number of insts issued each cycle 44310409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.539368 # Number of insts issued each cycle 44410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.101787 # Number of insts issued each cycle 4458317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 44610409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 40716883 18.10% 18.10% # Number of insts issued each cycle 44710409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 78348178 34.83% 52.93% # Number of insts issued each cycle 44810409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 60751241 27.01% 79.94% # Number of insts issued each cycle 44910409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 34738398 15.44% 95.38% # Number of insts issued each cycle 45010409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 9740749 4.33% 99.71% # Number of insts issued each cycle 45110409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 637378 0.28% 100.00% # Number of insts issued each cycle 45210409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 8687 0.00% 100.00% # Number of insts issued each cycle 45310409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 45410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 4558317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4568317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 45710409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 45810409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 224941514 # Number of insts issued each cycle 4598241SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 46010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 9315738 7.51% 7.51% # attempts to use FU when none available 46110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 7336 0.01% 7.52% # attempts to use FU when none available 46210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available 46310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available 46410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available 46510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available 46610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available 46710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available 46810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available 46910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available 47010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available 47110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available 47210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available 47310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available 47410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available 47510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available 47610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available 47710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available 47810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available 47910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available 48010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 233465 0.19% 7.70% # attempts to use FU when none available 48110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available 48210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 152519 0.12% 7.83% # attempts to use FU when none available 48310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 103426 0.08% 7.91% # attempts to use FU when none available 48410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available 48510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 820096 0.66% 8.60% # attempts to use FU when none available 48610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 318386 0.26% 8.86% # attempts to use FU when none available 48710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 687826 0.55% 9.41% # attempts to use FU when none available 48810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available 48910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 53407084 43.05% 52.46% # attempts to use FU when none available 49010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 58973857 47.54% 100.00% # attempts to use FU when none available 4918241SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4928241SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4938317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 49410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 110648843 31.95% 31.95% # Type of FU issued 49510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 2148167 0.62% 32.58% # Type of FU issued 49610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued 49710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued 49810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued 49910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued 50010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued 50110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued 50210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued 50310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued 50410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued 50510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued 50610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued 50710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued 50810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued 50910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued 51010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued 51110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued 51210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued 51310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued 51410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 6796997 1.96% 34.54% # Type of FU issued 51510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued 51610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 8667397 2.50% 37.04% # Type of FU issued 51710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 3331873 0.96% 38.00% # Type of FU issued 51810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 1592437 0.46% 38.46% # Type of FU issued 51910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 20937214 6.05% 44.51% # Type of FU issued 52010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 7180794 2.07% 46.58% # Type of FU issued 52110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 7147102 2.06% 48.65% # Type of FU issued 52210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued 52310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 91783348 26.51% 75.20% # Type of FU issued 52410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 85858404 24.80% 100.00% # Type of FU issued 5258317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5268317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 52710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 346267862 # Type of FU issued 52810409Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.538412 # Inst issue rate 52910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 124056913 # FU busy when requested 53010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.358269 # FU busy rate (busy events/executed inst) 53110409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 756613481 # Number of integer instruction queue reads 53210409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 251259921 # Number of integer instruction queue writes 53310409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 223227498 # Number of integer instruction queue wakeup accesses 53410409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 287265399 # Number of floating instruction queue reads 53510409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 126793827 # Number of floating instruction queue writes 53610409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 117417697 # Number of floating instruction queue wakeup accesses 53710409Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 302953956 # Number of integer alu accesses 53810409Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 167370819 # Number of floating point alu accesses 53910409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 5034316 # Number of loads that had data forwarded from stores 5408317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 54110409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 6696915 # Number of loads squashed 54210409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 13655 # Number of memory responses ignored because the instruction is squashed 54310409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 10694 # Number of memory ordering violations 54410409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 6089616 # Number of stores squashed 5458317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5468317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 54710409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 151174 # Number of loads that were rescheduled 54810409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 488913 # Number of times an access to memory failed due to the cache being blocked 5498317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 55010409Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1620993 # Number of cycles IEW is squashing 55110409Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 2123091 # Number of cycles IEW is blocking 55210409Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 319754 # Number of cycles IEW is unblocking 55310409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 353236194 # Number of instructions dispatched to IQ 55410409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 55510409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 92429190 # Number of dispatched load instructions 55610409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 88465233 # Number of dispatched store instructions 55710409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions 55810409Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 8080 # Number of times the IQ has become full, causing a stall 55910409Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 327488 # Number of times the LSQ has become full, causing a stall 56010409Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 10694 # Number of memory order violations 56110409Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 1220289 # Number of branches that were predicted taken incorrectly 56210409Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 438322 # Number of branches that were predicted not taken incorrectly 56310409Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 1658611 # Number of branch mispredicts detected at execute 56410409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 342304940 # Number of executed instructions 56510409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 90585369 # Number of load instructions executed 56610409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 3962922 # Number of squashed instructions skipped in execute 5678317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 56810409Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 864 # number of nop insts executed 56910409Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 175168098 # number of memory reference insts executed 57010409Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 31752179 # Number of branches executed 57110409Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 84582729 # Number of stores executed 57210409Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.520806 # Inst execution rate 57310409Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 340904975 # cumulative count of insts sent to commit 57410409Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 340645195 # cumulative count of insts written-back 57510409Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 153543382 # num instructions producing a value 57610409Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 265817565 # num instructions consuming a value 5778317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 57810409Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.513432 # insts written-back per cycle 57910409Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back 5808317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 58110409Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 23000910 # The number of squashed insts skipped by commit 5829459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards 58310409Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 1611472 # The number of times a branch was mispredicted 58410409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 221213350 # Number of insts commited each cycle 58510409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.481883 # Number of insts commited each cycle 58610409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.053410 # Number of insts commited each cycle 5878317SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 58810409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 87832177 39.70% 39.70% # Number of insts commited each cycle 58910409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 69867778 31.58% 71.29% # Number of insts commited each cycle 59010409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 20927331 9.46% 80.75% # Number of insts commited each cycle 59110409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 13474141 6.09% 86.84% # Number of insts commited each cycle 59210409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 8800060 3.98% 90.82% # Number of insts commited each cycle 59310409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 4584952 2.07% 92.89% # Number of insts commited each cycle 59410409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 2913270 1.32% 94.21% # Number of insts commited each cycle 59510409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 2446398 1.11% 95.31% # Number of insts commited each cycle 59610409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 10367243 4.69% 100.00% # Number of insts commited each cycle 5978317SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5988317SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5998317SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 60010409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 221213350 # Number of insts commited each cycle 60110409Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 273037831 # Number of instructions committed 60210409Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed 6038317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 60410409Sandreas.hansson@arm.comsystem.cpu.commit.refs 168107892 # Number of memory references committed 60510409Sandreas.hansson@arm.comsystem.cpu.commit.loads 85732275 # Number of loads committed 6068317SN/Asystem.cpu.commit.membars 11033 # Number of memory barriers committed 60710409Sandreas.hansson@arm.comsystem.cpu.commit.branches 30563525 # Number of branches committed 6088317SN/Asystem.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. 60910409Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 258331704 # Number of committed integer instructions. 61010409Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 6225114 # Number of function calls committed. 61110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 61210409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction 61310409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction 61410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 61510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 61610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 61710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 61810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction 61910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction 62010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction 62110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction 62210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction 62310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction 62410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction 62510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction 62610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction 62710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction 62810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction 62910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction 63010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction 63110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction 63210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction 63310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction 63410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction 63510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction 63610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction 63710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction 63810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 63910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 64010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 64110409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction 64210409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction 64310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 64410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 64510409Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 327812213 # Class of committed instruction 64610409Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 10367243 # number cycles where commit BW limit reached 6478317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 64810409Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 561656707 # The number of ROB reads 64910488Snilay@cs.wisc.edusystem.cpu.rob.rob_writes 705358339 # The number of ROB writes 65010409Sandreas.hansson@arm.comsystem.cpu.timesIdled 49342 # Number of times that the entire CPU went into an idle state and unscheduled itself 65110409Sandreas.hansson@arm.comsystem.cpu.idleCycles 139797 # Total number of cycles that the CPU has spent unscheduled due to idling 65210409Sandreas.hansson@arm.comsystem.cpu.committedInsts 273037219 # Number of Instructions Simulated 65310409Sandreas.hansson@arm.comsystem.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated 65410409Sandreas.hansson@arm.comsystem.cpu.cpi 0.824361 # CPI: Cycles Per Instruction 65510409Sandreas.hansson@arm.comsystem.cpu.cpi_total 0.824361 # CPI: Total CPI of All Threads 65610409Sandreas.hansson@arm.comsystem.cpu.ipc 1.213060 # IPC: Instructions Per Cycle 65710409Sandreas.hansson@arm.comsystem.cpu.ipc_total 1.213060 # IPC: Total IPC of All Threads 65810488Snilay@cs.wisc.edusystem.cpu.int_regfile_reads 331187240 # number of integer regfile reads 65910409Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 136909181 # number of integer regfile writes 66010409Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 187100304 # number of floating regfile reads 66110409Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 132166714 # number of floating regfile writes 66210409Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 1296661589 # number of cc regfile reads 66310409Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 80246596 # number of cc regfile writes 66410409Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 1182269483 # number of misc regfile reads 6659459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 34421755 # number of misc regfile writes 66610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2029653 # Transaction distribution 66710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2029653 # Transaction distribution 66810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 966282 # Transaction distribution 66910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 49309 # Transaction distribution 67010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution 67110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution 67210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 220486 # Transaction distribution 67310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 220486 # Transaction distribution 67410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430858 # Packet count per connected master and slave (bytes) 67510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034802 # Packet count per connected master and slave (bytes) 67610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 5465660 # Packet count per connected master and slave (bytes) 67710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45758528 # Cumulative packet size per connected master and slave (bytes) 67810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034560 # Cumulative packet size per connected master and slave (bytes) 67910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 205793088 # Cumulative packet size per connected master and slave (bytes) 68010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 50213 # Total snoops (count) 68110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 3265775 # Request fanout histogram 68210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 5.015099 # Request fanout histogram 68310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.121946 # Request fanout histogram 68410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 68510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 68610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 68710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 68810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 68910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 69010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::5 3216466 98.49% 98.49% # Request fanout histogram 69110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::6 49309 1.51% 100.00% # Request fanout histogram 69210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 69310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 69410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 69510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 3265775 # Request fanout histogram 69610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2574531466 # Layer occupancy (ticks) 69710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) 69810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1074172389 # Layer occupancy (ticks) 69910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) 70010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2301537734 # Layer occupancy (ticks) 70110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) 70210409Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 715368 # number of replacements 70310409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.871967 # Cycle average of tags in use 70410409Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 88391816 # Total number of references to valid blocks. 70510409Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 715880 # Sample count of references to valid blocks. 70610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 123.472951 # Average number of references to valid blocks. 70710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 275609500 # Cycle when the warmup percentage was hit. 70810409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.871967 # Average occupied blocks per requestor 70910409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999750 # Average percentage of cache occupancy 71010409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999750 # Average percentage of cache occupancy 71110409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 71210409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 71310409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 71410409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id 71510409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 71610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 66 # Occupied blocks per task id 71710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 71810409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 178939093 # Number of tag accesses 71910409Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 178939093 # Number of data accesses 72010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 88391816 # number of ReadReq hits 72110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 88391816 # number of ReadReq hits 72210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 88391816 # number of demand (read+write) hits 72310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 88391816 # number of demand (read+write) hits 72410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 88391816 # number of overall hits 72510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 88391816 # number of overall hits 72610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 719790 # number of ReadReq misses 72710409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 719790 # number of ReadReq misses 72810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 719790 # number of demand (read+write) misses 72910409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 719790 # number of demand (read+write) misses 73010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 719790 # number of overall misses 73110409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 719790 # number of overall misses 73210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 5791847611 # number of ReadReq miss cycles 73310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 5791847611 # number of ReadReq miss cycles 73410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 5791847611 # number of demand (read+write) miss cycles 73510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 5791847611 # number of demand (read+write) miss cycles 73610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 5791847611 # number of overall miss cycles 73710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 5791847611 # number of overall miss cycles 73810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 89111606 # number of ReadReq accesses(hits+misses) 73910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 89111606 # number of ReadReq accesses(hits+misses) 74010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 89111606 # number of demand (read+write) accesses 74110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 89111606 # number of demand (read+write) accesses 74210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 89111606 # number of overall (read+write) accesses 74310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 89111606 # number of overall (read+write) accesses 74410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008077 # miss rate for ReadReq accesses 74510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses 74610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.008077 # miss rate for demand accesses 74710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.008077 # miss rate for demand accesses 74810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.008077 # miss rate for overall accesses 74910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.008077 # miss rate for overall accesses 75010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8046.579712 # average ReadReq miss latency 75110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 8046.579712 # average ReadReq miss latency 75210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency 75310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 8046.579712 # average overall miss latency 75410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 8046.579712 # average overall miss latency 75510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 8046.579712 # average overall miss latency 75610409Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 12631 # number of cycles access was blocked 75710409Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 17 # number of cycles access was blocked 75810409Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 1514 # number of cycles access was blocked 75910409Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 76010409Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 8.342801 # average number of cycles each access was blocked 76110409Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 17 # average number of cycles each access was blocked 7628317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 7638317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 76410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 3909 # number of ReadReq MSHR hits 76510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 3909 # number of ReadReq MSHR hits 76610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 3909 # number of demand (read+write) MSHR hits 76710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 3909 # number of demand (read+write) MSHR hits 76810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 3909 # number of overall MSHR hits 76910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 3909 # number of overall MSHR hits 77010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 715881 # number of ReadReq MSHR misses 77110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 715881 # number of ReadReq MSHR misses 77210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 715881 # number of demand (read+write) MSHR misses 77310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 715881 # number of demand (read+write) MSHR misses 77410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 715881 # number of overall MSHR misses 77510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 715881 # number of overall MSHR misses 77610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4688303087 # number of ReadReq MSHR miss cycles 77710409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 4688303087 # number of ReadReq MSHR miss cycles 77810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 4688303087 # number of demand (read+write) MSHR miss cycles 77910409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 4688303087 # number of demand (read+write) MSHR miss cycles 78010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 4688303087 # number of overall MSHR miss cycles 78110409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 4688303087 # number of overall MSHR miss cycles 78210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for ReadReq accesses 78310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses 78410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for demand accesses 78510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.008034 # mshr miss rate for demand accesses 78610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008034 # mshr miss rate for overall accesses 78710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.008034 # mshr miss rate for overall accesses 78810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6548.997790 # average ReadReq mshr miss latency 78910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6548.997790 # average ReadReq mshr miss latency 79010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency 79110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency 79210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6548.997790 # average overall mshr miss latency 79310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 6548.997790 # average overall mshr miss latency 7948317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 79510409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 6641923 # number of hwpf identified 79610409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 7386 # number of hwpf that were already in mshr 79710409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6574564 # number of hwpf that were already in the cache 79810409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 13578 # number of hwpf that were already in the prefetch queue 79910409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 80010409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated 80110409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 44298 # number of hwpf issued 80210409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 135685 # number of hwpf spanning a virtual page 80310409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 8049838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 80510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 8320.579960 # Cycle average of tags in use 80610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2794148 # Total number of references to valid blocks. 80710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 9718 # Sample count of references to valid blocks. 80810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 287.522947 # Average number of references to valid blocks. 8099838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 81010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 2574.248018 # Average occupied blocks per requestor 81110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 441.129211 # Average occupied blocks per requestor 81210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 367.415546 # Average occupied blocks per requestor 81310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4937.787185 # Average occupied blocks per requestor 81410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.157120 # Average percentage of cache occupancy 81510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.026924 # Average percentage of cache occupancy 81610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.022425 # Average percentage of cache occupancy 81710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.301379 # Average percentage of cache occupancy 81810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.507848 # Average percentage of cache occupancy 81910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 5676 # Occupied blocks per task id 82010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 4042 # Occupied blocks per task id 82110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::0 59 # Occupied blocks per task id 82210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 84 # Occupied blocks per task id 82310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 572 # Occupied blocks per task id 82410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 4961 # Occupied blocks per task id 82510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 82610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id 82710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 626 # Occupied blocks per task id 82810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id 82910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 3234 # Occupied blocks per task id 83010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.346436 # Percentage of cache occupancy per task id 83110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.246704 # Percentage of cache occupancy per task id 83210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 51678510 # Number of tag accesses 83310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 51678510 # Number of data accesses 83410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 714431 # number of ReadReq hits 83510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 1313042 # number of ReadReq hits 83610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2027473 # number of ReadReq hits 83710409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 966282 # number of Writeback hits 83810409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 966282 # number of Writeback hits 83910352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits 84010352Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits 84110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 219797 # number of ReadExReq hits 84210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 219797 # number of ReadExReq hits 84310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 714431 # number of demand (read+write) hits 84410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1532839 # number of demand (read+write) hits 84510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2247270 # number of demand (read+write) hits 84610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 714431 # number of overall hits 84710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1532839 # number of overall hits 84810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2247270 # number of overall hits 84910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 546 # number of ReadReq misses 85010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 730 # number of ReadReq misses 85110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 1276 # number of ReadReq misses 85210409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses 85310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses 85410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 689 # number of ReadExReq misses 85510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 689 # number of ReadExReq misses 85610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 546 # number of demand (read+write) misses 85710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1419 # number of demand (read+write) misses 85810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1965 # number of demand (read+write) misses 85910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 546 # number of overall misses 86010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1419 # number of overall misses 86110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1965 # number of overall misses 86210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 38998499 # number of ReadReq miss cycles 86310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 50021748 # number of ReadReq miss cycles 86410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 89020247 # number of ReadReq miss cycles 86510409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles 86610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles 86710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41954499 # number of ReadExReq miss cycles 86810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 41954499 # number of ReadExReq miss cycles 86910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 38998499 # number of demand (read+write) miss cycles 87010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 91976247 # number of demand (read+write) miss cycles 87110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 130974746 # number of demand (read+write) miss cycles 87210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 38998499 # number of overall miss cycles 87310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 91976247 # number of overall miss cycles 87410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 130974746 # number of overall miss cycles 87510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 714977 # number of ReadReq accesses(hits+misses) 87610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1313772 # number of ReadReq accesses(hits+misses) 87710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2028749 # number of ReadReq accesses(hits+misses) 87810409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 966282 # number of Writeback accesses(hits+misses) 87910409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 966282 # number of Writeback accesses(hits+misses) 88010409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) 88110409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) 88210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 220486 # number of ReadExReq accesses(hits+misses) 88310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 220486 # number of ReadExReq accesses(hits+misses) 88410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 714977 # number of demand (read+write) accesses 88510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1534258 # number of demand (read+write) accesses 88610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2249235 # number of demand (read+write) accesses 88710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 714977 # number of overall (read+write) accesses 88810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1534258 # number of overall (read+write) accesses 88910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2249235 # number of overall (read+write) accesses 89010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000764 # miss rate for ReadReq accesses 89110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000556 # miss rate for ReadReq accesses 89210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.000629 # miss rate for ReadReq accesses 89310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses 89410409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses 89510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003125 # miss rate for ReadExReq accesses 89610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.003125 # miss rate for ReadExReq accesses 89710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.000764 # miss rate for demand accesses 89810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.000925 # miss rate for demand accesses 89910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.000874 # miss rate for demand accesses 90010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.000764 # miss rate for overall accesses 90110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.000925 # miss rate for overall accesses 90210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.000874 # miss rate for overall accesses 90310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71425.822344 # average ReadReq miss latency 90410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68522.942466 # average ReadReq miss latency 90510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 69765.083856 # average ReadReq miss latency 90610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency 90710409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency 90810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60891.870827 # average ReadExReq miss latency 90910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 60891.870827 # average ReadExReq miss latency 91010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency 91110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency 91210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 66653.814758 # average overall miss latency 91310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71425.822344 # average overall miss latency 91410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 64817.651163 # average overall miss latency 91510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 66653.814758 # average overall miss latency 91610409Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 6173 # number of cycles access was blocked 9179348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91810409Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 209 # number of cycles access was blocked 9199348SAli.Saidi@ARM.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 92010409Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.535885 # average number of cycles each access was blocked 9219348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9229348SAli.Saidi@ARM.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 9239348SAli.Saidi@ARM.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 92410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 92510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits 92610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits 92710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 114 # number of ReadExReq MSHR hits 92810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 114 # number of ReadExReq MSHR hits 92910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 93010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 157 # number of demand (read+write) MSHR hits 93110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 225 # number of demand (read+write) MSHR hits 93210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 93310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 157 # number of overall MSHR hits 93410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 225 # number of overall MSHR hits 93510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 478 # number of ReadReq MSHR misses 93610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 687 # number of ReadReq MSHR misses 93710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 1165 # number of ReadReq MSHR misses 93810409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 44298 # number of HardPFReq MSHR misses 93910409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 44298 # number of HardPFReq MSHR misses 94010409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses 94110409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses 94210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 575 # number of ReadExReq MSHR misses 94310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 575 # number of ReadExReq MSHR misses 94410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 478 # number of demand (read+write) MSHR misses 94510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1262 # number of demand (read+write) MSHR misses 94610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 1740 # number of demand (read+write) MSHR misses 94710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 478 # number of overall MSHR misses 94810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1262 # number of overall MSHR misses 94910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 44298 # number of overall MSHR misses 95010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 46038 # number of overall MSHR misses 95110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32592250 # number of ReadReq MSHR miss cycles 95210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 42691498 # number of ReadReq MSHR miss cycles 95310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 75283748 # number of ReadReq MSHR miss cycles 95410409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of HardPFReq MSHR miss cycles 95510409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 669707182 # number of HardPFReq MSHR miss cycles 95610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles 95710409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles 95810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34465750 # number of ReadExReq MSHR miss cycles 95910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34465750 # number of ReadExReq MSHR miss cycles 96010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32592250 # number of demand (read+write) MSHR miss cycles 96110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 77157248 # number of demand (read+write) MSHR miss cycles 96210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 109749498 # number of demand (read+write) MSHR miss cycles 96310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32592250 # number of overall MSHR miss cycles 96410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 77157248 # number of overall MSHR miss cycles 96510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 669707182 # number of overall MSHR miss cycles 96610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 779456680 # number of overall MSHR miss cycles 96710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for ReadReq accesses 96810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000523 # mshr miss rate for ReadReq accesses 96910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000574 # mshr miss rate for ReadReq accesses 97010409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 97110409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 97210409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses 97310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses 97410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.002608 # mshr miss rate for ReadExReq accesses 97510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.002608 # mshr miss rate for ReadExReq accesses 97610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for demand accesses 97710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for demand accesses 97810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.000774 # mshr miss rate for demand accesses 97910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000669 # mshr miss rate for overall accesses 98010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000823 # mshr miss rate for overall accesses 98110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 98210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.020468 # mshr miss rate for overall accesses 98310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68184.623431 # average ReadReq mshr miss latency 98410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62141.918486 # average ReadReq mshr miss latency 98510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64621.242918 # average ReadReq mshr miss latency 98610409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average HardPFReq mshr miss latency 98710409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 15118.226150 # average HardPFReq mshr miss latency 98810409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 98910409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 99010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59940.434783 # average ReadExReq mshr miss latency 99110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59940.434783 # average ReadExReq mshr miss latency 99210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency 99310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency 99410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 63074.424138 # average overall mshr miss latency 99510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68184.623431 # average overall mshr miss latency 99610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61138.865293 # average overall mshr miss latency 99710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 15118.226150 # average overall mshr miss latency 99810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 16930.724184 # average overall mshr miss latency 9999348SAli.Saidi@ARM.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 100010409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1533746 # number of replacements 100110409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.875745 # Cycle average of tags in use 100210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 163803379 # Total number of references to valid blocks. 100310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1534258 # Sample count of references to valid blocks. 100410409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 106.763907 # Average number of references to valid blocks. 100510409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 61007500 # Cycle when the warmup percentage was hit. 100610409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.875745 # Average occupied blocks per requestor 100710409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy 100810409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy 100910409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 101010409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 101110409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id 101210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 101310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 101410409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 101510409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 336684382 # Number of tag accesses 101610409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 336684382 # Number of data accesses 101710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 82726080 # number of ReadReq hits 101810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 82726080 # number of ReadReq hits 101910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 80985064 # number of WriteReq hits 102010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 80985064 # number of WriteReq hits 102110409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits 102210409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits 102310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits 102410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits 10259459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 10269459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 102710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 163711144 # number of demand (read+write) hits 102810409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 163711144 # number of demand (read+write) hits 102910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 163781573 # number of overall hits 103010409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 163781573 # number of overall hits 103110409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 2704026 # number of ReadReq misses 103210409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 2704026 # number of ReadReq misses 103310409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1067635 # number of WriteReq misses 103410409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1067635 # number of WriteReq misses 103510409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses 103610409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses 103710409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses 103810409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses 103910409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3771661 # number of demand (read+write) misses 104010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3771661 # number of demand (read+write) misses 104110409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3771680 # number of overall misses 104210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3771680 # number of overall misses 104310409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 21403617484 # number of ReadReq miss cycles 104410409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 21403617484 # number of ReadReq miss cycles 104510409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 8344449821 # number of WriteReq miss cycles 104610409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 8344449821 # number of WriteReq miss cycles 104710409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 164500 # number of LoadLockedReq miss cycles 104810409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 164500 # number of LoadLockedReq miss cycles 104910409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 29748067305 # number of demand (read+write) miss cycles 105010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 29748067305 # number of demand (read+write) miss cycles 105110409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 29748067305 # number of overall miss cycles 105210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 29748067305 # number of overall miss cycles 105310409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 85430106 # number of ReadReq accesses(hits+misses) 105410409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 85430106 # number of ReadReq accesses(hits+misses) 105510409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) 105610409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) 105710409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) 105810409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) 105910409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) 106010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) 10619459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 10629459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 106310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 167482805 # number of demand (read+write) accesses 106410409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 167482805 # number of demand (read+write) accesses 106510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 167553253 # number of overall (read+write) accesses 106610409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 167553253 # number of overall (read+write) accesses 106710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses 106810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses 106910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013012 # miss rate for WriteReq accesses 107010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.013012 # miss rate for WriteReq accesses 107110409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses 107210409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses 107310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses 107410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses 107510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.022520 # miss rate for demand accesses 107610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.022520 # miss rate for demand accesses 107710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.022510 # miss rate for overall accesses 107810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.022510 # miss rate for overall accesses 107910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7915.462900 # average ReadReq miss latency 108010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 7915.462900 # average ReadReq miss latency 108110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7815.826402 # average WriteReq miss latency 108210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 7815.826402 # average WriteReq miss latency 108310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32900 # average LoadLockedReq miss latency 108410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32900 # average LoadLockedReq miss latency 108510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 7887.259037 # average overall miss latency 108610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 7887.259037 # average overall miss latency 108710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 7887.219304 # average overall miss latency 108810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 7887.219304 # average overall miss latency 108910409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked 109010409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 761243 # number of cycles access was blocked 109110409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 109210409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 111844 # number of cycles access was blocked 109310409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 12.500000 # average number of cycles each access was blocked 109410409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 6.806293 # average number of cycles each access was blocked 10959449SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 10969449SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 109710409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 966282 # number of writebacks 109810409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 966282 # number of writebacks 109910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390265 # number of ReadReq MSHR hits 110010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 1390265 # number of ReadReq MSHR hits 110110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 847147 # number of WriteReq MSHR hits 110210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 847147 # number of WriteReq MSHR hits 110310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits 110410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits 110510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2237412 # number of demand (read+write) MSHR hits 110610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2237412 # number of demand (read+write) MSHR hits 110710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2237412 # number of overall MSHR hits 110810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2237412 # number of overall MSHR hits 110910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313761 # number of ReadReq MSHR misses 111010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1313761 # number of ReadReq MSHR misses 111110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 220488 # number of WriteReq MSHR misses 111210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 220488 # number of WriteReq MSHR misses 111310409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses 111410409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses 111510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1534249 # number of demand (read+write) MSHR misses 111610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1534249 # number of demand (read+write) MSHR misses 111710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1534260 # number of overall MSHR misses 111810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1534260 # number of overall MSHR misses 111910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9295842016 # number of ReadReq MSHR miss cycles 112010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 9295842016 # number of ReadReq MSHR miss cycles 112110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1592020910 # number of WriteReq MSHR miss cycles 112210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1592020910 # number of WriteReq MSHR miss cycles 112310409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 638250 # number of SoftPFReq MSHR miss cycles 112410409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 638250 # number of SoftPFReq MSHR miss cycles 112510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10887862926 # number of demand (read+write) MSHR miss cycles 112610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10887862926 # number of demand (read+write) MSHR miss cycles 112710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10888501176 # number of overall MSHR miss cycles 112810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10888501176 # number of overall MSHR miss cycles 112910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses 113010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses 113110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses 113210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses 113310409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses 113410409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses 113510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses 113610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses 113710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses 113810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses 113910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7075.748189 # average ReadReq mshr miss latency 114010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7075.748189 # average ReadReq mshr miss latency 114110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7220.442428 # average WriteReq mshr miss latency 114210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7220.442428 # average WriteReq mshr miss latency 114310409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58022.727273 # average SoftPFReq mshr miss latency 114410409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58022.727273 # average SoftPFReq mshr miss latency 114510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7096.542299 # average overall mshr miss latency 114610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 7096.542299 # average overall mshr miss latency 114710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7096.907419 # average overall mshr miss latency 114810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 7096.907419 # average overall mshr miss latency 11499449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 11507860SN/A 11517860SN/A---------- End Simulation Statistics ---------- 1152