config.ini revision 7860
16242Sgblack@eecs.umich.edu[root]
211575SDylan.Johnson@ARM.comtype=Root
37093Sgblack@eecs.umich.educhildren=system
47093Sgblack@eecs.umich.edudummy=0
57093Sgblack@eecs.umich.edu
67093Sgblack@eecs.umich.edu[system]
77093Sgblack@eecs.umich.edutype=System
87093Sgblack@eecs.umich.educhildren=cpu membus physmem
97093Sgblack@eecs.umich.edumem_mode=atomic
107093Sgblack@eecs.umich.eduphysmem=system.physmem
117093Sgblack@eecs.umich.edu
127093Sgblack@eecs.umich.edu[system.cpu]
137093Sgblack@eecs.umich.edutype=DerivO3CPU
146242Sgblack@eecs.umich.educhildren=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
156242Sgblack@eecs.umich.eduBTBEntries=4096
166242Sgblack@eecs.umich.eduBTBTagSize=16
176242Sgblack@eecs.umich.eduLFSTSize=1024
186242Sgblack@eecs.umich.eduLQEntries=32
196242Sgblack@eecs.umich.eduRASSize=16
206242Sgblack@eecs.umich.eduSQEntries=32
216242Sgblack@eecs.umich.eduSSITSize=1024
226242Sgblack@eecs.umich.eduactivity=0
236242Sgblack@eecs.umich.edubackComSize=5
246242Sgblack@eecs.umich.educachePorts=200
256242Sgblack@eecs.umich.educhecker=Null
266242Sgblack@eecs.umich.educhoiceCtrBits=2
276242Sgblack@eecs.umich.educhoicePredictorSize=8192
286242Sgblack@eecs.umich.educlock=500
296242Sgblack@eecs.umich.educommitToDecodeDelay=1
306242Sgblack@eecs.umich.educommitToFetchDelay=1
316242Sgblack@eecs.umich.educommitToIEWDelay=1
326242Sgblack@eecs.umich.educommitToRenameDelay=1
336242Sgblack@eecs.umich.educommitWidth=8
346242Sgblack@eecs.umich.educpu_id=0
356242Sgblack@eecs.umich.edudecodeToFetchDelay=1
366242Sgblack@eecs.umich.edudecodeToRenameDelay=1
376242Sgblack@eecs.umich.edudecodeWidth=8
386242Sgblack@eecs.umich.edudefer_registration=false
396242Sgblack@eecs.umich.edudispatchWidth=8
406242Sgblack@eecs.umich.edudo_checkpoint_insts=true
4110037SARM gem5 Developersdo_statistics_insts=true
426242Sgblack@eecs.umich.edudtb=system.cpu.dtb
436242Sgblack@eecs.umich.edufetchToDecodeDelay=1
446242Sgblack@eecs.umich.edufetchTrapLatency=1
456242Sgblack@eecs.umich.edufetchWidth=8
4610037SARM gem5 DevelopersforwardComSize=5
4710037SARM gem5 DevelopersfuPool=system.cpu.fuPool
486242Sgblack@eecs.umich.edufunction_trace=false
499256SAndreas.Sandberg@arm.comfunction_trace_start=0
506242Sgblack@eecs.umich.eduglobalCtrBits=2
5110037SARM gem5 DevelopersglobalHistoryBits=13
5210037SARM gem5 DevelopersglobalPredictorSize=8192
5310037SARM gem5 DevelopersiewToCommitDelay=1
546242Sgblack@eecs.umich.eduiewToDecodeDelay=1
556242Sgblack@eecs.umich.eduiewToFetchDelay=1
566242Sgblack@eecs.umich.eduiewToRenameDelay=1
5710037SARM gem5 DevelopersinstShiftAmt=2
5810037SARM gem5 DevelopersissueToExecuteDelay=1
5910037SARM gem5 DevelopersissueWidth=8
6010037SARM gem5 Developersitb=system.cpu.itb
6110037SARM gem5 DeveloperslocalCtrBits=2
6210037SARM gem5 DeveloperslocalHistoryBits=11
6310037SARM gem5 DeveloperslocalHistoryTableSize=2048
6410037SARM gem5 DeveloperslocalPredictorSize=2048
6510037SARM gem5 Developersmax_insts_all_threads=0
6610037SARM gem5 Developersmax_insts_any_thread=0
6710037SARM gem5 Developersmax_loads_all_threads=0
6810037SARM gem5 Developersmax_loads_any_thread=0
6910037SARM gem5 DevelopersnumIQEntries=64
7010037SARM gem5 DevelopersnumPhysFloatRegs=256
7110037SARM gem5 DevelopersnumPhysIntRegs=256
727259Sgblack@eecs.umich.edunumROBEntries=192
7310037SARM gem5 DevelopersnumRobs=1
7410037SARM gem5 DevelopersnumThreads=1
7510037SARM gem5 Developersphase=0
7610037SARM gem5 DeveloperspredType=tournament
7710037SARM gem5 Developersprogress_interval=0
7810037SARM gem5 DevelopersrenameToDecodeDelay=1
7910037SARM gem5 DevelopersrenameToFetchDelay=1
8010037SARM gem5 DevelopersrenameToIEWDelay=2
8110037SARM gem5 DevelopersrenameToROBDelay=1
8210037SARM gem5 DevelopersrenameWidth=8
8310037SARM gem5 DeveloperssmtCommitPolicy=RoundRobin
8410037SARM gem5 DeveloperssmtFetchPolicy=SingleThread
8510037SARM gem5 DeveloperssmtIQPolicy=Partitioned
8610037SARM gem5 DeveloperssmtIQThreshold=100
8710037SARM gem5 DeveloperssmtLSQPolicy=Partitioned
8810037SARM gem5 DeveloperssmtLSQThreshold=100
898868SMatt.Horsnell@arm.comsmtNumFetchingThreads=1
9010037SARM gem5 DeveloperssmtROBPolicy=Partitioned
9110037SARM gem5 DeveloperssmtROBThreshold=100
9210037SARM gem5 DeveloperssquashWidth=8
9310037SARM gem5 Developerssystem=system
9410037SARM gem5 Developerstracer=system.cpu.tracer
9510037SARM gem5 DeveloperstrapLatency=13
9610037SARM gem5 DeveloperswbDepth=1
9710037SARM gem5 DeveloperswbWidth=8
9810037SARM gem5 Developersworkload=system.cpu.workload
9910037SARM gem5 Developersdcache_port=system.cpu.dcache.cpu_side
10010037SARM gem5 Developersicache_port=system.cpu.icache.cpu_side
10110037SARM gem5 Developers
10210037SARM gem5 Developers[system.cpu.dcache]
10310037SARM gem5 Developerstype=BaseCache
10410037SARM gem5 Developersaddr_range=0:18446744073709551615
10510037SARM gem5 Developersassoc=2
10610037SARM gem5 Developersblock_size=64
10710037SARM gem5 Developersforward_snoops=true
10810037SARM gem5 Developershash_delay=1
10910037SARM gem5 Developerslatency=1000
11010037SARM gem5 Developersmax_miss_count=0
11110037SARM gem5 Developersmshrs=10
11210037SARM gem5 Developersnum_cpus=1
11310037SARM gem5 Developersprefetch_data_accesses_only=false
11410037SARM gem5 Developersprefetch_degree=1
11510037SARM gem5 Developersprefetch_latency=10000
11610037SARM gem5 Developersprefetch_on_access=false
11710037SARM gem5 Developersprefetch_past_page=false
11810037SARM gem5 Developersprefetch_policy=none
11910037SARM gem5 Developersprefetch_serial_squash=false
12010037SARM gem5 Developersprefetch_use_cpu_id=true
12110037SARM gem5 Developersprefetcher_size=100
12210037SARM gem5 DevelopersprioritizeRequests=false
12310037SARM gem5 Developersrepl=Null
12410037SARM gem5 Developerssize=262144
12510037SARM gem5 Developerssubblock_size=0
12610037SARM gem5 Developerstgts_per_mshr=20
12710037SARM gem5 Developerstrace_addr=0
12810037SARM gem5 Developerstwo_queue=false
12910037SARM gem5 Developerswrite_buffers=8
13010037SARM gem5 Developerscpu_side=system.cpu.dcache_port
13110037SARM gem5 Developersmem_side=system.cpu.toL2Bus.port[1]
13210037SARM gem5 Developers
13310037SARM gem5 Developers[system.cpu.dtb]
13410037SARM gem5 Developerstype=ArmTLB
13510037SARM gem5 Developerssize=64
13611768SCurtis.Dunham@arm.com
13710037SARM gem5 Developers[system.cpu.fuPool]
13811768SCurtis.Dunham@arm.comtype=FUPool
13910037SARM gem5 Developerschildren=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
14010037SARM gem5 DevelopersFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
1417351Sgblack@eecs.umich.edu
14210037SARM gem5 Developers[system.cpu.fuPool.FUList0]
14310037SARM gem5 Developerstype=FUDesc
14410037SARM gem5 Developerschildren=opList
14510037SARM gem5 Developerscount=6
14610037SARM gem5 DevelopersopList=system.cpu.fuPool.FUList0.opList
14710037SARM gem5 Developers
14810037SARM gem5 Developers[system.cpu.fuPool.FUList0.opList]
14910037SARM gem5 Developerstype=OpDesc
15010037SARM gem5 DevelopersissueLat=1
15110037SARM gem5 DevelopersopClass=IntAlu
15210037SARM gem5 DevelopersopLat=1
15310037SARM gem5 Developers
15410037SARM gem5 Developers[system.cpu.fuPool.FUList1]
15510037SARM gem5 Developerstype=FUDesc
15610037SARM gem5 Developerschildren=opList0 opList1
15710037SARM gem5 Developerscount=2
15810037SARM gem5 DevelopersopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
15910037SARM gem5 Developers
16010037SARM gem5 Developers[system.cpu.fuPool.FUList1.opList0]
16110037SARM gem5 Developerstype=OpDesc
16210037SARM gem5 DevelopersissueLat=1
16310037SARM gem5 DevelopersopClass=IntMult
16410037SARM gem5 DevelopersopLat=3
16510037SARM gem5 Developers
16610037SARM gem5 Developers[system.cpu.fuPool.FUList1.opList1]
16710037SARM gem5 Developerstype=OpDesc
16810037SARM gem5 DevelopersissueLat=19
16910037SARM gem5 DevelopersopClass=IntDiv
17010037SARM gem5 DevelopersopLat=20
17110037SARM gem5 Developers
17210037SARM gem5 Developers[system.cpu.fuPool.FUList2]
17310037SARM gem5 Developerstype=FUDesc
17410037SARM gem5 Developerschildren=opList0 opList1 opList2
17510037SARM gem5 Developerscount=4
17610037SARM gem5 DevelopersopList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
17710037SARM gem5 Developers
17810037SARM gem5 Developers[system.cpu.fuPool.FUList2.opList0]
17910037SARM gem5 Developerstype=OpDesc
18010037SARM gem5 DevelopersissueLat=1
18110037SARM gem5 DevelopersopClass=FloatAdd
18210037SARM gem5 DevelopersopLat=2
18310037SARM gem5 Developers
18410037SARM gem5 Developers[system.cpu.fuPool.FUList2.opList1]
18510037SARM gem5 Developerstype=OpDesc
18610037SARM gem5 DevelopersissueLat=1
18710037SARM gem5 DevelopersopClass=FloatCmp
18810037SARM gem5 DevelopersopLat=2
18910037SARM gem5 Developers
19010037SARM gem5 Developers[system.cpu.fuPool.FUList2.opList2]
19110037SARM gem5 Developerstype=OpDesc
19210037SARM gem5 DevelopersissueLat=1
19310037SARM gem5 DevelopersopClass=FloatCvt
19410037SARM gem5 DevelopersopLat=2
19510037SARM gem5 Developers
19610037SARM gem5 Developers[system.cpu.fuPool.FUList3]
19710037SARM gem5 Developerstype=FUDesc
19810037SARM gem5 Developerschildren=opList0 opList1 opList2
19910037SARM gem5 Developerscount=2
20010037SARM gem5 DevelopersopList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
20110037SARM gem5 Developers
20210037SARM gem5 Developers[system.cpu.fuPool.FUList3.opList0]
20310037SARM gem5 Developerstype=OpDesc
20410037SARM gem5 DevelopersissueLat=1
20510037SARM gem5 DevelopersopClass=FloatMult
20610037SARM gem5 DevelopersopLat=4
20710037SARM gem5 Developers
20810037SARM gem5 Developers[system.cpu.fuPool.FUList3.opList1]
20910037SARM gem5 Developerstype=OpDesc
21010037SARM gem5 DevelopersissueLat=12
21110037SARM gem5 DevelopersopClass=FloatDiv
21210037SARM gem5 DevelopersopLat=12
21310037SARM gem5 Developers
21410037SARM gem5 Developers[system.cpu.fuPool.FUList3.opList2]
21510037SARM gem5 Developerstype=OpDesc
21610037SARM gem5 DevelopersissueLat=24
21710037SARM gem5 DevelopersopClass=FloatSqrt
21810037SARM gem5 DevelopersopLat=24
21910037SARM gem5 Developers
22010037SARM gem5 Developers[system.cpu.fuPool.FUList4]
22110037SARM gem5 Developerstype=FUDesc
22210037SARM gem5 Developerschildren=opList
22310037SARM gem5 Developerscount=0
22410037SARM gem5 DevelopersopList=system.cpu.fuPool.FUList4.opList
22510037SARM gem5 Developers
22610037SARM gem5 Developers[system.cpu.fuPool.FUList4.opList]
22710037SARM gem5 Developerstype=OpDesc
22810037SARM gem5 DevelopersissueLat=1
22910037SARM gem5 DevelopersopClass=MemRead
23010037SARM gem5 DevelopersopLat=1
23110037SARM gem5 Developers
23210037SARM gem5 Developers[system.cpu.fuPool.FUList5]
23310037SARM gem5 Developerstype=FUDesc
23410037SARM gem5 Developerschildren=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
23510037SARM gem5 Developerscount=4
23610037SARM gem5 DevelopersopList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
23710037SARM gem5 Developers
23810037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList00]
23910037SARM gem5 Developerstype=OpDesc
24010037SARM gem5 DevelopersissueLat=1
24110037SARM gem5 DevelopersopClass=SimdAdd
24210037SARM gem5 DevelopersopLat=1
24310037SARM gem5 Developers
24410037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList01]
24510037SARM gem5 Developerstype=OpDesc
24610037SARM gem5 DevelopersissueLat=1
24710037SARM gem5 DevelopersopClass=SimdAddAcc
24810037SARM gem5 DevelopersopLat=1
24910037SARM gem5 Developers
25010037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList02]
25110037SARM gem5 Developerstype=OpDesc
25210037SARM gem5 DevelopersissueLat=1
25310037SARM gem5 DevelopersopClass=SimdAlu
25410037SARM gem5 DevelopersopLat=1
25510037SARM gem5 Developers
25610037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList03]
25710037SARM gem5 Developerstype=OpDesc
25810037SARM gem5 DevelopersissueLat=1
25910037SARM gem5 DevelopersopClass=SimdCmp
26010037SARM gem5 DevelopersopLat=1
26110037SARM gem5 Developers
26210037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList04]
26310037SARM gem5 Developerstype=OpDesc
26410037SARM gem5 DevelopersissueLat=1
26510037SARM gem5 DevelopersopClass=SimdCvt
26610037SARM gem5 DevelopersopLat=1
26710037SARM gem5 Developers
26810037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList05]
26910037SARM gem5 Developerstype=OpDesc
27010037SARM gem5 DevelopersissueLat=1
27110037SARM gem5 DevelopersopClass=SimdMisc
27210037SARM gem5 DevelopersopLat=1
27310037SARM gem5 Developers
27410037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList06]
27510037SARM gem5 Developerstype=OpDesc
27610037SARM gem5 DevelopersissueLat=1
27710037SARM gem5 DevelopersopClass=SimdMult
27810037SARM gem5 DevelopersopLat=1
27910037SARM gem5 Developers
28010037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList07]
28110037SARM gem5 Developerstype=OpDesc
28210037SARM gem5 DevelopersissueLat=1
28310037SARM gem5 DevelopersopClass=SimdMultAcc
28410037SARM gem5 DevelopersopLat=1
28510037SARM gem5 Developers
28610037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList08]
28710037SARM gem5 Developerstype=OpDesc
28810037SARM gem5 DevelopersissueLat=1
28910037SARM gem5 DevelopersopClass=SimdShift
29010037SARM gem5 DevelopersopLat=1
29110037SARM gem5 Developers
29210037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList09]
29310037SARM gem5 Developerstype=OpDesc
29410037SARM gem5 DevelopersissueLat=1
29510037SARM gem5 DevelopersopClass=SimdShiftAcc
29610037SARM gem5 DevelopersopLat=1
29710037SARM gem5 Developers
29810037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList10]
29910037SARM gem5 Developerstype=OpDesc
30010037SARM gem5 DevelopersissueLat=1
30110037SARM gem5 DevelopersopClass=SimdSqrt
30210037SARM gem5 DevelopersopLat=1
30310037SARM gem5 Developers
30410037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList11]
30510037SARM gem5 Developerstype=OpDesc
30610037SARM gem5 DevelopersissueLat=1
30710037SARM gem5 DevelopersopClass=SimdFloatAdd
30810037SARM gem5 DevelopersopLat=1
30910037SARM gem5 Developers
31010037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList12]
31110037SARM gem5 Developerstype=OpDesc
31210037SARM gem5 DevelopersissueLat=1
31310037SARM gem5 DevelopersopClass=SimdFloatAlu
31410037SARM gem5 DevelopersopLat=1
31510037SARM gem5 Developers
31610037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList13]
31710037SARM gem5 Developerstype=OpDesc
31810037SARM gem5 DevelopersissueLat=1
31910037SARM gem5 DevelopersopClass=SimdFloatCmp
32010037SARM gem5 DevelopersopLat=1
32110037SARM gem5 Developers
32210037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList14]
32310037SARM gem5 Developerstype=OpDesc
32410037SARM gem5 DevelopersissueLat=1
32510037SARM gem5 DevelopersopClass=SimdFloatCvt
32610037SARM gem5 DevelopersopLat=1
32710037SARM gem5 Developers
32810037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList15]
32910037SARM gem5 Developerstype=OpDesc
33010037SARM gem5 DevelopersissueLat=1
33110037SARM gem5 DevelopersopClass=SimdFloatDiv
33210037SARM gem5 DevelopersopLat=1
33310037SARM gem5 Developers
33410037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList16]
33510037SARM gem5 Developerstype=OpDesc
33610037SARM gem5 DevelopersissueLat=1
33710037SARM gem5 DevelopersopClass=SimdFloatMisc
33810037SARM gem5 DevelopersopLat=1
33910037SARM gem5 Developers
34010037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList17]
34110037SARM gem5 Developerstype=OpDesc
34210037SARM gem5 DevelopersissueLat=1
34310037SARM gem5 DevelopersopClass=SimdFloatMult
34410037SARM gem5 DevelopersopLat=1
34510037SARM gem5 Developers
34610037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList18]
34710037SARM gem5 Developerstype=OpDesc
34810037SARM gem5 DevelopersissueLat=1
34910037SARM gem5 DevelopersopClass=SimdFloatMultAcc
35010037SARM gem5 DevelopersopLat=1
35110037SARM gem5 Developers
35210037SARM gem5 Developers[system.cpu.fuPool.FUList5.opList19]
35310037SARM gem5 Developerstype=OpDesc
35410037SARM gem5 DevelopersissueLat=1
35510037SARM gem5 DevelopersopClass=SimdFloatSqrt
35610037SARM gem5 DevelopersopLat=1
35710037SARM gem5 Developers
35810037SARM gem5 Developers[system.cpu.fuPool.FUList6]
35910037SARM gem5 Developerstype=FUDesc
36010037SARM gem5 Developerschildren=opList
36110037SARM gem5 Developerscount=0
36210037SARM gem5 DevelopersopList=system.cpu.fuPool.FUList6.opList
36310037SARM gem5 Developers
36410037SARM gem5 Developers[system.cpu.fuPool.FUList6.opList]
36510037SARM gem5 Developerstype=OpDesc
36610037SARM gem5 DevelopersissueLat=1
36710037SARM gem5 DevelopersopClass=MemWrite
36810037SARM gem5 DevelopersopLat=1
36910037SARM gem5 Developers
37010037SARM gem5 Developers[system.cpu.fuPool.FUList7]
37110037SARM gem5 Developerstype=FUDesc
37210037SARM gem5 Developerschildren=opList0 opList1
37310037SARM gem5 Developerscount=4
37410037SARM gem5 DevelopersopList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
37510037SARM gem5 Developers
37610037SARM gem5 Developers[system.cpu.fuPool.FUList7.opList0]
37710037SARM gem5 Developerstype=OpDesc
37810037SARM gem5 DevelopersissueLat=1
37910037SARM gem5 DevelopersopClass=MemRead
38010037SARM gem5 DevelopersopLat=1
38110037SARM gem5 Developers
38210037SARM gem5 Developers[system.cpu.fuPool.FUList7.opList1]
3837259Sgblack@eecs.umich.edutype=OpDesc
38410037SARM gem5 DevelopersissueLat=1
38510037SARM gem5 DevelopersopClass=MemWrite
38610037SARM gem5 DevelopersopLat=1
38710037SARM gem5 Developers
38810037SARM gem5 Developers[system.cpu.fuPool.FUList8]
38910037SARM gem5 Developerstype=FUDesc
39010037SARM gem5 Developerschildren=opList
39110037SARM gem5 Developerscount=1
39210037SARM gem5 DevelopersopList=system.cpu.fuPool.FUList8.opList
39310037SARM gem5 Developers
39410037SARM gem5 Developers[system.cpu.fuPool.FUList8.opList]
39510037SARM gem5 Developerstype=OpDesc
39610037SARM gem5 DevelopersissueLat=3
39710037SARM gem5 DevelopersopClass=IprAccess
39810037SARM gem5 DevelopersopLat=3
39910037SARM gem5 Developers
40010037SARM gem5 Developers[system.cpu.icache]
40110037SARM gem5 Developerstype=BaseCache
40210037SARM gem5 Developersaddr_range=0:18446744073709551615
40310037SARM gem5 Developersassoc=2
40410037SARM gem5 Developersblock_size=64
40510037SARM gem5 Developersforward_snoops=true
40610037SARM gem5 Developershash_delay=1
40710037SARM gem5 Developerslatency=1000
40810037SARM gem5 Developersmax_miss_count=0
40910037SARM gem5 Developersmshrs=10
41010037SARM gem5 Developersnum_cpus=1
41110037SARM gem5 Developersprefetch_data_accesses_only=false
41210037SARM gem5 Developersprefetch_degree=1
41310037SARM gem5 Developersprefetch_latency=10000
41410037SARM gem5 Developersprefetch_on_access=false
41510037SARM gem5 Developersprefetch_past_page=false
41610037SARM gem5 Developersprefetch_policy=none
41710037SARM gem5 Developersprefetch_serial_squash=false
41810037SARM gem5 Developersprefetch_use_cpu_id=true
41910037SARM gem5 Developersprefetcher_size=100
42010037SARM gem5 DevelopersprioritizeRequests=false
42110037SARM gem5 Developersrepl=Null
42210037SARM gem5 Developerssize=131072
42311768SCurtis.Dunham@arm.comsubblock_size=0
42411768SCurtis.Dunham@arm.comtgts_per_mshr=20
4257259Sgblack@eecs.umich.edutrace_addr=0
42610037SARM gem5 Developerstwo_queue=false
42710037SARM gem5 Developerswrite_buffers=8
42810037SARM gem5 Developerscpu_side=system.cpu.icache_port
42910037SARM gem5 Developersmem_side=system.cpu.toL2Bus.port[0]
43010037SARM gem5 Developers
43110037SARM gem5 Developers[system.cpu.itb]
43210037SARM gem5 Developerstype=ArmTLB
43310037SARM gem5 Developerssize=64
43410037SARM gem5 Developers
43510037SARM gem5 Developers[system.cpu.l2cache]
43610037SARM gem5 Developerstype=BaseCache
43710037SARM gem5 Developersaddr_range=0:18446744073709551615
43810037SARM gem5 Developersassoc=2
43910037SARM gem5 Developersblock_size=64
44010037SARM gem5 Developersforward_snoops=true
44110037SARM gem5 Developershash_delay=1
44210037SARM gem5 Developerslatency=1000
44310037SARM gem5 Developersmax_miss_count=0
44410037SARM gem5 Developersmshrs=10
44510037SARM gem5 Developersnum_cpus=1
44610037SARM gem5 Developersprefetch_data_accesses_only=false
44710037SARM gem5 Developersprefetch_degree=1
44810037SARM gem5 Developersprefetch_latency=10000
44910037SARM gem5 Developersprefetch_on_access=false
45010037SARM gem5 Developersprefetch_past_page=false
45110037SARM gem5 Developersprefetch_policy=none
45210037SARM gem5 Developersprefetch_serial_squash=false
45310037SARM gem5 Developersprefetch_use_cpu_id=true
45410037SARM gem5 Developersprefetcher_size=100
45510037SARM gem5 DevelopersprioritizeRequests=false
45610037SARM gem5 Developersrepl=Null
45710037SARM gem5 Developerssize=2097152
45810037SARM gem5 Developerssubblock_size=0
45910037SARM gem5 Developerstgts_per_mshr=5
46010037SARM gem5 Developerstrace_addr=0
46110037SARM gem5 Developerstwo_queue=false
46210037SARM gem5 Developerswrite_buffers=8
46310037SARM gem5 Developerscpu_side=system.cpu.toL2Bus.port[2]
46410037SARM gem5 Developersmem_side=system.membus.port[1]
46510037SARM gem5 Developers
46610037SARM gem5 Developers[system.cpu.toL2Bus]
46710037SARM gem5 Developerstype=Bus
46810037SARM gem5 Developersblock_size=64
46910037SARM gem5 Developersbus_id=0
47010037SARM gem5 Developersclock=1000
47110037SARM gem5 Developersheader_cycles=1
47210037SARM gem5 Developersuse_default_range=false
47310037SARM gem5 Developerswidth=64
47410037SARM gem5 Developersport=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
47510037SARM gem5 Developers
47610037SARM gem5 Developers[system.cpu.tracer]
47710037SARM gem5 Developerstype=ExeTracer
47810037SARM gem5 Developers
47910037SARM gem5 Developers[system.cpu.workload]
48010037SARM gem5 Developerstype=LiveProcess
48110037SARM gem5 Developerscmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
48210037SARM gem5 Developerscwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
48310037SARM gem5 Developersegid=100
48410037SARM gem5 Developersenv=
48510037SARM gem5 Developerserrout=cerr
48610037SARM gem5 Developerseuid=100
48710037SARM gem5 Developersexecutable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/eon
48810037SARM gem5 Developersgid=100
48910037SARM gem5 Developersinput=cin
49010037SARM gem5 Developersmax_stack_size=67108864
49110037SARM gem5 Developersoutput=cout
49210037SARM gem5 Developerspid=100
49310037SARM gem5 Developersppid=99
49410037SARM gem5 Developerssimpoint=0
49510037SARM gem5 Developerssystem=system
49610037SARM gem5 Developersuid=100
49710037SARM gem5 Developers
49810037SARM gem5 Developers[system.membus]
49910037SARM gem5 Developerstype=Bus
50010037SARM gem5 Developersblock_size=64
50110037SARM gem5 Developersbus_id=0
50210037SARM gem5 Developersclock=1000
50310037SARM gem5 Developersheader_cycles=1
50410037SARM gem5 Developersuse_default_range=false
50510037SARM gem5 Developerswidth=64
50610037SARM gem5 Developersport=system.physmem.port[0] system.cpu.l2cache.mem_side
50710037SARM gem5 Developers
50810037SARM gem5 Developers[system.physmem]
50910037SARM gem5 Developerstype=PhysicalMemory
51010037SARM gem5 Developersfile=
51110037SARM gem5 Developerslatency=30000
51210037SARM gem5 Developerslatency_var=0
51310037SARM gem5 Developersnull=false
51410037SARM gem5 Developersrange=0:134217727
51510037SARM gem5 Developerszero=false
51610037SARM gem5 Developersport=system.membus.port[0]
51710037SARM gem5 Developers
51810037SARM gem5 Developers