stats.txt revision 11955:1170d039b31e
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.225185 # Number of seconds simulated 4sim_ticks 225184887000 # Number of ticks simulated 5final_tick 225184887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 292846 # Simulator instruction rate (inst/s) 8host_op_rate 351594 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 241521552 # Simulator tick rate (ticks/s) 10host_mem_usage 280036 # Number of bytes of host memory used 11host_seconds 932.36 # Real time elapsed on the host 12sim_insts 273037855 # Number of instructions simulated 13sim_ops 327812212 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory 19system.physmem.bytes_read::total 485504 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 972854 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 1183170 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2156024 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 972854 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 972854 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 972854 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 1183170 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2156024 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 7586 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 630 # Per bank write bursts 46system.physmem.perBankRdBursts::1 846 # Per bank write bursts 47system.physmem.perBankRdBursts::2 628 # Per bank write bursts 48system.physmem.perBankRdBursts::3 541 # Per bank write bursts 49system.physmem.perBankRdBursts::4 466 # Per bank write bursts 50system.physmem.perBankRdBursts::5 349 # Per bank write bursts 51system.physmem.perBankRdBursts::6 171 # Per bank write bursts 52system.physmem.perBankRdBursts::7 228 # Per bank write bursts 53system.physmem.perBankRdBursts::8 208 # Per bank write bursts 54system.physmem.perBankRdBursts::9 309 # Per bank write bursts 55system.physmem.perBankRdBursts::10 343 # Per bank write bursts 56system.physmem.perBankRdBursts::11 428 # Per bank write bursts 57system.physmem.perBankRdBursts::12 553 # Per bank write bursts 58system.physmem.perBankRdBursts::13 705 # Per bank write bursts 59system.physmem.perBankRdBursts::14 639 # Per bank write bursts 60system.physmem.perBankRdBursts::15 542 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 225184633000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 7586 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 6690 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 1509 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 321.017893 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 191.649066 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 328.624854 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 538 35.65% 35.65% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 351 23.26% 58.91% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 166 11.00% 69.91% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 79 5.24% 75.15% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 78 5.17% 80.32% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 56 3.71% 84.03% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 32 2.12% 86.15% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 36 2.39% 88.54% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 173 11.46% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1509 # Bytes accessed per row activation 204system.physmem.totQLat 232077250 # Total ticks spent queuing 205system.physmem.totMemAccLat 374314750 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 30592.84 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 49342.84 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.02 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 6074 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 29684238.47 # Average gap between requests 225system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 100520070 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 15505920 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 721291110 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 385301760 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 53419321200 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 54961303020 # Total energy per rank (pJ) 237system.physmem_0.averagePower 244.071899 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 224923904000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 29388000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 222338897000 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 1003385750 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 110367750 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 1581838500 # Time in different power states 245system.physmem_1.actEnergy 6069000 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 3221955 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 26610780 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 121194540 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 22344960 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 914224140 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 605228160 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 53190600045 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 55284153510 # Total energy per rank (pJ) 256system.physmem_1.averagePower 245.505612 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 224860041750 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 42127000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 221279795000 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 1576124250 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 114092500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 2004910250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 32421416 # Number of BP lookups 266system.cpu.branchPred.condPredicted 16919401 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 734831 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 17534346 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 12860140 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 73.342570 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 6521085 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 2302887 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 2263691 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 39196 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 128438 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 280system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 282system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 283system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 284system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 288system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 289system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 290system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 291system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 292system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 293system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 294system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 295system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 296system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 297system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 298system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 299system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 300system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 301system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 302system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 303system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 304system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 305system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 306system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 307system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 308system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 309system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 310system.cpu.dtb.walker.walks 0 # Table walker walks requested 311system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 318system.cpu.dtb.inst_hits 0 # ITB inst hits 319system.cpu.dtb.inst_misses 0 # ITB inst misses 320system.cpu.dtb.read_hits 0 # DTB read hits 321system.cpu.dtb.read_misses 0 # DTB read misses 322system.cpu.dtb.write_hits 0 # DTB write hits 323system.cpu.dtb.write_misses 0 # DTB write misses 324system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 325system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 326system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 327system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 328system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 329system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 330system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 331system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 332system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 333system.cpu.dtb.read_accesses 0 # DTB read accesses 334system.cpu.dtb.write_accesses 0 # DTB write accesses 335system.cpu.dtb.inst_accesses 0 # ITB inst accesses 336system.cpu.dtb.hits 0 # DTB hits 337system.cpu.dtb.misses 0 # DTB misses 338system.cpu.dtb.accesses 0 # DTB accesses 339system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 340system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 342system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 343system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 344system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 349system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 350system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 351system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 352system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 353system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 354system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 355system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 356system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 357system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 358system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 359system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 360system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 361system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 364system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 365system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 366system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 367system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 368system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 369system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 370system.cpu.itb.walker.walks 0 # Table walker walks requested 371system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.inst_hits 0 # ITB inst hits 379system.cpu.itb.inst_misses 0 # ITB inst misses 380system.cpu.itb.read_hits 0 # DTB read hits 381system.cpu.itb.read_misses 0 # DTB read misses 382system.cpu.itb.write_hits 0 # DTB write hits 383system.cpu.itb.write_misses 0 # DTB write misses 384system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 385system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 386system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 387system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 388system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 389system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 390system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 391system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 392system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu.itb.read_accesses 0 # DTB read accesses 394system.cpu.itb.write_accesses 0 # DTB write accesses 395system.cpu.itb.inst_accesses 0 # ITB inst accesses 396system.cpu.itb.hits 0 # DTB hits 397system.cpu.itb.misses 0 # DTB misses 398system.cpu.itb.accesses 0 # DTB accesses 399system.cpu.workload.numSyscalls 191 # Number of system calls 400system.cpu.pwrStateResidencyTicks::ON 225184887000 # Cumulative time (in ticks) in various power states 401system.cpu.numCycles 450369774 # number of cpu cycles simulated 402system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 403system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 404system.cpu.committedInsts 273037855 # Number of instructions committed 405system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed 406system.cpu.discardedOps 2044614 # Number of ops (including micro ops) which were discarded before commit 407system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 408system.cpu.cpi 1.649477 # CPI: cycles per instruction 409system.cpu.ipc 0.606253 # IPC: instructions per cycle 410system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 411system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction 412system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction 413system.cpu.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction 414system.cpu.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction 415system.cpu.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction 416system.cpu.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction 417system.cpu.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction 418system.cpu.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction 419system.cpu.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction 420system.cpu.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction 421system.cpu.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction 422system.cpu.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction 423system.cpu.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction 424system.cpu.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction 425system.cpu.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction 426system.cpu.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction 427system.cpu.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction 428system.cpu.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction 429system.cpu.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction 430system.cpu.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction 431system.cpu.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction 432system.cpu.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction 433system.cpu.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction 434system.cpu.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction 435system.cpu.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction 436system.cpu.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction 437system.cpu.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction 438system.cpu.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction 439system.cpu.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction 440system.cpu.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction 441system.cpu.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction 442system.cpu.op_class_0::MemRead 44185174 13.48% 62.20% # Class of committed instruction 443system.cpu.op_class_0::MemWrite 55008381 16.78% 78.98% # Class of committed instruction 444system.cpu.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction 445system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction 446system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 447system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 448system.cpu.op_class_0::total 327812212 # Class of committed instruction 449system.cpu.tickCycles 434912818 # Number of cycles that the object actually ticked 450system.cpu.idleCycles 15456956 # Total number of cycles that the object has spent stopped 451system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 452system.cpu.dcache.tags.replacements 1355 # number of replacements 453system.cpu.dcache.tags.tagsinuse 3085.765100 # Cycle average of tags in use 454system.cpu.dcache.tags.total_refs 168647477 # Total number of references to valid blocks. 455system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. 456system.cpu.dcache.tags.avg_refs 37377.543661 # Average number of references to valid blocks. 457system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 458system.cpu.dcache.tags.occ_blocks::cpu.data 3085.765100 # Average occupied blocks per requestor 459system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy 460system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy 461system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 462system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 463system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 464system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 465system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id 466system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id 467system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id 468system.cpu.dcache.tags.tag_accesses 337313356 # Number of tag accesses 469system.cpu.dcache.tags.data_accesses 337313356 # Number of data accesses 470system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 471system.cpu.dcache.ReadReq_hits::cpu.data 86514704 # number of ReadReq hits 472system.cpu.dcache.ReadReq_hits::total 86514704 # number of ReadReq hits 473system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits 474system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits 475system.cpu.dcache.SoftPFReq_hits::cpu.data 63536 # number of SoftPFReq hits 476system.cpu.dcache.SoftPFReq_hits::total 63536 # number of SoftPFReq hits 477system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 478system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 479system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 480system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 481system.cpu.dcache.demand_hits::cpu.data 168562151 # number of demand (read+write) hits 482system.cpu.dcache.demand_hits::total 168562151 # number of demand (read+write) hits 483system.cpu.dcache.overall_hits::cpu.data 168625687 # number of overall hits 484system.cpu.dcache.overall_hits::total 168625687 # number of overall hits 485system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses 486system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses 487system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses 488system.cpu.dcache.WriteReq_misses::total 5230 # number of WriteReq misses 489system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses 490system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses 491system.cpu.dcache.demand_misses::cpu.data 6940 # number of demand (read+write) misses 492system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses 493system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses 494system.cpu.dcache.overall_misses::total 6945 # number of overall misses 495system.cpu.dcache.ReadReq_miss_latency::cpu.data 177071500 # number of ReadReq miss cycles 496system.cpu.dcache.ReadReq_miss_latency::total 177071500 # number of ReadReq miss cycles 497system.cpu.dcache.WriteReq_miss_latency::cpu.data 487051000 # number of WriteReq miss cycles 498system.cpu.dcache.WriteReq_miss_latency::total 487051000 # number of WriteReq miss cycles 499system.cpu.dcache.demand_miss_latency::cpu.data 664122500 # number of demand (read+write) miss cycles 500system.cpu.dcache.demand_miss_latency::total 664122500 # number of demand (read+write) miss cycles 501system.cpu.dcache.overall_miss_latency::cpu.data 664122500 # number of overall miss cycles 502system.cpu.dcache.overall_miss_latency::total 664122500 # number of overall miss cycles 503system.cpu.dcache.ReadReq_accesses::cpu.data 86516414 # number of ReadReq accesses(hits+misses) 504system.cpu.dcache.ReadReq_accesses::total 86516414 # number of ReadReq accesses(hits+misses) 505system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 506system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 507system.cpu.dcache.SoftPFReq_accesses::cpu.data 63541 # number of SoftPFReq accesses(hits+misses) 508system.cpu.dcache.SoftPFReq_accesses::total 63541 # number of SoftPFReq accesses(hits+misses) 509system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 510system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 511system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 512system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 513system.cpu.dcache.demand_accesses::cpu.data 168569091 # number of demand (read+write) accesses 514system.cpu.dcache.demand_accesses::total 168569091 # number of demand (read+write) accesses 515system.cpu.dcache.overall_accesses::cpu.data 168632632 # number of overall (read+write) accesses 516system.cpu.dcache.overall_accesses::total 168632632 # number of overall (read+write) accesses 517system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses 518system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses 519system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses 520system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 521system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses 522system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses 523system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 # miss rate for demand accesses 524system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses 525system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses 526system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses 527system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103550.584795 # average ReadReq miss latency 528system.cpu.dcache.ReadReq_avg_miss_latency::total 103550.584795 # average ReadReq miss latency 529system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93126.386233 # average WriteReq miss latency 530system.cpu.dcache.WriteReq_avg_miss_latency::total 93126.386233 # average WriteReq miss latency 531system.cpu.dcache.demand_avg_miss_latency::cpu.data 95694.884726 # average overall miss latency 532system.cpu.dcache.demand_avg_miss_latency::total 95694.884726 # average overall miss latency 533system.cpu.dcache.overall_avg_miss_latency::cpu.data 95625.989921 # average overall miss latency 534system.cpu.dcache.overall_avg_miss_latency::total 95625.989921 # average overall miss latency 535system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 536system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 537system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 538system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 539system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 540system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 541system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks 542system.cpu.dcache.writebacks::total 1010 # number of writebacks 543system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits 544system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 545system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2360 # number of WriteReq MSHR hits 546system.cpu.dcache.WriteReq_mshr_hits::total 2360 # number of WriteReq MSHR hits 547system.cpu.dcache.demand_mshr_hits::cpu.data 2431 # number of demand (read+write) MSHR hits 548system.cpu.dcache.demand_mshr_hits::total 2431 # number of demand (read+write) MSHR hits 549system.cpu.dcache.overall_mshr_hits::cpu.data 2431 # number of overall MSHR hits 550system.cpu.dcache.overall_mshr_hits::total 2431 # number of overall MSHR hits 551system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1639 # number of ReadReq MSHR misses 552system.cpu.dcache.ReadReq_mshr_misses::total 1639 # number of ReadReq MSHR misses 553system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses 554system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses 555system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 556system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 557system.cpu.dcache.demand_mshr_misses::cpu.data 4509 # number of demand (read+write) MSHR misses 558system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses 559system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses 560system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses 561system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171838500 # number of ReadReq MSHR miss cycles 562system.cpu.dcache.ReadReq_mshr_miss_latency::total 171838500 # number of ReadReq MSHR miss cycles 563system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285292000 # number of WriteReq MSHR miss cycles 564system.cpu.dcache.WriteReq_mshr_miss_latency::total 285292000 # number of WriteReq MSHR miss cycles 565system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles 566system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles 567system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457130500 # number of demand (read+write) MSHR miss cycles 568system.cpu.dcache.demand_mshr_miss_latency::total 457130500 # number of demand (read+write) MSHR miss cycles 569system.cpu.dcache.overall_mshr_miss_latency::cpu.data 457389500 # number of overall MSHR miss cycles 570system.cpu.dcache.overall_mshr_miss_latency::total 457389500 # number of overall MSHR miss cycles 571system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses 572system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 573system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 574system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 575system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses 576system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses 577system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses 578system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 579system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses 580system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 581system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104843.502135 # average ReadReq mshr miss latency 582system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104843.502135 # average ReadReq mshr miss latency 583system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99404.878049 # average WriteReq mshr miss latency 584system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99404.878049 # average WriteReq mshr miss latency 585system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency 586system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency 587system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101381.791972 # average overall mshr miss latency 588system.cpu.dcache.demand_avg_mshr_miss_latency::total 101381.791972 # average overall mshr miss latency 589system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101371.786348 # average overall mshr miss latency 590system.cpu.dcache.overall_avg_mshr_miss_latency::total 101371.786348 # average overall mshr miss latency 591system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 592system.cpu.icache.tags.replacements 38251 # number of replacements 593system.cpu.icache.tags.tagsinuse 1924.799688 # Cycle average of tags in use 594system.cpu.icache.tags.total_refs 69805458 # Total number of references to valid blocks. 595system.cpu.icache.tags.sampled_refs 40188 # Sample count of references to valid blocks. 596system.cpu.icache.tags.avg_refs 1736.972678 # Average number of references to valid blocks. 597system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 598system.cpu.icache.tags.occ_blocks::cpu.inst 1924.799688 # Average occupied blocks per requestor 599system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy 600system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy 601system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id 602system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 603system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 604system.cpu.icache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 605system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id 606system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id 607system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id 608system.cpu.icache.tags.tag_accesses 139731482 # Number of tag accesses 609system.cpu.icache.tags.data_accesses 139731482 # Number of data accesses 610system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 611system.cpu.icache.ReadReq_hits::cpu.inst 69805458 # number of ReadReq hits 612system.cpu.icache.ReadReq_hits::total 69805458 # number of ReadReq hits 613system.cpu.icache.demand_hits::cpu.inst 69805458 # number of demand (read+write) hits 614system.cpu.icache.demand_hits::total 69805458 # number of demand (read+write) hits 615system.cpu.icache.overall_hits::cpu.inst 69805458 # number of overall hits 616system.cpu.icache.overall_hits::total 69805458 # number of overall hits 617system.cpu.icache.ReadReq_misses::cpu.inst 40189 # number of ReadReq misses 618system.cpu.icache.ReadReq_misses::total 40189 # number of ReadReq misses 619system.cpu.icache.demand_misses::cpu.inst 40189 # number of demand (read+write) misses 620system.cpu.icache.demand_misses::total 40189 # number of demand (read+write) misses 621system.cpu.icache.overall_misses::cpu.inst 40189 # number of overall misses 622system.cpu.icache.overall_misses::total 40189 # number of overall misses 623system.cpu.icache.ReadReq_miss_latency::cpu.inst 818936000 # number of ReadReq miss cycles 624system.cpu.icache.ReadReq_miss_latency::total 818936000 # number of ReadReq miss cycles 625system.cpu.icache.demand_miss_latency::cpu.inst 818936000 # number of demand (read+write) miss cycles 626system.cpu.icache.demand_miss_latency::total 818936000 # number of demand (read+write) miss cycles 627system.cpu.icache.overall_miss_latency::cpu.inst 818936000 # number of overall miss cycles 628system.cpu.icache.overall_miss_latency::total 818936000 # number of overall miss cycles 629system.cpu.icache.ReadReq_accesses::cpu.inst 69845647 # number of ReadReq accesses(hits+misses) 630system.cpu.icache.ReadReq_accesses::total 69845647 # number of ReadReq accesses(hits+misses) 631system.cpu.icache.demand_accesses::cpu.inst 69845647 # number of demand (read+write) accesses 632system.cpu.icache.demand_accesses::total 69845647 # number of demand (read+write) accesses 633system.cpu.icache.overall_accesses::cpu.inst 69845647 # number of overall (read+write) accesses 634system.cpu.icache.overall_accesses::total 69845647 # number of overall (read+write) accesses 635system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000575 # miss rate for ReadReq accesses 636system.cpu.icache.ReadReq_miss_rate::total 0.000575 # miss rate for ReadReq accesses 637system.cpu.icache.demand_miss_rate::cpu.inst 0.000575 # miss rate for demand accesses 638system.cpu.icache.demand_miss_rate::total 0.000575 # miss rate for demand accesses 639system.cpu.icache.overall_miss_rate::cpu.inst 0.000575 # miss rate for overall accesses 640system.cpu.icache.overall_miss_rate::total 0.000575 # miss rate for overall accesses 641system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20377.118117 # average ReadReq miss latency 642system.cpu.icache.ReadReq_avg_miss_latency::total 20377.118117 # average ReadReq miss latency 643system.cpu.icache.demand_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency 644system.cpu.icache.demand_avg_miss_latency::total 20377.118117 # average overall miss latency 645system.cpu.icache.overall_avg_miss_latency::cpu.inst 20377.118117 # average overall miss latency 646system.cpu.icache.overall_avg_miss_latency::total 20377.118117 # average overall miss latency 647system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 648system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 649system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 650system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 651system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 652system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 653system.cpu.icache.writebacks::writebacks 38251 # number of writebacks 654system.cpu.icache.writebacks::total 38251 # number of writebacks 655system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40189 # number of ReadReq MSHR misses 656system.cpu.icache.ReadReq_mshr_misses::total 40189 # number of ReadReq MSHR misses 657system.cpu.icache.demand_mshr_misses::cpu.inst 40189 # number of demand (read+write) MSHR misses 658system.cpu.icache.demand_mshr_misses::total 40189 # number of demand (read+write) MSHR misses 659system.cpu.icache.overall_mshr_misses::cpu.inst 40189 # number of overall MSHR misses 660system.cpu.icache.overall_mshr_misses::total 40189 # number of overall MSHR misses 661system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 778748000 # number of ReadReq MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_miss_latency::total 778748000 # number of ReadReq MSHR miss cycles 663system.cpu.icache.demand_mshr_miss_latency::cpu.inst 778748000 # number of demand (read+write) MSHR miss cycles 664system.cpu.icache.demand_mshr_miss_latency::total 778748000 # number of demand (read+write) MSHR miss cycles 665system.cpu.icache.overall_mshr_miss_latency::cpu.inst 778748000 # number of overall MSHR miss cycles 666system.cpu.icache.overall_mshr_miss_latency::total 778748000 # number of overall MSHR miss cycles 667system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for ReadReq accesses 668system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000575 # mshr miss rate for ReadReq accesses 669system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for demand accesses 670system.cpu.icache.demand_mshr_miss_rate::total 0.000575 # mshr miss rate for demand accesses 671system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000575 # mshr miss rate for overall accesses 672system.cpu.icache.overall_mshr_miss_rate::total 0.000575 # mshr miss rate for overall accesses 673system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19377.142999 # average ReadReq mshr miss latency 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19377.142999 # average ReadReq mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency 677system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency 679system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 680system.cpu.l2cache.tags.replacements 0 # number of replacements 681system.cpu.l2cache.tags.tagsinuse 6596.199570 # Cycle average of tags in use 682system.cpu.l2cache.tags.total_refs 61643 # Total number of references to valid blocks. 683system.cpu.l2cache.tags.sampled_refs 7586 # Sample count of references to valid blocks. 684system.cpu.l2cache.tags.avg_refs 8.125890 # Average number of references to valid blocks. 685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 686system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.827893 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.371677 # Average occupied blocks per requestor 688system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096674 # Average percentage of cache occupancy 689system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy 690system.cpu.l2cache.tags.occ_percent::total 0.201300 # Average percentage of cache occupancy 691system.cpu.l2cache.tags.occ_task_id_blocks::1024 7586 # Occupied blocks per task id 692system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 693system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id 695system.cpu.l2cache.tags.age_task_id_blocks_1024::3 788 # Occupied blocks per task id 696system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id 697system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231506 # Percentage of cache occupancy per task id 698system.cpu.l2cache.tags.tag_accesses 561762 # Number of tag accesses 699system.cpu.l2cache.tags.data_accesses 561762 # Number of data accesses 700system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 701system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits 702system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits 703system.cpu.l2cache.WritebackClean_hits::writebacks 23333 # number of WritebackClean hits 704system.cpu.l2cache.WritebackClean_hits::total 23333 # number of WritebackClean hits 705system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 706system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 707system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36764 # number of ReadCleanReq hits 708system.cpu.l2cache.ReadCleanReq_hits::total 36764 # number of ReadCleanReq hits 709system.cpu.l2cache.ReadSharedReq_hits::cpu.data 292 # number of ReadSharedReq hits 710system.cpu.l2cache.ReadSharedReq_hits::total 292 # number of ReadSharedReq hits 711system.cpu.l2cache.demand_hits::cpu.inst 36764 # number of demand (read+write) hits 712system.cpu.l2cache.demand_hits::cpu.data 308 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::total 37072 # number of demand (read+write) hits 714system.cpu.l2cache.overall_hits::cpu.inst 36764 # number of overall hits 715system.cpu.l2cache.overall_hits::cpu.data 308 # number of overall hits 716system.cpu.l2cache.overall_hits::total 37072 # number of overall hits 717system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses 718system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses 719system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3425 # number of ReadCleanReq misses 720system.cpu.l2cache.ReadCleanReq_misses::total 3425 # number of ReadCleanReq misses 721system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1350 # number of ReadSharedReq misses 722system.cpu.l2cache.ReadSharedReq_misses::total 1350 # number of ReadSharedReq misses 723system.cpu.l2cache.demand_misses::cpu.inst 3425 # number of demand (read+write) misses 724system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses 725system.cpu.l2cache.demand_misses::total 7629 # number of demand (read+write) misses 726system.cpu.l2cache.overall_misses::cpu.inst 3425 # number of overall misses 727system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses 728system.cpu.l2cache.overall_misses::total 7629 # number of overall misses 729system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 280789500 # number of ReadExReq miss cycles 730system.cpu.l2cache.ReadExReq_miss_latency::total 280789500 # number of ReadExReq miss cycles 731system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 317508500 # number of ReadCleanReq miss cycles 732system.cpu.l2cache.ReadCleanReq_miss_latency::total 317508500 # number of ReadCleanReq miss cycles 733system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 166371500 # number of ReadSharedReq miss cycles 734system.cpu.l2cache.ReadSharedReq_miss_latency::total 166371500 # number of ReadSharedReq miss cycles 735system.cpu.l2cache.demand_miss_latency::cpu.inst 317508500 # number of demand (read+write) miss cycles 736system.cpu.l2cache.demand_miss_latency::cpu.data 447161000 # number of demand (read+write) miss cycles 737system.cpu.l2cache.demand_miss_latency::total 764669500 # number of demand (read+write) miss cycles 738system.cpu.l2cache.overall_miss_latency::cpu.inst 317508500 # number of overall miss cycles 739system.cpu.l2cache.overall_miss_latency::cpu.data 447161000 # number of overall miss cycles 740system.cpu.l2cache.overall_miss_latency::total 764669500 # number of overall miss cycles 741system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses) 742system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses) 743system.cpu.l2cache.WritebackClean_accesses::writebacks 23333 # number of WritebackClean accesses(hits+misses) 744system.cpu.l2cache.WritebackClean_accesses::total 23333 # number of WritebackClean accesses(hits+misses) 745system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) 746system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) 747system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 40189 # number of ReadCleanReq accesses(hits+misses) 748system.cpu.l2cache.ReadCleanReq_accesses::total 40189 # number of ReadCleanReq accesses(hits+misses) 749system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1642 # number of ReadSharedReq accesses(hits+misses) 750system.cpu.l2cache.ReadSharedReq_accesses::total 1642 # number of ReadSharedReq accesses(hits+misses) 751system.cpu.l2cache.demand_accesses::cpu.inst 40189 # number of demand (read+write) accesses 752system.cpu.l2cache.demand_accesses::cpu.data 4512 # number of demand (read+write) accesses 753system.cpu.l2cache.demand_accesses::total 44701 # number of demand (read+write) accesses 754system.cpu.l2cache.overall_accesses::cpu.inst 40189 # number of overall (read+write) accesses 755system.cpu.l2cache.overall_accesses::cpu.data 4512 # number of overall (read+write) accesses 756system.cpu.l2cache.overall_accesses::total 44701 # number of overall (read+write) accesses 757system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses 758system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses 759system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.085222 # miss rate for ReadCleanReq accesses 760system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.085222 # miss rate for ReadCleanReq accesses 761system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822168 # miss rate for ReadSharedReq accesses 762system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822168 # miss rate for ReadSharedReq accesses 763system.cpu.l2cache.demand_miss_rate::cpu.inst 0.085222 # miss rate for demand accesses 764system.cpu.l2cache.demand_miss_rate::cpu.data 0.931738 # miss rate for demand accesses 765system.cpu.l2cache.demand_miss_rate::total 0.170667 # miss rate for demand accesses 766system.cpu.l2cache.overall_miss_rate::cpu.inst 0.085222 # miss rate for overall accesses 767system.cpu.l2cache.overall_miss_rate::cpu.data 0.931738 # miss rate for overall accesses 768system.cpu.l2cache.overall_miss_rate::total 0.170667 # miss rate for overall accesses 769system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98384.548003 # average ReadExReq miss latency 770system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98384.548003 # average ReadExReq miss latency 771system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92703.211679 # average ReadCleanReq miss latency 772system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92703.211679 # average ReadCleanReq miss latency 773system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123238.148148 # average ReadSharedReq miss latency 774system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123238.148148 # average ReadSharedReq miss latency 775system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency 776system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency 777system.cpu.l2cache.demand_avg_miss_latency::total 100231.943898 # average overall miss latency 778system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency 779system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency 780system.cpu.l2cache.overall_avg_miss_latency::total 100231.943898 # average overall miss latency 781system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 782system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 785system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 787system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 788system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 789system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 41 # number of ReadSharedReq MSHR hits 790system.cpu.l2cache.ReadSharedReq_mshr_hits::total 41 # number of ReadSharedReq MSHR hits 791system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 792system.cpu.l2cache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits 793system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits 794system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 795system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits 796system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits 797system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses 798system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses 799system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses 800system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses 801system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1309 # number of ReadSharedReq MSHR misses 802system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1309 # number of ReadSharedReq MSHR misses 803system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses 804system.cpu.l2cache.demand_mshr_misses::cpu.data 4163 # number of demand (read+write) MSHR misses 805system.cpu.l2cache.demand_mshr_misses::total 7586 # number of demand (read+write) MSHR misses 806system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses 807system.cpu.l2cache.overall_mshr_misses::cpu.data 4163 # number of overall MSHR misses 808system.cpu.l2cache.overall_mshr_misses::total 7586 # number of overall MSHR misses 809system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 252249500 # number of ReadExReq MSHR miss cycles 810system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 252249500 # number of ReadExReq MSHR miss cycles 811system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283130000 # number of ReadCleanReq MSHR miss cycles 812system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283130000 # number of ReadCleanReq MSHR miss cycles 813system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 150320500 # number of ReadSharedReq MSHR miss cycles 814system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150320500 # number of ReadSharedReq MSHR miss cycles 815system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283130000 # number of demand (read+write) MSHR miss cycles 816system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 402570000 # number of demand (read+write) MSHR miss cycles 817system.cpu.l2cache.demand_mshr_miss_latency::total 685700000 # number of demand (read+write) MSHR miss cycles 818system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283130000 # number of overall MSHR miss cycles 819system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 402570000 # number of overall MSHR miss cycles 820system.cpu.l2cache.overall_mshr_miss_latency::total 685700000 # number of overall MSHR miss cycles 821system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses 822system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses 823system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for ReadCleanReq accesses 824system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085173 # mshr miss rate for ReadCleanReq accesses 825system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses 826system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses 827system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for demand accesses 828system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses 829system.cpu.l2cache.demand_mshr_miss_rate::total 0.169705 # mshr miss rate for demand accesses 830system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for overall accesses 831system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses 832system.cpu.l2cache.overall_mshr_miss_rate::total 0.169705 # mshr miss rate for overall accesses 833system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88384.548003 # average ReadExReq mshr miss latency 834system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88384.548003 # average ReadExReq mshr miss latency 835system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82713.993573 # average ReadCleanReq mshr miss latency 836system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82713.993573 # average ReadCleanReq mshr miss latency 837system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114836.134454 # average ReadSharedReq mshr miss latency 838system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114836.134454 # average ReadSharedReq mshr miss latency 839system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency 840system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency 841system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency 842system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency 843system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency 844system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency 845system.cpu.toL2Bus.snoop_filter.tot_requests 84307 # Total number of requests made to the snoop filter. 846system.cpu.toL2Bus.snoop_filter.hit_single_requests 39708 # Number of requests hitting in the snoop filter with a single holder of the requested data. 847system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 848system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 849system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 850system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 851system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 852system.cpu.toL2Bus.trans_dist::ReadResp 41830 # Transaction distribution 853system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution 854system.cpu.toL2Bus.trans_dist::WritebackClean 38251 # Transaction distribution 855system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution 856system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution 857system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution 858system.cpu.toL2Bus.trans_dist::ReadCleanReq 40189 # Transaction distribution 859system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution 860system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118628 # Packet count per connected master and slave (bytes) 861system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes) 862system.cpu.toL2Bus.pkt_count::total 129007 # Packet count per connected master and slave (bytes) 863system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5020096 # Cumulative packet size per connected master and slave (bytes) 864system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes) 865system.cpu.toL2Bus.pkt_size::total 5373504 # Cumulative packet size per connected master and slave (bytes) 866system.cpu.toL2Bus.snoops 0 # Total snoops (count) 867system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 868system.cpu.toL2Bus.snoop_fanout::samples 44701 # Request fanout histogram 869system.cpu.toL2Bus.snoop_fanout::mean 0.338628 # Request fanout histogram 870system.cpu.toL2Bus.snoop_fanout::stdev 0.473248 # Request fanout histogram 871system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 872system.cpu.toL2Bus.snoop_fanout::0 29564 66.14% 66.14% # Request fanout histogram 873system.cpu.toL2Bus.snoop_fanout::1 15137 33.86% 100.00% # Request fanout histogram 874system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 875system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 876system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 877system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 878system.cpu.toL2Bus.snoop_fanout::total 44701 # Request fanout histogram 879system.cpu.toL2Bus.reqLayer0.occupancy 81414500 # Layer occupancy (ticks) 880system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 881system.cpu.toL2Bus.respLayer0.occupancy 60282998 # Layer occupancy (ticks) 882system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 883system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) 884system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 885system.membus.snoop_filter.tot_requests 7586 # Total number of requests made to the snoop filter. 886system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 887system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 888system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 889system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 890system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 891system.membus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states 892system.membus.trans_dist::ReadResp 4732 # Transaction distribution 893system.membus.trans_dist::ReadExReq 2854 # Transaction distribution 894system.membus.trans_dist::ReadExResp 2854 # Transaction distribution 895system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution 896system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) 897system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) 898system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) 899system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) 900system.membus.snoops 0 # Total snoops (count) 901system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 902system.membus.snoop_fanout::samples 7586 # Request fanout histogram 903system.membus.snoop_fanout::mean 0 # Request fanout histogram 904system.membus.snoop_fanout::stdev 0 # Request fanout histogram 905system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 906system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram 907system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 908system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 909system.membus.snoop_fanout::min_value 0 # Request fanout histogram 910system.membus.snoop_fanout::max_value 0 # Request fanout histogram 911system.membus.snoop_fanout::total 7586 # Request fanout histogram 912system.membus.reqLayer0.occupancy 9076000 # Layer occupancy (ticks) 913system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 914system.membus.respLayer1.occupancy 40293000 # Layer occupancy (ticks) 915system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 916 917---------- End Simulation Statistics ---------- 918