stats.txt revision 10409:8c80b91944c5
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.212377 # Number of seconds simulated 4sim_ticks 212377413000 # Number of ticks simulated 5final_tick 212377413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 164145 # Simulator instruction rate (inst/s) 8host_op_rate 197075 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 127677508 # Simulator tick rate (ticks/s) 10host_mem_usage 316656 # Number of bytes of host memory used 11host_seconds 1663.39 # Real time elapsed on the host 12sim_insts 273037856 # Number of instructions simulated 13sim_ops 327812213 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory 17system.physmem.bytes_read::total 485312 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory 20system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 2285139 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::total 2285139 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_inst_read::cpu.inst 1031221 # Instruction read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::total 1031221 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_total::cpu.inst 2285139 # Total bandwidth to/from this memory (bytes/s) 27system.physmem.bw_total::total 2285139 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.readReqs 7583 # Number of read requests accepted 29system.physmem.writeReqs 0 # Number of write requests accepted 30system.physmem.readBursts 7583 # Number of DRAM read bursts, including those serviced by the write queue 31system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 32system.physmem.bytesReadDRAM 485312 # Total number of bytes read from DRAM 33system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 34system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 35system.physmem.bytesReadSys 485312 # Total read bytes from the system interface side 36system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 37system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 38system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 39system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 40system.physmem.perBankRdBursts::0 630 # Per bank write bursts 41system.physmem.perBankRdBursts::1 843 # Per bank write bursts 42system.physmem.perBankRdBursts::2 628 # Per bank write bursts 43system.physmem.perBankRdBursts::3 541 # Per bank write bursts 44system.physmem.perBankRdBursts::4 466 # Per bank write bursts 45system.physmem.perBankRdBursts::5 349 # Per bank write bursts 46system.physmem.perBankRdBursts::6 173 # Per bank write bursts 47system.physmem.perBankRdBursts::7 228 # Per bank write bursts 48system.physmem.perBankRdBursts::8 209 # Per bank write bursts 49system.physmem.perBankRdBursts::9 310 # Per bank write bursts 50system.physmem.perBankRdBursts::10 342 # Per bank write bursts 51system.physmem.perBankRdBursts::11 428 # Per bank write bursts 52system.physmem.perBankRdBursts::12 554 # Per bank write bursts 53system.physmem.perBankRdBursts::13 705 # Per bank write bursts 54system.physmem.perBankRdBursts::14 637 # Per bank write bursts 55system.physmem.perBankRdBursts::15 540 # Per bank write bursts 56system.physmem.perBankWrBursts::0 0 # Per bank write bursts 57system.physmem.perBankWrBursts::1 0 # Per bank write bursts 58system.physmem.perBankWrBursts::2 0 # Per bank write bursts 59system.physmem.perBankWrBursts::3 0 # Per bank write bursts 60system.physmem.perBankWrBursts::4 0 # Per bank write bursts 61system.physmem.perBankWrBursts::5 0 # Per bank write bursts 62system.physmem.perBankWrBursts::6 0 # Per bank write bursts 63system.physmem.perBankWrBursts::7 0 # Per bank write bursts 64system.physmem.perBankWrBursts::8 0 # Per bank write bursts 65system.physmem.perBankWrBursts::9 0 # Per bank write bursts 66system.physmem.perBankWrBursts::10 0 # Per bank write bursts 67system.physmem.perBankWrBursts::11 0 # Per bank write bursts 68system.physmem.perBankWrBursts::12 0 # Per bank write bursts 69system.physmem.perBankWrBursts::13 0 # Per bank write bursts 70system.physmem.perBankWrBursts::14 0 # Per bank write bursts 71system.physmem.perBankWrBursts::15 0 # Per bank write bursts 72system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 73system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 74system.physmem.totGap 212377186000 # Total gap between requests 75system.physmem.readPktSize::0 0 # Read request sizes (log2) 76system.physmem.readPktSize::1 0 # Read request sizes (log2) 77system.physmem.readPktSize::2 0 # Read request sizes (log2) 78system.physmem.readPktSize::3 0 # Read request sizes (log2) 79system.physmem.readPktSize::4 0 # Read request sizes (log2) 80system.physmem.readPktSize::5 0 # Read request sizes (log2) 81system.physmem.readPktSize::6 7583 # Read request sizes (log2) 82system.physmem.writePktSize::0 0 # Write request sizes (log2) 83system.physmem.writePktSize::1 0 # Write request sizes (log2) 84system.physmem.writePktSize::2 0 # Write request sizes (log2) 85system.physmem.writePktSize::3 0 # Write request sizes (log2) 86system.physmem.writePktSize::4 0 # Write request sizes (log2) 87system.physmem.writePktSize::5 0 # Write request sizes (log2) 88system.physmem.writePktSize::6 0 # Write request sizes (log2) 89system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 121system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 185system.physmem.bytesPerActivate::samples 1498 # Bytes accessed per row activation 186system.physmem.bytesPerActivate::mean 322.691589 # Bytes accessed per row activation 187system.physmem.bytesPerActivate::gmean 189.527839 # Bytes accessed per row activation 188system.physmem.bytesPerActivate::stdev 333.553355 # Bytes accessed per row activation 189system.physmem.bytesPerActivate::0-127 554 36.98% 36.98% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::128-255 333 22.23% 59.21% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::256-383 160 10.68% 69.89% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::384-511 67 4.47% 74.37% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::512-639 72 4.81% 79.17% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::640-767 61 4.07% 83.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::768-895 43 2.87% 86.11% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::896-1023 33 2.20% 88.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1151 175 11.68% 100.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::total 1498 # Bytes accessed per row activation 199system.physmem.totQLat 52768250 # Total ticks spent queuing 200system.physmem.totMemAccLat 194949500 # Total ticks spent from burst creation until serviced by the DRAM 201system.physmem.totBusLat 37915000 # Total ticks spent in databus transfers 202system.physmem.avgQLat 6958.76 # Average queueing delay per DRAM burst 203system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 204system.physmem.avgMemAccLat 25708.76 # Average memory access latency per DRAM burst 205system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s 206system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 207system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s 208system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 209system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 210system.physmem.busUtil 0.02 # Data bus utilization in percentage 211system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 212system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 213system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 214system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 215system.physmem.readRowHits 6077 # Number of row buffer hits during reads 216system.physmem.writeRowHits 0 # Number of row buffer hits during writes 217system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads 218system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 219system.physmem.avgGap 28007013.85 # Average gap between requests 220system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined 221system.physmem.memoryStateTime::IDLE 202838268250 # Time in different power states 222system.physmem.memoryStateTime::REF 7091500000 # Time in different power states 223system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 224system.physmem.memoryStateTime::ACT 2441586750 # Time in different power states 225system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 226system.membus.trans_dist::ReadReq 4730 # Transaction distribution 227system.membus.trans_dist::ReadResp 4730 # Transaction distribution 228system.membus.trans_dist::ReadExReq 2853 # Transaction distribution 229system.membus.trans_dist::ReadExResp 2853 # Transaction distribution 230system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15166 # Packet count per connected master and slave (bytes) 231system.membus.pkt_count::total 15166 # Packet count per connected master and slave (bytes) 232system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485312 # Cumulative packet size per connected master and slave (bytes) 233system.membus.pkt_size::total 485312 # Cumulative packet size per connected master and slave (bytes) 234system.membus.snoops 0 # Total snoops (count) 235system.membus.snoop_fanout::samples 7583 # Request fanout histogram 236system.membus.snoop_fanout::mean 0 # Request fanout histogram 237system.membus.snoop_fanout::stdev 0 # Request fanout histogram 238system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 239system.membus.snoop_fanout::0 7583 100.00% 100.00% # Request fanout histogram 240system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 241system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 242system.membus.snoop_fanout::min_value 0 # Request fanout histogram 243system.membus.snoop_fanout::max_value 0 # Request fanout histogram 244system.membus.snoop_fanout::total 7583 # Request fanout histogram 245system.membus.reqLayer0.occupancy 8812500 # Layer occupancy (ticks) 246system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 247system.membus.respLayer1.occupancy 70869750 # Layer occupancy (ticks) 248system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 249system.cpu_clk_domain.clock 500 # Clock period in ticks 250system.cpu.branchPred.lookups 33146132 # Number of BP lookups 251system.cpu.branchPred.condPredicted 17115100 # Number of conditional branches predicted 252system.cpu.branchPred.condIncorrect 1582628 # Number of conditional branches incorrect 253system.cpu.branchPred.BTBLookups 18038080 # Number of BTB lookups 254system.cpu.branchPred.BTBHits 15622031 # Number of BTB hits 255system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 256system.cpu.branchPred.BTBHitPct 86.605842 # BTB Hit Percentage 257system.cpu.branchPred.usedRAS 6627212 # Number of times the RAS was used to get a target. 258system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 259system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 260system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 261system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 262system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 263system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 264system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 265system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 266system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 267system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 268system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 269system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 270system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 271system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 272system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 273system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 274system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 275system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 276system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 277system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 278system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 279system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 280system.cpu.dtb.inst_hits 0 # ITB inst hits 281system.cpu.dtb.inst_misses 0 # ITB inst misses 282system.cpu.dtb.read_hits 0 # DTB read hits 283system.cpu.dtb.read_misses 0 # DTB read misses 284system.cpu.dtb.write_hits 0 # DTB write hits 285system.cpu.dtb.write_misses 0 # DTB write misses 286system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 287system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 288system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 289system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 290system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 291system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 292system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 293system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 294system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 295system.cpu.dtb.read_accesses 0 # DTB read accesses 296system.cpu.dtb.write_accesses 0 # DTB write accesses 297system.cpu.dtb.inst_accesses 0 # ITB inst accesses 298system.cpu.dtb.hits 0 # DTB hits 299system.cpu.dtb.misses 0 # DTB misses 300system.cpu.dtb.accesses 0 # DTB accesses 301system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 302system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 303system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 304system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 305system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 306system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 307system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 308system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 309system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 310system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 311system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 312system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 313system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 314system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 315system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 316system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 317system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 318system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 319system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 320system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 321system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 322system.cpu.itb.inst_hits 0 # ITB inst hits 323system.cpu.itb.inst_misses 0 # ITB inst misses 324system.cpu.itb.read_hits 0 # DTB read hits 325system.cpu.itb.read_misses 0 # DTB read misses 326system.cpu.itb.write_hits 0 # DTB write hits 327system.cpu.itb.write_misses 0 # DTB write misses 328system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 329system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 330system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 331system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 332system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 333system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 334system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 335system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 336system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.itb.read_accesses 0 # DTB read accesses 338system.cpu.itb.write_accesses 0 # DTB write accesses 339system.cpu.itb.inst_accesses 0 # ITB inst accesses 340system.cpu.itb.hits 0 # DTB hits 341system.cpu.itb.misses 0 # DTB misses 342system.cpu.itb.accesses 0 # DTB accesses 343system.cpu.workload.num_syscalls 191 # Number of system calls 344system.cpu.numCycles 424754826 # number of cpu cycles simulated 345system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 346system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 347system.cpu.committedInsts 273037856 # Number of instructions committed 348system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed 349system.cpu.discardedOps 4318159 # Number of ops (including micro ops) which were discarded before commit 350system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 351system.cpu.cpi 1.555663 # CPI: cycles per instruction 352system.cpu.ipc 0.642813 # IPC: instructions per cycle 353system.cpu.tickCycles 420995875 # Number of cycles that the object actually ticked 354system.cpu.idleCycles 3758951 # Total number of cycles that the object has spent stopped 355system.cpu.icache.tags.replacements 36952 # number of replacements 356system.cpu.icache.tags.tagsinuse 1924.941243 # Cycle average of tags in use 357system.cpu.icache.tags.total_refs 73208046 # Total number of references to valid blocks. 358system.cpu.icache.tags.sampled_refs 38889 # Sample count of references to valid blocks. 359system.cpu.icache.tags.avg_refs 1882.487233 # Average number of references to valid blocks. 360system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 361system.cpu.icache.tags.occ_blocks::cpu.inst 1924.941243 # Average occupied blocks per requestor 362system.cpu.icache.tags.occ_percent::cpu.inst 0.939913 # Average percentage of cache occupancy 363system.cpu.icache.tags.occ_percent::total 0.939913 # Average percentage of cache occupancy 364system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id 365system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 366system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 367system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 368system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id 369system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id 370system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id 371system.cpu.icache.tags.tag_accesses 146532761 # Number of tag accesses 372system.cpu.icache.tags.data_accesses 146532761 # Number of data accesses 373system.cpu.icache.ReadReq_hits::cpu.inst 73208046 # number of ReadReq hits 374system.cpu.icache.ReadReq_hits::total 73208046 # number of ReadReq hits 375system.cpu.icache.demand_hits::cpu.inst 73208046 # number of demand (read+write) hits 376system.cpu.icache.demand_hits::total 73208046 # number of demand (read+write) hits 377system.cpu.icache.overall_hits::cpu.inst 73208046 # number of overall hits 378system.cpu.icache.overall_hits::total 73208046 # number of overall hits 379system.cpu.icache.ReadReq_misses::cpu.inst 38890 # number of ReadReq misses 380system.cpu.icache.ReadReq_misses::total 38890 # number of ReadReq misses 381system.cpu.icache.demand_misses::cpu.inst 38890 # number of demand (read+write) misses 382system.cpu.icache.demand_misses::total 38890 # number of demand (read+write) misses 383system.cpu.icache.overall_misses::cpu.inst 38890 # number of overall misses 384system.cpu.icache.overall_misses::total 38890 # number of overall misses 385system.cpu.icache.ReadReq_miss_latency::cpu.inst 705005996 # number of ReadReq miss cycles 386system.cpu.icache.ReadReq_miss_latency::total 705005996 # number of ReadReq miss cycles 387system.cpu.icache.demand_miss_latency::cpu.inst 705005996 # number of demand (read+write) miss cycles 388system.cpu.icache.demand_miss_latency::total 705005996 # number of demand (read+write) miss cycles 389system.cpu.icache.overall_miss_latency::cpu.inst 705005996 # number of overall miss cycles 390system.cpu.icache.overall_miss_latency::total 705005996 # number of overall miss cycles 391system.cpu.icache.ReadReq_accesses::cpu.inst 73246936 # number of ReadReq accesses(hits+misses) 392system.cpu.icache.ReadReq_accesses::total 73246936 # number of ReadReq accesses(hits+misses) 393system.cpu.icache.demand_accesses::cpu.inst 73246936 # number of demand (read+write) accesses 394system.cpu.icache.demand_accesses::total 73246936 # number of demand (read+write) accesses 395system.cpu.icache.overall_accesses::cpu.inst 73246936 # number of overall (read+write) accesses 396system.cpu.icache.overall_accesses::total 73246936 # number of overall (read+write) accesses 397system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000531 # miss rate for ReadReq accesses 398system.cpu.icache.ReadReq_miss_rate::total 0.000531 # miss rate for ReadReq accesses 399system.cpu.icache.demand_miss_rate::cpu.inst 0.000531 # miss rate for demand accesses 400system.cpu.icache.demand_miss_rate::total 0.000531 # miss rate for demand accesses 401system.cpu.icache.overall_miss_rate::cpu.inst 0.000531 # miss rate for overall accesses 402system.cpu.icache.overall_miss_rate::total 0.000531 # miss rate for overall accesses 403system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18128.207663 # average ReadReq miss latency 404system.cpu.icache.ReadReq_avg_miss_latency::total 18128.207663 # average ReadReq miss latency 405system.cpu.icache.demand_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency 406system.cpu.icache.demand_avg_miss_latency::total 18128.207663 # average overall miss latency 407system.cpu.icache.overall_avg_miss_latency::cpu.inst 18128.207663 # average overall miss latency 408system.cpu.icache.overall_avg_miss_latency::total 18128.207663 # average overall miss latency 409system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 415system.cpu.icache.fast_writes 0 # number of fast writes performed 416system.cpu.icache.cache_copies 0 # number of cache copies performed 417system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38890 # number of ReadReq MSHR misses 418system.cpu.icache.ReadReq_mshr_misses::total 38890 # number of ReadReq MSHR misses 419system.cpu.icache.demand_mshr_misses::cpu.inst 38890 # number of demand (read+write) MSHR misses 420system.cpu.icache.demand_mshr_misses::total 38890 # number of demand (read+write) MSHR misses 421system.cpu.icache.overall_mshr_misses::cpu.inst 38890 # number of overall MSHR misses 422system.cpu.icache.overall_mshr_misses::total 38890 # number of overall MSHR misses 423system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 625833004 # number of ReadReq MSHR miss cycles 424system.cpu.icache.ReadReq_mshr_miss_latency::total 625833004 # number of ReadReq MSHR miss cycles 425system.cpu.icache.demand_mshr_miss_latency::cpu.inst 625833004 # number of demand (read+write) MSHR miss cycles 426system.cpu.icache.demand_mshr_miss_latency::total 625833004 # number of demand (read+write) MSHR miss cycles 427system.cpu.icache.overall_mshr_miss_latency::cpu.inst 625833004 # number of overall MSHR miss cycles 428system.cpu.icache.overall_mshr_miss_latency::total 625833004 # number of overall MSHR miss cycles 429system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for ReadReq accesses 430system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000531 # mshr miss rate for ReadReq accesses 431system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for demand accesses 432system.cpu.icache.demand_mshr_miss_rate::total 0.000531 # mshr miss rate for demand accesses 433system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000531 # mshr miss rate for overall accesses 434system.cpu.icache.overall_mshr_miss_rate::total 0.000531 # mshr miss rate for overall accesses 435system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16092.388892 # average ReadReq mshr miss latency 436system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16092.388892 # average ReadReq mshr miss latency 437system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency 438system.cpu.icache.demand_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency 439system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16092.388892 # average overall mshr miss latency 440system.cpu.icache.overall_avg_mshr_miss_latency::total 16092.388892 # average overall mshr miss latency 441system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 442system.cpu.toL2Bus.trans_dist::ReadReq 40531 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadResp 40530 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::Writeback 1009 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::ReadExReq 2869 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadExResp 2869 # Transaction distribution 447system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77779 # Packet count per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10029 # Packet count per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_count::total 87808 # Packet count per connected master and slave (bytes) 450system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2488896 # Cumulative packet size per connected master and slave (bytes) 451system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353216 # Cumulative packet size per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_size::total 2842112 # Cumulative packet size per connected master and slave (bytes) 453system.cpu.toL2Bus.snoops 0 # Total snoops (count) 454system.cpu.toL2Bus.snoop_fanout::samples 44409 # Request fanout histogram 455system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 457system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 459system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 461system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 462system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 463system.cpu.toL2Bus.snoop_fanout::5 44409 100.00% 100.00% # Request fanout histogram 464system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 465system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 467system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 468system.cpu.toL2Bus.snoop_fanout::total 44409 # Request fanout histogram 469system.cpu.toL2Bus.reqLayer0.occupancy 23213500 # Layer occupancy (ticks) 470system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 471system.cpu.toL2Bus.respLayer0.occupancy 59030996 # Layer occupancy (ticks) 472system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 473system.cpu.toL2Bus.respLayer1.occupancy 7495960 # Layer occupancy (ticks) 474system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 475system.cpu.l2cache.tags.replacements 0 # number of replacements 476system.cpu.l2cache.tags.tagsinuse 4198.136942 # Cycle average of tags in use 477system.cpu.l2cache.tags.total_refs 35837 # Total number of references to valid blocks. 478system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks. 479system.cpu.l2cache.tags.avg_refs 6.349575 # Average number of references to valid blocks. 480system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 481system.cpu.l2cache.tags.occ_blocks::writebacks 353.492030 # Average occupied blocks per requestor 482system.cpu.l2cache.tags.occ_blocks::cpu.inst 3844.644913 # Average occupied blocks per requestor 483system.cpu.l2cache.tags.occ_percent::writebacks 0.010788 # Average percentage of cache occupancy 484system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117329 # Average percentage of cache occupancy 485system.cpu.l2cache.tags.occ_percent::total 0.128117 # Average percentage of cache occupancy 486system.cpu.l2cache.tags.occ_task_id_blocks::1024 5644 # Occupied blocks per task id 487system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 488system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 489system.cpu.l2cache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 490system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id 491system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id 492system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id 493system.cpu.l2cache.tags.tag_accesses 363785 # Number of tag accesses 494system.cpu.l2cache.tags.data_accesses 363785 # Number of data accesses 495system.cpu.l2cache.ReadReq_hits::cpu.inst 35758 # number of ReadReq hits 496system.cpu.l2cache.ReadReq_hits::total 35758 # number of ReadReq hits 497system.cpu.l2cache.Writeback_hits::writebacks 1009 # number of Writeback hits 498system.cpu.l2cache.Writeback_hits::total 1009 # number of Writeback hits 499system.cpu.l2cache.ReadExReq_hits::cpu.inst 16 # number of ReadExReq hits 500system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 501system.cpu.l2cache.demand_hits::cpu.inst 35774 # number of demand (read+write) hits 502system.cpu.l2cache.demand_hits::total 35774 # number of demand (read+write) hits 503system.cpu.l2cache.overall_hits::cpu.inst 35774 # number of overall hits 504system.cpu.l2cache.overall_hits::total 35774 # number of overall hits 505system.cpu.l2cache.ReadReq_misses::cpu.inst 4773 # number of ReadReq misses 506system.cpu.l2cache.ReadReq_misses::total 4773 # number of ReadReq misses 507system.cpu.l2cache.ReadExReq_misses::cpu.inst 2853 # number of ReadExReq misses 508system.cpu.l2cache.ReadExReq_misses::total 2853 # number of ReadExReq misses 509system.cpu.l2cache.demand_misses::cpu.inst 7626 # number of demand (read+write) misses 510system.cpu.l2cache.demand_misses::total 7626 # number of demand (read+write) misses 511system.cpu.l2cache.overall_misses::cpu.inst 7626 # number of overall misses 512system.cpu.l2cache.overall_misses::total 7626 # number of overall misses 513system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 328394750 # number of ReadReq miss cycles 514system.cpu.l2cache.ReadReq_miss_latency::total 328394750 # number of ReadReq miss cycles 515system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 194183750 # number of ReadExReq miss cycles 516system.cpu.l2cache.ReadExReq_miss_latency::total 194183750 # number of ReadExReq miss cycles 517system.cpu.l2cache.demand_miss_latency::cpu.inst 522578500 # number of demand (read+write) miss cycles 518system.cpu.l2cache.demand_miss_latency::total 522578500 # number of demand (read+write) miss cycles 519system.cpu.l2cache.overall_miss_latency::cpu.inst 522578500 # number of overall miss cycles 520system.cpu.l2cache.overall_miss_latency::total 522578500 # number of overall miss cycles 521system.cpu.l2cache.ReadReq_accesses::cpu.inst 40531 # number of ReadReq accesses(hits+misses) 522system.cpu.l2cache.ReadReq_accesses::total 40531 # number of ReadReq accesses(hits+misses) 523system.cpu.l2cache.Writeback_accesses::writebacks 1009 # number of Writeback accesses(hits+misses) 524system.cpu.l2cache.Writeback_accesses::total 1009 # number of Writeback accesses(hits+misses) 525system.cpu.l2cache.ReadExReq_accesses::cpu.inst 2869 # number of ReadExReq accesses(hits+misses) 526system.cpu.l2cache.ReadExReq_accesses::total 2869 # number of ReadExReq accesses(hits+misses) 527system.cpu.l2cache.demand_accesses::cpu.inst 43400 # number of demand (read+write) accesses 528system.cpu.l2cache.demand_accesses::total 43400 # number of demand (read+write) accesses 529system.cpu.l2cache.overall_accesses::cpu.inst 43400 # number of overall (read+write) accesses 530system.cpu.l2cache.overall_accesses::total 43400 # number of overall (read+write) accesses 531system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.117762 # miss rate for ReadReq accesses 532system.cpu.l2cache.ReadReq_miss_rate::total 0.117762 # miss rate for ReadReq accesses 533system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.994423 # miss rate for ReadExReq accesses 534system.cpu.l2cache.ReadExReq_miss_rate::total 0.994423 # miss rate for ReadExReq accesses 535system.cpu.l2cache.demand_miss_rate::cpu.inst 0.175714 # miss rate for demand accesses 536system.cpu.l2cache.demand_miss_rate::total 0.175714 # miss rate for demand accesses 537system.cpu.l2cache.overall_miss_rate::cpu.inst 0.175714 # miss rate for overall accesses 538system.cpu.l2cache.overall_miss_rate::total 0.175714 # miss rate for overall accesses 539system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68802.587471 # average ReadReq miss latency 540system.cpu.l2cache.ReadReq_avg_miss_latency::total 68802.587471 # average ReadReq miss latency 541system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68063.003856 # average ReadExReq miss latency 542system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68063.003856 # average ReadExReq miss latency 543system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency 544system.cpu.l2cache.demand_avg_miss_latency::total 68525.898243 # average overall miss latency 545system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68525.898243 # average overall miss latency 546system.cpu.l2cache.overall_avg_miss_latency::total 68525.898243 # average overall miss latency 547system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.l2cache.fast_writes 0 # number of fast writes performed 554system.cpu.l2cache.cache_copies 0 # number of cache copies performed 555system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 43 # number of ReadReq MSHR hits 556system.cpu.l2cache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits 557system.cpu.l2cache.demand_mshr_hits::cpu.inst 43 # number of demand (read+write) MSHR hits 558system.cpu.l2cache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits 559system.cpu.l2cache.overall_mshr_hits::cpu.inst 43 # number of overall MSHR hits 560system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits 561system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4730 # number of ReadReq MSHR misses 562system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses 563system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 2853 # number of ReadExReq MSHR misses 564system.cpu.l2cache.ReadExReq_mshr_misses::total 2853 # number of ReadExReq MSHR misses 565system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses 566system.cpu.l2cache.demand_mshr_misses::total 7583 # number of demand (read+write) MSHR misses 567system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses 568system.cpu.l2cache.overall_mshr_misses::total 7583 # number of overall MSHR misses 569system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266721500 # number of ReadReq MSHR miss cycles 570system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266721500 # number of ReadReq MSHR miss cycles 571system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 158370750 # number of ReadExReq MSHR miss cycles 572system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158370750 # number of ReadExReq MSHR miss cycles 573system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 425092250 # number of demand (read+write) MSHR miss cycles 574system.cpu.l2cache.demand_mshr_miss_latency::total 425092250 # number of demand (read+write) MSHR miss cycles 575system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 425092250 # number of overall MSHR miss cycles 576system.cpu.l2cache.overall_mshr_miss_latency::total 425092250 # number of overall MSHR miss cycles 577system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.116701 # mshr miss rate for ReadReq accesses 578system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116701 # mshr miss rate for ReadReq accesses 579system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.994423 # mshr miss rate for ReadExReq accesses 580system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994423 # mshr miss rate for ReadExReq accesses 581system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for demand accesses 582system.cpu.l2cache.demand_mshr_miss_rate::total 0.174724 # mshr miss rate for demand accesses 583system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.174724 # mshr miss rate for overall accesses 584system.cpu.l2cache.overall_mshr_miss_rate::total 0.174724 # mshr miss rate for overall accesses 585system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56389.323467 # average ReadReq mshr miss latency 586system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56389.323467 # average ReadReq mshr miss latency 587system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55510.252366 # average ReadExReq mshr miss latency 588system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55510.252366 # average ReadExReq mshr miss latency 589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency 590system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency 591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56058.584993 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56058.584993 # average overall mshr miss latency 593system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 594system.cpu.dcache.tags.replacements 1353 # number of replacements 595system.cpu.dcache.tags.tagsinuse 3085.890938 # Cycle average of tags in use 596system.cpu.dcache.tags.total_refs 168774540 # Total number of references to valid blocks. 597system.cpu.dcache.tags.sampled_refs 4510 # Sample count of references to valid blocks. 598system.cpu.dcache.tags.avg_refs 37422.292683 # Average number of references to valid blocks. 599system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 600system.cpu.dcache.tags.occ_blocks::cpu.inst 3085.890938 # Average occupied blocks per requestor 601system.cpu.dcache.tags.occ_percent::cpu.inst 0.753391 # Average percentage of cache occupancy 602system.cpu.dcache.tags.occ_percent::total 0.753391 # Average percentage of cache occupancy 603system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id 604system.cpu.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 605system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 606system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 607system.cpu.dcache.tags.age_task_id_blocks_1024::3 671 # Occupied blocks per task id 608system.cpu.dcache.tags.age_task_id_blocks_1024::4 2433 # Occupied blocks per task id 609system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id 610system.cpu.dcache.tags.tag_accesses 337568172 # Number of tag accesses 611system.cpu.dcache.tags.data_accesses 337568172 # Number of data accesses 612system.cpu.dcache.ReadReq_hits::cpu.inst 86705299 # number of ReadReq hits 613system.cpu.dcache.ReadReq_hits::total 86705299 # number of ReadReq hits 614system.cpu.dcache.WriteReq_hits::cpu.inst 82047451 # number of WriteReq hits 615system.cpu.dcache.WriteReq_hits::total 82047451 # number of WriteReq hits 616system.cpu.dcache.LoadLockedReq_hits::cpu.inst 10895 # number of LoadLockedReq hits 617system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 618system.cpu.dcache.StoreCondReq_hits::cpu.inst 10895 # number of StoreCondReq hits 619system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 620system.cpu.dcache.demand_hits::cpu.inst 168752750 # number of demand (read+write) hits 621system.cpu.dcache.demand_hits::total 168752750 # number of demand (read+write) hits 622system.cpu.dcache.overall_hits::cpu.inst 168752750 # number of overall hits 623system.cpu.dcache.overall_hits::total 168752750 # number of overall hits 624system.cpu.dcache.ReadReq_misses::cpu.inst 2065 # number of ReadReq misses 625system.cpu.dcache.ReadReq_misses::total 2065 # number of ReadReq misses 626system.cpu.dcache.WriteReq_misses::cpu.inst 5226 # number of WriteReq misses 627system.cpu.dcache.WriteReq_misses::total 5226 # number of WriteReq misses 628system.cpu.dcache.demand_misses::cpu.inst 7291 # number of demand (read+write) misses 629system.cpu.dcache.demand_misses::total 7291 # number of demand (read+write) misses 630system.cpu.dcache.overall_misses::cpu.inst 7291 # number of overall misses 631system.cpu.dcache.overall_misses::total 7291 # number of overall misses 632system.cpu.dcache.ReadReq_miss_latency::cpu.inst 127168958 # number of ReadReq miss cycles 633system.cpu.dcache.ReadReq_miss_latency::total 127168958 # number of ReadReq miss cycles 634system.cpu.dcache.WriteReq_miss_latency::cpu.inst 358839500 # number of WriteReq miss cycles 635system.cpu.dcache.WriteReq_miss_latency::total 358839500 # number of WriteReq miss cycles 636system.cpu.dcache.demand_miss_latency::cpu.inst 486008458 # number of demand (read+write) miss cycles 637system.cpu.dcache.demand_miss_latency::total 486008458 # number of demand (read+write) miss cycles 638system.cpu.dcache.overall_miss_latency::cpu.inst 486008458 # number of overall miss cycles 639system.cpu.dcache.overall_miss_latency::total 486008458 # number of overall miss cycles 640system.cpu.dcache.ReadReq_accesses::cpu.inst 86707364 # number of ReadReq accesses(hits+misses) 641system.cpu.dcache.ReadReq_accesses::total 86707364 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.WriteReq_accesses::cpu.inst 82052677 # number of WriteReq accesses(hits+misses) 643system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 10895 # number of LoadLockedReq accesses(hits+misses) 645system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 646system.cpu.dcache.StoreCondReq_accesses::cpu.inst 10895 # number of StoreCondReq accesses(hits+misses) 647system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 648system.cpu.dcache.demand_accesses::cpu.inst 168760041 # number of demand (read+write) accesses 649system.cpu.dcache.demand_accesses::total 168760041 # number of demand (read+write) accesses 650system.cpu.dcache.overall_accesses::cpu.inst 168760041 # number of overall (read+write) accesses 651system.cpu.dcache.overall_accesses::total 168760041 # number of overall (read+write) accesses 652system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000024 # miss rate for ReadReq accesses 653system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses 654system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000064 # miss rate for WriteReq accesses 655system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses 656system.cpu.dcache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses 657system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses 658system.cpu.dcache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses 659system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses 660system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61583.030508 # average ReadReq miss latency 661system.cpu.dcache.ReadReq_avg_miss_latency::total 61583.030508 # average ReadReq miss latency 662system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68664.274780 # average WriteReq miss latency 663system.cpu.dcache.WriteReq_avg_miss_latency::total 68664.274780 # average WriteReq miss latency 664system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency 665system.cpu.dcache.demand_avg_miss_latency::total 66658.683034 # average overall miss latency 666system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66658.683034 # average overall miss latency 667system.cpu.dcache.overall_avg_miss_latency::total 66658.683034 # average overall miss latency 668system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 669system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu.dcache.fast_writes 0 # number of fast writes performed 675system.cpu.dcache.cache_copies 0 # number of cache copies performed 676system.cpu.dcache.writebacks::writebacks 1009 # number of writebacks 677system.cpu.dcache.writebacks::total 1009 # number of writebacks 678system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits 679system.cpu.dcache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits 680system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2357 # number of WriteReq MSHR hits 681system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits 682system.cpu.dcache.demand_mshr_hits::cpu.inst 2781 # number of demand (read+write) MSHR hits 683system.cpu.dcache.demand_mshr_hits::total 2781 # number of demand (read+write) MSHR hits 684system.cpu.dcache.overall_mshr_hits::cpu.inst 2781 # number of overall MSHR hits 685system.cpu.dcache.overall_mshr_hits::total 2781 # number of overall MSHR hits 686system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1641 # number of ReadReq MSHR misses 687system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses 688system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 2869 # number of WriteReq MSHR misses 689system.cpu.dcache.WriteReq_mshr_misses::total 2869 # number of WriteReq MSHR misses 690system.cpu.dcache.demand_mshr_misses::cpu.inst 4510 # number of demand (read+write) MSHR misses 691system.cpu.dcache.demand_mshr_misses::total 4510 # number of demand (read+write) MSHR misses 692system.cpu.dcache.overall_mshr_misses::cpu.inst 4510 # number of overall MSHR misses 693system.cpu.dcache.overall_mshr_misses::total 4510 # number of overall MSHR misses 694system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 100686290 # number of ReadReq MSHR miss cycles 695system.cpu.dcache.ReadReq_mshr_miss_latency::total 100686290 # number of ReadReq MSHR miss cycles 696system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 197251750 # number of WriteReq MSHR miss cycles 697system.cpu.dcache.WriteReq_mshr_miss_latency::total 197251750 # number of WriteReq MSHR miss cycles 698system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 297938040 # number of demand (read+write) MSHR miss cycles 699system.cpu.dcache.demand_mshr_miss_latency::total 297938040 # number of demand (read+write) MSHR miss cycles 700system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 297938040 # number of overall MSHR miss cycles 701system.cpu.dcache.overall_mshr_miss_latency::total 297938040 # number of overall MSHR miss cycles 702system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000019 # mshr miss rate for ReadReq accesses 703system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses 704system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000035 # mshr miss rate for WriteReq accesses 705system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 706system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses 707system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses 708system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses 709system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses 710system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61356.666667 # average ReadReq mshr miss latency 711system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61356.666667 # average ReadReq mshr miss latency 712system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68752.788428 # average WriteReq mshr miss latency 713system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68752.788428 # average WriteReq mshr miss latency 714system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency 715system.cpu.dcache.demand_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency 716system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66061.649667 # average overall mshr miss latency 717system.cpu.dcache.overall_avg_mshr_miss_latency::total 66061.649667 # average overall mshr miss latency 718system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 719 720---------- End Simulation Statistics ---------- 721