stats.txt revision 8983:8800b05e1cb3
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.658730 # Number of seconds simulated 4sim_ticks 1658729604000 # Number of ticks simulated 5final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 332704 # Simulator instruction rate (inst/s) 8host_op_rate 615206 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 667409022 # Simulator tick rate (ticks/s) 10host_mem_usage 228396 # Number of bytes of host memory used 11host_seconds 2485.33 # Real time elapsed on the host 12sim_insts 826877145 # Number of instructions simulated 13sim_ops 1528988757 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 37094976 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 148544 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 26349376 # Number of bytes written to this memory 17system.physmem.num_reads 579609 # Number of read requests responded to by this memory 18system.physmem.num_writes 411709 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 22363486 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 89553 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 15885275 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 38248761 # Total bandwidth to/from this memory (bytes/s) 24system.cpu.workload.num_syscalls 551 # Number of system calls 25system.cpu.numCycles 3317459208 # number of cpu cycles simulated 26system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 27system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 28system.cpu.committedInsts 826877145 # Number of instructions committed 29system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed 30system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses 31system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 32system.cpu.num_func_calls 0 # number of times a function call or return occured 33system.cpu.num_conditional_control_insts 92658800 # number of instructions that are conditional controls 34system.cpu.num_int_insts 1528317615 # number of integer instructions 35system.cpu.num_fp_insts 0 # number of float instructions 36system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read 37system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written 38system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 39system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 40system.cpu.num_mem_refs 533262345 # number of memory refs 41system.cpu.num_load_insts 384102160 # Number of load instructions 42system.cpu.num_store_insts 149160185 # Number of store instructions 43system.cpu.num_idle_cycles 0 # Number of idle cycles 44system.cpu.num_busy_cycles 3317459208 # Number of busy cycles 45system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 46system.cpu.idle_fraction 0 # Percentage of idle cycles 47system.cpu.icache.replacements 1253 # number of replacements 48system.cpu.icache.tagsinuse 882.231489 # Cycle average of tags in use 49system.cpu.icache.total_refs 1068344296 # Total number of references to valid blocks. 50system.cpu.icache.sampled_refs 2814 # Sample count of references to valid blocks. 51system.cpu.icache.avg_refs 379653.267946 # Average number of references to valid blocks. 52system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 53system.cpu.icache.occ_blocks::cpu.inst 882.231489 # Average occupied blocks per requestor 54system.cpu.icache.occ_percent::cpu.inst 0.430777 # Average percentage of cache occupancy 55system.cpu.icache.occ_percent::total 0.430777 # Average percentage of cache occupancy 56system.cpu.icache.ReadReq_hits::cpu.inst 1068344296 # number of ReadReq hits 57system.cpu.icache.ReadReq_hits::total 1068344296 # number of ReadReq hits 58system.cpu.icache.demand_hits::cpu.inst 1068344296 # number of demand (read+write) hits 59system.cpu.icache.demand_hits::total 1068344296 # number of demand (read+write) hits 60system.cpu.icache.overall_hits::cpu.inst 1068344296 # number of overall hits 61system.cpu.icache.overall_hits::total 1068344296 # number of overall hits 62system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 63system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 64system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 65system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 66system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 67system.cpu.icache.overall_misses::total 2814 # number of overall misses 68system.cpu.icache.ReadReq_miss_latency::cpu.inst 136878000 # number of ReadReq miss cycles 69system.cpu.icache.ReadReq_miss_latency::total 136878000 # number of ReadReq miss cycles 70system.cpu.icache.demand_miss_latency::cpu.inst 136878000 # number of demand (read+write) miss cycles 71system.cpu.icache.demand_miss_latency::total 136878000 # number of demand (read+write) miss cycles 72system.cpu.icache.overall_miss_latency::cpu.inst 136878000 # number of overall miss cycles 73system.cpu.icache.overall_miss_latency::total 136878000 # number of overall miss cycles 74system.cpu.icache.ReadReq_accesses::cpu.inst 1068347110 # number of ReadReq accesses(hits+misses) 75system.cpu.icache.ReadReq_accesses::total 1068347110 # number of ReadReq accesses(hits+misses) 76system.cpu.icache.demand_accesses::cpu.inst 1068347110 # number of demand (read+write) accesses 77system.cpu.icache.demand_accesses::total 1068347110 # number of demand (read+write) accesses 78system.cpu.icache.overall_accesses::cpu.inst 1068347110 # number of overall (read+write) accesses 79system.cpu.icache.overall_accesses::total 1068347110 # number of overall (read+write) accesses 80system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 81system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 82system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 83system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045 # average ReadReq miss latency 84system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency 85system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045 # average overall miss latency 86system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 88system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 90system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92system.cpu.icache.fast_writes 0 # number of fast writes performed 93system.cpu.icache.cache_copies 0 # number of cache copies performed 94system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 95system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 96system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 97system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 98system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 99system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses 100system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128436000 # number of ReadReq MSHR miss cycles 101system.cpu.icache.ReadReq_mshr_miss_latency::total 128436000 # number of ReadReq MSHR miss cycles 102system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128436000 # number of demand (read+write) MSHR miss cycles 103system.cpu.icache.demand_mshr_miss_latency::total 128436000 # number of demand (read+write) MSHR miss cycles 104system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128436000 # number of overall MSHR miss cycles 105system.cpu.icache.overall_mshr_miss_latency::total 128436000 # number of overall MSHR miss cycles 106system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 107system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 108system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 109system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045 # average ReadReq mshr miss latency 110system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency 111system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045 # average overall mshr miss latency 112system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 113system.cpu.dcache.replacements 2514362 # number of replacements 114system.cpu.dcache.tagsinuse 4086.472055 # Cycle average of tags in use 115system.cpu.dcache.total_refs 530743932 # Total number of references to valid blocks. 116system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks. 117system.cpu.dcache.avg_refs 210.741625 # Average number of references to valid blocks. 118system.cpu.dcache.warmup_cycle 8216675000 # Cycle when the warmup percentage was hit. 119system.cpu.dcache.occ_blocks::cpu.data 4086.472055 # Average occupied blocks per requestor 120system.cpu.dcache.occ_percent::cpu.data 0.997674 # Average percentage of cache occupancy 121system.cpu.dcache.occ_percent::total 0.997674 # Average percentage of cache occupancy 122system.cpu.dcache.ReadReq_hits::cpu.data 382374775 # number of ReadReq hits 123system.cpu.dcache.ReadReq_hits::total 382374775 # number of ReadReq hits 124system.cpu.dcache.WriteReq_hits::cpu.data 148369157 # number of WriteReq hits 125system.cpu.dcache.WriteReq_hits::total 148369157 # number of WriteReq hits 126system.cpu.dcache.demand_hits::cpu.data 530743932 # number of demand (read+write) hits 127system.cpu.dcache.demand_hits::total 530743932 # number of demand (read+write) hits 128system.cpu.dcache.overall_hits::cpu.data 530743932 # number of overall hits 129system.cpu.dcache.overall_hits::total 530743932 # number of overall hits 130system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses 131system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses 132system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses 133system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses 134system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses 135system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses 136system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses 137system.cpu.dcache.overall_misses::total 2518458 # number of overall misses 138system.cpu.dcache.ReadReq_miss_latency::cpu.data 38012508000 # number of ReadReq miss cycles 139system.cpu.dcache.ReadReq_miss_latency::total 38012508000 # number of ReadReq miss cycles 140system.cpu.dcache.WriteReq_miss_latency::cpu.data 21492013500 # number of WriteReq miss cycles 141system.cpu.dcache.WriteReq_miss_latency::total 21492013500 # number of WriteReq miss cycles 142system.cpu.dcache.demand_miss_latency::cpu.data 59504521500 # number of demand (read+write) miss cycles 143system.cpu.dcache.demand_miss_latency::total 59504521500 # number of demand (read+write) miss cycles 144system.cpu.dcache.overall_miss_latency::cpu.data 59504521500 # number of overall miss cycles 145system.cpu.dcache.overall_miss_latency::total 59504521500 # number of overall miss cycles 146system.cpu.dcache.ReadReq_accesses::cpu.data 384102189 # number of ReadReq accesses(hits+misses) 147system.cpu.dcache.ReadReq_accesses::total 384102189 # number of ReadReq accesses(hits+misses) 148system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 149system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 150system.cpu.dcache.demand_accesses::cpu.data 533262390 # number of demand (read+write) accesses 151system.cpu.dcache.demand_accesses::total 533262390 # number of demand (read+write) accesses 152system.cpu.dcache.overall_accesses::cpu.data 533262390 # number of overall (read+write) accesses 153system.cpu.dcache.overall_accesses::total 533262390 # number of overall (read+write) accesses 154system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses 155system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses 156system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses 157system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses 158system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660 # average ReadReq miss latency 159system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798 # average WriteReq miss latency 160system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency 161system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053 # average overall miss latency 162system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 163system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 164system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 165system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 166system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 167system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 168system.cpu.dcache.fast_writes 0 # number of fast writes performed 169system.cpu.dcache.cache_copies 0 # number of cache copies performed 170system.cpu.dcache.writebacks::writebacks 2223170 # number of writebacks 171system.cpu.dcache.writebacks::total 2223170 # number of writebacks 172system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses 173system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses 174system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses 175system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses 176system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses 177system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses 178system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses 179system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses 180system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32830264000 # number of ReadReq MSHR miss cycles 181system.cpu.dcache.ReadReq_mshr_miss_latency::total 32830264000 # number of ReadReq MSHR miss cycles 182system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19118876000 # number of WriteReq MSHR miss cycles 183system.cpu.dcache.WriteReq_mshr_miss_latency::total 19118876000 # number of WriteReq MSHR miss cycles 184system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51949140000 # number of demand (read+write) MSHR miss cycles 185system.cpu.dcache.demand_mshr_miss_latency::total 51949140000 # number of demand (read+write) MSHR miss cycles 186system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51949140000 # number of overall MSHR miss cycles 187system.cpu.dcache.overall_mshr_miss_latency::total 51949140000 # number of overall MSHR miss cycles 188system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses 189system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses 190system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses 191system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses 192system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502 # average ReadReq mshr miss latency 193system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845 # average WriteReq mshr miss latency 194system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency 195system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075 # average overall mshr miss latency 196system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 197system.cpu.l2cache.replacements 568906 # number of replacements 198system.cpu.l2cache.tagsinuse 21228.193311 # Cycle average of tags in use 199system.cpu.l2cache.total_refs 3146531 # Total number of references to valid blocks. 200system.cpu.l2cache.sampled_refs 587958 # Sample count of references to valid blocks. 201system.cpu.l2cache.avg_refs 5.351625 # Average number of references to valid blocks. 202system.cpu.l2cache.warmup_cycle 896565143000 # Cycle when the warmup percentage was hit. 203system.cpu.l2cache.occ_blocks::writebacks 13679.064710 # Average occupied blocks per requestor 204system.cpu.l2cache.occ_blocks::cpu.inst 30.006309 # Average occupied blocks per requestor 205system.cpu.l2cache.occ_blocks::cpu.data 7519.122292 # Average occupied blocks per requestor 206system.cpu.l2cache.occ_percent::writebacks 0.417452 # Average percentage of cache occupancy 207system.cpu.l2cache.occ_percent::cpu.inst 0.000916 # Average percentage of cache occupancy 208system.cpu.l2cache.occ_percent::cpu.data 0.229465 # Average percentage of cache occupancy 209system.cpu.l2cache.occ_percent::total 0.647833 # Average percentage of cache occupancy 210system.cpu.l2cache.ReadReq_hits::cpu.inst 493 # number of ReadReq hits 211system.cpu.l2cache.ReadReq_hits::cpu.data 1398159 # number of ReadReq hits 212system.cpu.l2cache.ReadReq_hits::total 1398652 # number of ReadReq hits 213system.cpu.l2cache.Writeback_hits::writebacks 2223170 # number of Writeback hits 214system.cpu.l2cache.Writeback_hits::total 2223170 # number of Writeback hits 215system.cpu.l2cache.ReadExReq_hits::cpu.data 543011 # number of ReadExReq hits 216system.cpu.l2cache.ReadExReq_hits::total 543011 # number of ReadExReq hits 217system.cpu.l2cache.demand_hits::cpu.inst 493 # number of demand (read+write) hits 218system.cpu.l2cache.demand_hits::cpu.data 1941170 # number of demand (read+write) hits 219system.cpu.l2cache.demand_hits::total 1941663 # number of demand (read+write) hits 220system.cpu.l2cache.overall_hits::cpu.inst 493 # number of overall hits 221system.cpu.l2cache.overall_hits::cpu.data 1941170 # number of overall hits 222system.cpu.l2cache.overall_hits::total 1941663 # number of overall hits 223system.cpu.l2cache.ReadReq_misses::cpu.inst 2321 # number of ReadReq misses 224system.cpu.l2cache.ReadReq_misses::cpu.data 329255 # number of ReadReq misses 225system.cpu.l2cache.ReadReq_misses::total 331576 # number of ReadReq misses 226system.cpu.l2cache.ReadExReq_misses::cpu.data 248033 # number of ReadExReq misses 227system.cpu.l2cache.ReadExReq_misses::total 248033 # number of ReadExReq misses 228system.cpu.l2cache.demand_misses::cpu.inst 2321 # number of demand (read+write) misses 229system.cpu.l2cache.demand_misses::cpu.data 577288 # number of demand (read+write) misses 230system.cpu.l2cache.demand_misses::total 579609 # number of demand (read+write) misses 231system.cpu.l2cache.overall_misses::cpu.inst 2321 # number of overall misses 232system.cpu.l2cache.overall_misses::cpu.data 577288 # number of overall misses 233system.cpu.l2cache.overall_misses::total 579609 # number of overall misses 234system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120692000 # number of ReadReq miss cycles 235system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17121260000 # number of ReadReq miss cycles 236system.cpu.l2cache.ReadReq_miss_latency::total 17241952000 # number of ReadReq miss cycles 237system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12897722000 # number of ReadExReq miss cycles 238system.cpu.l2cache.ReadExReq_miss_latency::total 12897722000 # number of ReadExReq miss cycles 239system.cpu.l2cache.demand_miss_latency::cpu.inst 120692000 # number of demand (read+write) miss cycles 240system.cpu.l2cache.demand_miss_latency::cpu.data 30018982000 # number of demand (read+write) miss cycles 241system.cpu.l2cache.demand_miss_latency::total 30139674000 # number of demand (read+write) miss cycles 242system.cpu.l2cache.overall_miss_latency::cpu.inst 120692000 # number of overall miss cycles 243system.cpu.l2cache.overall_miss_latency::cpu.data 30018982000 # number of overall miss cycles 244system.cpu.l2cache.overall_miss_latency::total 30139674000 # number of overall miss cycles 245system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) 246system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) 247system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) 248system.cpu.l2cache.Writeback_accesses::writebacks 2223170 # number of Writeback accesses(hits+misses) 249system.cpu.l2cache.Writeback_accesses::total 2223170 # number of Writeback accesses(hits+misses) 250system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) 251system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) 252system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses 253system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses 254system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses 255system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses 256system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses 257system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses 258system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses 259system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses 260system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses 261system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses 262system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses 263system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses 264system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses 265system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 266system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 267system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency 268system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 269system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency 270system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 271system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency 272system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 273system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 274system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 275system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 276system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 277system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 278system.cpu.l2cache.fast_writes 0 # number of fast writes performed 279system.cpu.l2cache.cache_copies 0 # number of cache copies performed 280system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks 281system.cpu.l2cache.writebacks::total 411709 # number of writebacks 282system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2321 # number of ReadReq MSHR misses 283system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 329255 # number of ReadReq MSHR misses 284system.cpu.l2cache.ReadReq_mshr_misses::total 331576 # number of ReadReq MSHR misses 285system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 248033 # number of ReadExReq MSHR misses 286system.cpu.l2cache.ReadExReq_mshr_misses::total 248033 # number of ReadExReq MSHR misses 287system.cpu.l2cache.demand_mshr_misses::cpu.inst 2321 # number of demand (read+write) MSHR misses 288system.cpu.l2cache.demand_mshr_misses::cpu.data 577288 # number of demand (read+write) MSHR misses 289system.cpu.l2cache.demand_mshr_misses::total 579609 # number of demand (read+write) MSHR misses 290system.cpu.l2cache.overall_mshr_misses::cpu.inst 2321 # number of overall MSHR misses 291system.cpu.l2cache.overall_mshr_misses::cpu.data 577288 # number of overall MSHR misses 292system.cpu.l2cache.overall_mshr_misses::total 579609 # number of overall MSHR misses 293system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92840000 # number of ReadReq MSHR miss cycles 294system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13170200000 # number of ReadReq MSHR miss cycles 295system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13263040000 # number of ReadReq MSHR miss cycles 296system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9921320000 # number of ReadExReq MSHR miss cycles 297system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9921320000 # number of ReadExReq MSHR miss cycles 298system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles 299system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles 300system.cpu.l2cache.demand_mshr_miss_latency::total 23184360000 # number of demand (read+write) MSHR miss cycles 301system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles 302system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles 303system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles 304system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses 305system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses 306system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses 307system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses 308system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses 309system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses 310system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses 311system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 312system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 313system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 314system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 315system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 316system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 317system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 318system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 319 320---------- End Simulation Statistics ---------- 321