stats.txt revision 11507
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.650501 # Number of seconds simulated 4sim_ticks 1650501252500 # Number of ticks simulated 5final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 482495 # Simulator instruction rate (inst/s) 8host_op_rate 892859 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 963127288 # Simulator tick rate (ticks/s) 10host_mem_usage 277668 # Number of bytes of host memory used 11host_seconds 1713.69 # Real time elapsed on the host 12sim_insts 826847304 # Number of instructions simulated 13sim_ops 1530082521 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 41system.cpu.workload.num_syscalls 551 # Number of system calls 42system.cpu.numCycles 3301002505 # number of cpu cycles simulated 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 826847304 # Number of instructions committed 46system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 49system.cpu.num_func_calls 35346287 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls 51system.cpu.num_int_insts 1527470226 # number of integer instructions 52system.cpu.num_fp_insts 0 # number of float instructions 53system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read 54system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written 55system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 57system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read 58system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written 59system.cpu.num_mem_refs 533241508 # number of memory refs 60system.cpu.num_load_insts 384083313 # Number of load instructions 61system.cpu.num_store_insts 149158195 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 63system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 149981740 # Number of branches fetched 67system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction 68system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction 69system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction 70system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction 71system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction 72system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction 73system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction 74system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction 75system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction 76system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction 77system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction 78system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction 79system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction 80system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction 81system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction 82system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction 83system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction 84system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction 85system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction 86system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction 87system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction 88system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction 89system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction 90system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction 91system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction 92system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction 93system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction 94system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction 97system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction 98system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 1530082521 # Class of executed instruction 102system.cpu.dcache.tags.replacements 2517016 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses 120system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits 124system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits 126system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits 127system.cpu.dcache.overall_hits::total 530720441 # number of overall hits 128system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses 129system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses 130system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses 131system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses 132system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses 133system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses 134system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses 135system.cpu.dcache.overall_misses::total 2521112 # number of overall misses 136system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles 137system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles 139system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles 140system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles 141system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles 142system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles 143system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles 144system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses 149system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses 150system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses 151system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses 152system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses 153system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses 154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses 155system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses 156system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses 157system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses 158system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses 159system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses 160system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency 161system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency 163system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency 164system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency 165system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency 168system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks 175system.cpu.dcache.writebacks::total 2325221 # number of writebacks 176system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses 177system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses 178system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses 179system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses 180system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses 181system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses 182system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses 183system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses 184system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles 185system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles 186system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles 187system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles 188system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles 189system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles 190system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles 191system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles 192system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses 193system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses 194system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses 195system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses 196system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses 197system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses 198system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses 199system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses 200system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency 201system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency 202system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency 203system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency 204system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 205system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency 206system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency 207system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency 208system.cpu.icache.tags.replacements 1253 # number of replacements 209system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use 210system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks. 211system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 212system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks. 213system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 214system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor 215system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy 216system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy 217system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 218system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 219system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id 223system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id 224system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses 225system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses 226system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits 227system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits 228system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits 229system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits 230system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits 231system.cpu.icache.overall_hits::total 1068307822 # number of overall hits 232system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 233system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 234system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 235system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 236system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 237system.cpu.icache.overall_misses::total 2814 # number of overall misses 238system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles 239system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles 240system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles 241system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles 242system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles 243system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles 244system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses) 245system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses) 246system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses 247system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses 248system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses 249system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses 250system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 251system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 252system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 253system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 254system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 255system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses 256system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency 257system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency 258system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency 259system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency 260system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency 261system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency 262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 268system.cpu.icache.writebacks::writebacks 1253 # number of writebacks 269system.cpu.icache.writebacks::total 1253 # number of writebacks 270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 271system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 272system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 273system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 274system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 275system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses 276system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles 277system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles 278system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles 279system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles 280system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles 281system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles 282system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 283system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 284system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 285system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency 294system.cpu.l2cache.tags.replacements 348438 # number of replacements 295system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use 296system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks. 297system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. 298system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks. 299system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. 300system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor 301system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor 302system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor 303system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy 304system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy 305system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy 306system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id 308system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id 312system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id 313system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses 314system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses 315system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits 316system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits 317system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits 318system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits 319system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits 320system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits 321system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits 322system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits 323system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits 324system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits 325system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits 326system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits 327system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits 328system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits 329system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits 330system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits 331system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses 332system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses 333system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses 334system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses 335system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses 336system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses 337system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses 338system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses 339system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses 340system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses 341system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses 342system.cpu.l2cache.overall_misses::total 380855 # number of overall misses 343system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles 344system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles 345system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles 346system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles 347system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles 348system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles 349system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles 350system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles 351system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles 352system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles 353system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles 354system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles 355system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses) 356system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses) 357system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) 358system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) 359system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses) 360system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses) 361system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) 362system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) 363system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses) 364system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses) 365system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses 366system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses 367system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses 368system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses 369system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses 370system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses 371system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses 372system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses 373system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses 374system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses 375system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses 376system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses 377system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses 378system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses 379system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses 380system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses 381system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses 382system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses 383system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency 384system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency 385system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency 386system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency 387system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency 388system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency 389system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency 390system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency 391system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency 392system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency 393system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency 394system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency 395system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 401system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks 402system.cpu.l2cache.writebacks::total 293208 # number of writebacks 403system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses 404system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses 405system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses 406system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses 407system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses 408system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses 409system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses 410system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses 411system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses 412system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses 413system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses 414system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses 415system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses 416system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses 417system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles 418system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles 419system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles 420system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles 421system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles 422system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles 423system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles 424system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles 425system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles 426system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles 427system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles 428system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles 429system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 430system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 431system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses 432system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses 433system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses 434system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses 435system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses 436system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses 437system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses 438system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses 439system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses 440system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses 441system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses 442system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses 443system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency 444system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency 445system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency 446system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency 447system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency 448system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency 449system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency 450system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency 451system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency 452system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency 453system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency 455system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter. 456system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 457system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 458system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. 459system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 460system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 461system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution 469system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes) 472system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) 473system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes) 475system.cpu.toL2Bus.snoops 348438 # Total snoops (count) 476system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram 477system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram 478system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram 479system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 483system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram 487system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks) 488system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 489system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 490system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 491system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks) 492system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 493system.membus.trans_dist::ReadResp 174499 # Transaction distribution 494system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution 495system.membus.trans_dist::CleanEvict 53507 # Transaction distribution 496system.membus.trans_dist::ReadExReq 206356 # Transaction distribution 497system.membus.trans_dist::ReadExResp 206356 # Transaction distribution 498system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution 499system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) 500system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) 501system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) 502system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) 503system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) 504system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) 505system.membus.snoops 0 # Total snoops (count) 506system.membus.snoop_fanout::samples 727569 # Request fanout histogram 507system.membus.snoop_fanout::mean 0 # Request fanout histogram 508system.membus.snoop_fanout::stdev 0 # Request fanout histogram 509system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 510system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram 511system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 512system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 513system.membus.snoop_fanout::min_value 0 # Request fanout histogram 514system.membus.snoop_fanout::max_value 0 # Request fanout histogram 515system.membus.snoop_fanout::total 727569 # Request fanout histogram 516system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks) 517system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 518system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) 519system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 520 521---------- End Simulation Statistics ---------- 522