stats.txt revision 10892:bd37e25fb3b7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647861 # Number of seconds simulated 4sim_ticks 1647861059500 # Number of ticks simulated 5final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 708384 # Simulator instruction rate (inst/s) 8host_op_rate 1309882 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1411719986 # Simulator tick rate (ticks/s) 10host_mem_usage 323600 # Number of bytes of host memory used 11host_seconds 1167.27 # Real time elapsed on the host 12sim_insts 826877110 # Number of instructions simulated 13sim_ops 1528988702 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 120384 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24254848 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24375232 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 120384 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 120384 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18763136 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18763136 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1881 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 378982 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 380863 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 293174 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 293174 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 73055 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 14718989 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 14792043 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 73055 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 73055 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 11386358 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11386358 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11386358 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 73055 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 14718989 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 26178401 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 41system.cpu.workload.num_syscalls 551 # Number of system calls 42system.cpu.numCycles 3295722119 # number of cpu cycles simulated 43system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 44system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 45system.cpu.committedInsts 826877110 # Number of instructions committed 46system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed 47system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses 48system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 49system.cpu.num_func_calls 35346287 # number of times a function call or return occured 50system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls 51system.cpu.num_int_insts 1526605510 # number of integer instructions 52system.cpu.num_fp_insts 0 # number of float instructions 53system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read 54system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written 55system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 56system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 57system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read 58system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written 59system.cpu.num_mem_refs 533262343 # number of memory refs 60system.cpu.num_load_insts 384102157 # Number of load instructions 61system.cpu.num_store_insts 149160186 # Number of store instructions 62system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 63system.cpu.num_busy_cycles 3295722118.998000 # Number of busy cycles 64system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 65system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 66system.cpu.Branches 149758583 # Number of branches fetched 67system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction 68system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction 69system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction 70system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction 71system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction 72system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction 73system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction 74system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction 75system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction 76system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction 77system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction 78system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction 79system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction 80system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction 81system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction 82system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction 83system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction 84system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction 85system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction 86system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction 87system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction 88system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction 89system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction 90system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction 91system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction 92system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction 93system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction 94system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction 95system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction 96system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction 97system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction 98system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction 99system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 100system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 101system.cpu.op_class::total 1528988702 # Class of executed instruction 102system.cpu.dcache.tags.replacements 2514362 # number of replacements 103system.cpu.dcache.tags.tagsinuse 4086.415711 # Cycle average of tags in use 104system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. 105system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. 106system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. 107system.cpu.dcache.tags.warmup_cycle 8211725500 # Cycle when the warmup percentage was hit. 108system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415711 # Average occupied blocks per requestor 109system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy 110system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy 111system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 112system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 113system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 114system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 115system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id 116system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 117system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 118system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses 119system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses 120system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits 121system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits 122system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits 123system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits 124system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits 125system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits 126system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits 127system.cpu.dcache.overall_hits::total 530743930 # number of overall hits 128system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses 129system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses 130system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses 131system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses 132system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses 133system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses 134system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses 135system.cpu.dcache.overall_misses::total 2518458 # number of overall misses 136system.cpu.dcache.ReadReq_miss_latency::cpu.data 29707934500 # number of ReadReq miss cycles 137system.cpu.dcache.ReadReq_miss_latency::total 29707934500 # number of ReadReq miss cycles 138system.cpu.dcache.WriteReq_miss_latency::cpu.data 18949311500 # number of WriteReq miss cycles 139system.cpu.dcache.WriteReq_miss_latency::total 18949311500 # number of WriteReq miss cycles 140system.cpu.dcache.demand_miss_latency::cpu.data 48657246000 # number of demand (read+write) miss cycles 141system.cpu.dcache.demand_miss_latency::total 48657246000 # number of demand (read+write) miss cycles 142system.cpu.dcache.overall_miss_latency::cpu.data 48657246000 # number of overall miss cycles 143system.cpu.dcache.overall_miss_latency::total 48657246000 # number of overall miss cycles 144system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) 145system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) 146system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 147system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 148system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses 149system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses 150system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses 151system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses 152system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses 153system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses 154system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses 155system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses 156system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses 157system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses 158system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses 159system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses 160system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17197.923891 # average ReadReq miss latency 161system.cpu.dcache.ReadReq_avg_miss_latency::total 17197.923891 # average ReadReq miss latency 162system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23954.813512 # average WriteReq miss latency 163system.cpu.dcache.WriteReq_avg_miss_latency::total 23954.813512 # average WriteReq miss latency 164system.cpu.dcache.demand_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency 165system.cpu.dcache.demand_avg_miss_latency::total 19320.253107 # average overall miss latency 166system.cpu.dcache.overall_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency 167system.cpu.dcache.overall_avg_miss_latency::total 19320.253107 # average overall miss latency 168system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 172system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.cpu.dcache.fast_writes 0 # number of fast writes performed 175system.cpu.dcache.cache_copies 0 # number of cache copies performed 176system.cpu.dcache.writebacks::writebacks 2323227 # number of writebacks 177system.cpu.dcache.writebacks::total 2323227 # number of writebacks 178system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses 179system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses 180system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses 181system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses 182system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses 183system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses 184system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses 185system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses 186system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27980520500 # number of ReadReq MSHR miss cycles 187system.cpu.dcache.ReadReq_mshr_miss_latency::total 27980520500 # number of ReadReq MSHR miss cycles 188system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18158267500 # number of WriteReq MSHR miss cycles 189system.cpu.dcache.WriteReq_mshr_miss_latency::total 18158267500 # number of WriteReq MSHR miss cycles 190system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46138788000 # number of demand (read+write) MSHR miss cycles 191system.cpu.dcache.demand_mshr_miss_latency::total 46138788000 # number of demand (read+write) MSHR miss cycles 192system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46138788000 # number of overall MSHR miss cycles 193system.cpu.dcache.overall_mshr_miss_latency::total 46138788000 # number of overall MSHR miss cycles 194system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses 195system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses 196system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses 197system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses 198system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses 199system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses 200system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses 201system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses 202system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16197.923891 # average ReadReq mshr miss latency 203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16197.923891 # average ReadReq mshr miss latency 204system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22954.813512 # average WriteReq mshr miss latency 205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22954.813512 # average WriteReq mshr miss latency 206system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency 207system.cpu.dcache.demand_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency 208system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency 209system.cpu.dcache.overall_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency 210system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 211system.cpu.icache.tags.replacements 1253 # number of replacements 212system.cpu.icache.tags.tagsinuse 881.348726 # Cycle average of tags in use 213system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. 214system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 215system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. 216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 217system.cpu.icache.tags.occ_blocks::cpu.inst 881.348726 # Average occupied blocks per requestor 218system.cpu.icache.tags.occ_percent::cpu.inst 0.430346 # Average percentage of cache occupancy 219system.cpu.icache.tags.occ_percent::total 0.430346 # Average percentage of cache occupancy 220system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 223system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 224system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 225system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id 226system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id 227system.cpu.icache.tags.tag_accesses 2136696944 # Number of tag accesses 228system.cpu.icache.tags.data_accesses 2136696944 # Number of data accesses 229system.cpu.icache.ReadReq_hits::cpu.inst 1068344251 # number of ReadReq hits 230system.cpu.icache.ReadReq_hits::total 1068344251 # number of ReadReq hits 231system.cpu.icache.demand_hits::cpu.inst 1068344251 # number of demand (read+write) hits 232system.cpu.icache.demand_hits::total 1068344251 # number of demand (read+write) hits 233system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits 234system.cpu.icache.overall_hits::total 1068344251 # number of overall hits 235system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 236system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 237system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 238system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 239system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 240system.cpu.icache.overall_misses::total 2814 # number of overall misses 241system.cpu.icache.ReadReq_miss_latency::cpu.inst 115655000 # number of ReadReq miss cycles 242system.cpu.icache.ReadReq_miss_latency::total 115655000 # number of ReadReq miss cycles 243system.cpu.icache.demand_miss_latency::cpu.inst 115655000 # number of demand (read+write) miss cycles 244system.cpu.icache.demand_miss_latency::total 115655000 # number of demand (read+write) miss cycles 245system.cpu.icache.overall_miss_latency::cpu.inst 115655000 # number of overall miss cycles 246system.cpu.icache.overall_miss_latency::total 115655000 # number of overall miss cycles 247system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) 248system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) 249system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses 250system.cpu.icache.demand_accesses::total 1068347065 # number of demand (read+write) accesses 251system.cpu.icache.overall_accesses::cpu.inst 1068347065 # number of overall (read+write) accesses 252system.cpu.icache.overall_accesses::total 1068347065 # number of overall (read+write) accesses 253system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 254system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 255system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 256system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 257system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 258system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses 259system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41099.857854 # average ReadReq miss latency 260system.cpu.icache.ReadReq_avg_miss_latency::total 41099.857854 # average ReadReq miss latency 261system.cpu.icache.demand_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency 262system.cpu.icache.demand_avg_miss_latency::total 41099.857854 # average overall miss latency 263system.cpu.icache.overall_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency 264system.cpu.icache.overall_avg_miss_latency::total 41099.857854 # average overall miss latency 265system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 266system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 271system.cpu.icache.fast_writes 0 # number of fast writes performed 272system.cpu.icache.cache_copies 0 # number of cache copies performed 273system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 274system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 275system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 276system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 277system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 278system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses 279system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112841000 # number of ReadReq MSHR miss cycles 280system.cpu.icache.ReadReq_mshr_miss_latency::total 112841000 # number of ReadReq MSHR miss cycles 281system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112841000 # number of demand (read+write) MSHR miss cycles 282system.cpu.icache.demand_mshr_miss_latency::total 112841000 # number of demand (read+write) MSHR miss cycles 283system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112841000 # number of overall MSHR miss cycles 284system.cpu.icache.overall_mshr_miss_latency::total 112841000 # number of overall MSHR miss cycles 285system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 286system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 287system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 288system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 289system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 290system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 291system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40099.857854 # average ReadReq mshr miss latency 292system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40099.857854 # average ReadReq mshr miss latency 293system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency 294system.cpu.icache.demand_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency 295system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency 296system.cpu.icache.overall_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency 297system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 298system.cpu.l2cache.tags.replacements 348182 # number of replacements 299system.cpu.l2cache.tags.tagsinuse 29285.938694 # Cycle average of tags in use 300system.cpu.l2cache.tags.total_refs 3846845 # Total number of references to valid blocks. 301system.cpu.l2cache.tags.sampled_refs 380537 # Sample count of references to valid blocks. 302system.cpu.l2cache.tags.avg_refs 10.108991 # Average number of references to valid blocks. 303system.cpu.l2cache.tags.warmup_cycle 755943397500 # Cycle when the warmup percentage was hit. 304system.cpu.l2cache.tags.occ_blocks::writebacks 20928.501607 # Average occupied blocks per requestor 305system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.116925 # Average occupied blocks per requestor 306system.cpu.l2cache.tags.occ_blocks::cpu.data 8218.320163 # Average occupied blocks per requestor 307system.cpu.l2cache.tags.occ_percent::writebacks 0.638687 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004246 # Average percentage of cache occupancy 309system.cpu.l2cache.tags.occ_percent::cpu.data 0.250803 # Average percentage of cache occupancy 310system.cpu.l2cache.tags.occ_percent::total 0.893736 # Average percentage of cache occupancy 311system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 313system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 314system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id 315system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id 316system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id 317system.cpu.l2cache.tags.tag_accesses 41466677 # Number of tag accesses 318system.cpu.l2cache.tags.data_accesses 41466677 # Number of data accesses 319system.cpu.l2cache.Writeback_hits::writebacks 2323227 # number of Writeback hits 320system.cpu.l2cache.Writeback_hits::total 2323227 # number of Writeback hits 321system.cpu.l2cache.ReadExReq_hits::cpu.data 584717 # number of ReadExReq hits 322system.cpu.l2cache.ReadExReq_hits::total 584717 # number of ReadExReq hits 323system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 933 # number of ReadCleanReq hits 324system.cpu.l2cache.ReadCleanReq_hits::total 933 # number of ReadCleanReq hits 325system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554759 # number of ReadSharedReq hits 326system.cpu.l2cache.ReadSharedReq_hits::total 1554759 # number of ReadSharedReq hits 327system.cpu.l2cache.demand_hits::cpu.inst 933 # number of demand (read+write) hits 328system.cpu.l2cache.demand_hits::cpu.data 2139476 # number of demand (read+write) hits 329system.cpu.l2cache.demand_hits::total 2140409 # number of demand (read+write) hits 330system.cpu.l2cache.overall_hits::cpu.inst 933 # number of overall hits 331system.cpu.l2cache.overall_hits::cpu.data 2139476 # number of overall hits 332system.cpu.l2cache.overall_hits::total 2140409 # number of overall hits 333system.cpu.l2cache.ReadExReq_misses::cpu.data 206327 # number of ReadExReq misses 334system.cpu.l2cache.ReadExReq_misses::total 206327 # number of ReadExReq misses 335system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1881 # number of ReadCleanReq misses 336system.cpu.l2cache.ReadCleanReq_misses::total 1881 # number of ReadCleanReq misses 337system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172655 # number of ReadSharedReq misses 338system.cpu.l2cache.ReadSharedReq_misses::total 172655 # number of ReadSharedReq misses 339system.cpu.l2cache.demand_misses::cpu.inst 1881 # number of demand (read+write) misses 340system.cpu.l2cache.demand_misses::cpu.data 378982 # number of demand (read+write) misses 341system.cpu.l2cache.demand_misses::total 380863 # number of demand (read+write) misses 342system.cpu.l2cache.overall_misses::cpu.inst 1881 # number of overall misses 343system.cpu.l2cache.overall_misses::cpu.data 378982 # number of overall misses 344system.cpu.l2cache.overall_misses::total 380863 # number of overall misses 345system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10832173000 # number of ReadExReq miss cycles 346system.cpu.l2cache.ReadExReq_miss_latency::total 10832173000 # number of ReadExReq miss cycles 347system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 98817000 # number of ReadCleanReq miss cycles 348system.cpu.l2cache.ReadCleanReq_miss_latency::total 98817000 # number of ReadCleanReq miss cycles 349system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9064428500 # number of ReadSharedReq miss cycles 350system.cpu.l2cache.ReadSharedReq_miss_latency::total 9064428500 # number of ReadSharedReq miss cycles 351system.cpu.l2cache.demand_miss_latency::cpu.inst 98817000 # number of demand (read+write) miss cycles 352system.cpu.l2cache.demand_miss_latency::cpu.data 19896601500 # number of demand (read+write) miss cycles 353system.cpu.l2cache.demand_miss_latency::total 19995418500 # number of demand (read+write) miss cycles 354system.cpu.l2cache.overall_miss_latency::cpu.inst 98817000 # number of overall miss cycles 355system.cpu.l2cache.overall_miss_latency::cpu.data 19896601500 # number of overall miss cycles 356system.cpu.l2cache.overall_miss_latency::total 19995418500 # number of overall miss cycles 357system.cpu.l2cache.Writeback_accesses::writebacks 2323227 # number of Writeback accesses(hits+misses) 358system.cpu.l2cache.Writeback_accesses::total 2323227 # number of Writeback accesses(hits+misses) 359system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) 360system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) 361system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) 362system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) 363system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1727414 # number of ReadSharedReq accesses(hits+misses) 364system.cpu.l2cache.ReadSharedReq_accesses::total 1727414 # number of ReadSharedReq accesses(hits+misses) 365system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses 366system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses 367system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses 368system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses 369system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses 370system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses 371system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260829 # miss rate for ReadExReq accesses 372system.cpu.l2cache.ReadExReq_miss_rate::total 0.260829 # miss rate for ReadExReq accesses 373system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.668443 # miss rate for ReadCleanReq accesses 374system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.668443 # miss rate for ReadCleanReq accesses 375system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099950 # miss rate for ReadSharedReq accesses 376system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099950 # miss rate for ReadSharedReq accesses 377system.cpu.l2cache.demand_miss_rate::cpu.inst 0.668443 # miss rate for demand accesses 378system.cpu.l2cache.demand_miss_rate::cpu.data 0.150482 # miss rate for demand accesses 379system.cpu.l2cache.demand_miss_rate::total 0.151060 # miss rate for demand accesses 380system.cpu.l2cache.overall_miss_rate::cpu.inst 0.668443 # miss rate for overall accesses 381system.cpu.l2cache.overall_miss_rate::cpu.data 0.150482 # miss rate for overall accesses 382system.cpu.l2cache.overall_miss_rate::total 0.151060 # miss rate for overall accesses 383system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.026657 # average ReadExReq miss latency 384system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.026657 # average ReadExReq miss latency 385system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52534.290271 # average ReadCleanReq miss latency 386system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52534.290271 # average ReadCleanReq miss latency 387system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.237468 # average ReadSharedReq miss latency 388system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.237468 # average ReadSharedReq miss latency 389system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency 390system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency 391system.cpu.l2cache.demand_avg_miss_latency::total 52500.291443 # average overall miss latency 392system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency 393system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency 394system.cpu.l2cache.overall_avg_miss_latency::total 52500.291443 # average overall miss latency 395system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 401system.cpu.l2cache.fast_writes 0 # number of fast writes performed 402system.cpu.l2cache.cache_copies 0 # number of cache copies performed 403system.cpu.l2cache.writebacks::writebacks 293174 # number of writebacks 404system.cpu.l2cache.writebacks::total 293174 # number of writebacks 405system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 275 # number of CleanEvict MSHR misses 406system.cpu.l2cache.CleanEvict_mshr_misses::total 275 # number of CleanEvict MSHR misses 407system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206327 # number of ReadExReq MSHR misses 408system.cpu.l2cache.ReadExReq_mshr_misses::total 206327 # number of ReadExReq MSHR misses 409system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1881 # number of ReadCleanReq MSHR misses 410system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1881 # number of ReadCleanReq MSHR misses 411system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172655 # number of ReadSharedReq MSHR misses 412system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172655 # number of ReadSharedReq MSHR misses 413system.cpu.l2cache.demand_mshr_misses::cpu.inst 1881 # number of demand (read+write) MSHR misses 414system.cpu.l2cache.demand_mshr_misses::cpu.data 378982 # number of demand (read+write) MSHR misses 415system.cpu.l2cache.demand_mshr_misses::total 380863 # number of demand (read+write) MSHR misses 416system.cpu.l2cache.overall_mshr_misses::cpu.inst 1881 # number of overall MSHR misses 417system.cpu.l2cache.overall_mshr_misses::cpu.data 378982 # number of overall MSHR misses 418system.cpu.l2cache.overall_mshr_misses::total 380863 # number of overall MSHR misses 419system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8768903000 # number of ReadExReq MSHR miss cycles 420system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8768903000 # number of ReadExReq MSHR miss cycles 421system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 80007000 # number of ReadCleanReq MSHR miss cycles 422system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 80007000 # number of ReadCleanReq MSHR miss cycles 423system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7337878500 # number of ReadSharedReq MSHR miss cycles 424system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7337878500 # number of ReadSharedReq MSHR miss cycles 425system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 80007000 # number of demand (read+write) MSHR miss cycles 426system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16106781500 # number of demand (read+write) MSHR miss cycles 427system.cpu.l2cache.demand_mshr_miss_latency::total 16186788500 # number of demand (read+write) MSHR miss cycles 428system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 80007000 # number of overall MSHR miss cycles 429system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16106781500 # number of overall MSHR miss cycles 430system.cpu.l2cache.overall_mshr_miss_latency::total 16186788500 # number of overall MSHR miss cycles 431system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 432system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 433system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260829 # mshr miss rate for ReadExReq accesses 434system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260829 # mshr miss rate for ReadExReq accesses 435system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for ReadCleanReq accesses 436system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.668443 # mshr miss rate for ReadCleanReq accesses 437system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099950 # mshr miss rate for ReadSharedReq accesses 438system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099950 # mshr miss rate for ReadSharedReq accesses 439system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for demand accesses 440system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for demand accesses 441system.cpu.l2cache.demand_mshr_miss_rate::total 0.151060 # mshr miss rate for demand accesses 442system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for overall accesses 443system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for overall accesses 444system.cpu.l2cache.overall_mshr_miss_rate::total 0.151060 # mshr miss rate for overall accesses 445system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.026657 # average ReadExReq mshr miss latency 446system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.026657 # average ReadExReq mshr miss latency 447system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42534.290271 # average ReadCleanReq mshr miss latency 448system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42534.290271 # average ReadCleanReq mshr miss latency 449system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.237468 # average ReadSharedReq mshr miss latency 450system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.237468 # average ReadSharedReq mshr miss latency 451system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency 452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency 453system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency 455system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency 456system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency 457system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution 459system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution 460system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution 461system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution 463system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 # Transaction distribution 465system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes) 467system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes) 468system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309867840 # Cumulative packet size per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes) 471system.cpu.toL2Bus.snoops 348182 # Total snoops (count) 472system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram 473system.cpu.toL2Bus.snoop_fanout::mean 1.064657 # Request fanout histogram 474system.cpu.toL2Bus.snoop_fanout::stdev 0.245920 # Request fanout histogram 475system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 476system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 477system.cpu.toL2Bus.snoop_fanout::1 5036887 93.53% 93.53% # Request fanout histogram 478system.cpu.toL2Bus.snoop_fanout::2 348182 6.47% 100.00% # Request fanout histogram 479system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram 483system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks) 484system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 485system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 486system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 487system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) 488system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 489system.membus.trans_dist::ReadResp 174536 # Transaction distribution 490system.membus.trans_dist::Writeback 293174 # Transaction distribution 491system.membus.trans_dist::CleanEvict 53553 # Transaction distribution 492system.membus.trans_dist::ReadExReq 206327 # Transaction distribution 493system.membus.trans_dist::ReadExResp 206327 # Transaction distribution 494system.membus.trans_dist::ReadSharedReq 174536 # Transaction distribution 495system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108453 # Packet count per connected master and slave (bytes) 496system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108453 # Packet count per connected master and slave (bytes) 497system.membus.pkt_count::total 1108453 # Packet count per connected master and slave (bytes) 498system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43138368 # Cumulative packet size per connected master and slave (bytes) 499system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43138368 # Cumulative packet size per connected master and slave (bytes) 500system.membus.pkt_size::total 43138368 # Cumulative packet size per connected master and slave (bytes) 501system.membus.snoops 0 # Total snoops (count) 502system.membus.snoop_fanout::samples 727623 # Request fanout histogram 503system.membus.snoop_fanout::mean 0 # Request fanout histogram 504system.membus.snoop_fanout::stdev 0 # Request fanout histogram 505system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 506system.membus.snoop_fanout::0 727623 100.00% 100.00% # Request fanout histogram 507system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 508system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 509system.membus.snoop_fanout::min_value 0 # Request fanout histogram 510system.membus.snoop_fanout::max_value 0 # Request fanout histogram 511system.membus.snoop_fanout::total 727623 # Request fanout histogram 512system.membus.reqLayer0.occupancy 1900350576 # Layer occupancy (ticks) 513system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 514system.membus.respLayer1.occupancy 1904342076 # Layer occupancy (ticks) 515system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 516 517---------- End Simulation Statistics ---------- 518