stats.txt revision 10220:9eab5efc02e8
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.647873 # Number of seconds simulated 4sim_ticks 1647872849000 # Number of ticks simulated 5final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 654522 # Simulator instruction rate (inst/s) 8host_op_rate 1210285 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1304389188 # Simulator tick rate (ticks/s) 10host_mem_usage 297832 # Number of bytes of host memory used 11host_seconds 1263.33 # Real time elapsed on the host 12sim_insts 826877110 # Number of instructions simulated 13sim_ops 1528988702 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory 18system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 120704 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 120704 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 18706304 # Number of bytes written to this memory 22system.physmem.bytes_written::total 18706304 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1886 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 379257 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 381143 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) 39system.membus.throughput 26154600 # Throughput (bytes/s) 40system.membus.trans_dist::ReadReq 174452 # Transaction distribution 41system.membus.trans_dist::ReadResp 174452 # Transaction distribution 42system.membus.trans_dist::Writeback 292286 # Transaction distribution 43system.membus.trans_dist::ReadExReq 206691 # Transaction distribution 44system.membus.trans_dist::ReadExResp 206691 # Transaction distribution 45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) 47system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) 48system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) 49system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) 50system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) 51system.membus.data_through_bus 43099456 # Total data (bytes) 52system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 53system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) 54system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 55system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) 56system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 57system.cpu_clk_domain.clock 500 # Clock period in ticks 58system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 59system.cpu.workload.num_syscalls 551 # Number of system calls 60system.cpu.numCycles 3295745698 # number of cpu cycles simulated 61system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 62system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 63system.cpu.committedInsts 826877110 # Number of instructions committed 64system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed 65system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses 66system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 67system.cpu.num_func_calls 35346287 # number of times a function call or return occured 68system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls 69system.cpu.num_int_insts 1526605510 # number of integer instructions 70system.cpu.num_fp_insts 0 # number of float instructions 71system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read 72system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written 73system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 74system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 75system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read 76system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written 77system.cpu.num_mem_refs 533262343 # number of memory refs 78system.cpu.num_load_insts 384102157 # Number of load instructions 79system.cpu.num_store_insts 149160186 # Number of store instructions 80system.cpu.num_idle_cycles 0 # Number of idle cycles 81system.cpu.num_busy_cycles 3295745698 # Number of busy cycles 82system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 83system.cpu.idle_fraction 0 # Percentage of idle cycles 84system.cpu.Branches 149758583 # Number of branches fetched 85system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction 86system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction 87system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction 88system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction 89system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction 90system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction 91system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction 92system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction 93system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction 94system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction 95system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction 96system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction 97system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction 98system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction 99system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction 100system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction 101system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction 102system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction 103system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction 104system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction 105system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction 106system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction 107system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction 108system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction 109system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction 110system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction 111system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction 112system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction 113system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction 114system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction 115system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction 116system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction 117system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 118system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 119system.cpu.op_class::total 1528988702 # Class of executed instruction 120system.cpu.icache.tags.replacements 1253 # number of replacements 121system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use 122system.cpu.icache.tags.total_refs 1068344252 # Total number of references to valid blocks. 123system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. 124system.cpu.icache.tags.avg_refs 379653.252310 # Average number of references to valid blocks. 125system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 126system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor 127system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy 128system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy 129system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id 130system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 131system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 132system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 133system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id 134system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id 135system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id 136system.cpu.icache.tags.tag_accesses 2136696946 # Number of tag accesses 137system.cpu.icache.tags.data_accesses 2136696946 # Number of data accesses 138system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits 139system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits 140system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits 141system.cpu.icache.demand_hits::total 1068344252 # number of demand (read+write) hits 142system.cpu.icache.overall_hits::cpu.inst 1068344252 # number of overall hits 143system.cpu.icache.overall_hits::total 1068344252 # number of overall hits 144system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses 145system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses 146system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses 147system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses 148system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses 149system.cpu.icache.overall_misses::total 2814 # number of overall misses 150system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles 151system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles 152system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles 153system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles 154system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles 155system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles 156system.cpu.icache.ReadReq_accesses::cpu.inst 1068347066 # number of ReadReq accesses(hits+misses) 157system.cpu.icache.ReadReq_accesses::total 1068347066 # number of ReadReq accesses(hits+misses) 158system.cpu.icache.demand_accesses::cpu.inst 1068347066 # number of demand (read+write) accesses 159system.cpu.icache.demand_accesses::total 1068347066 # number of demand (read+write) accesses 160system.cpu.icache.overall_accesses::cpu.inst 1068347066 # number of overall (read+write) accesses 161system.cpu.icache.overall_accesses::total 1068347066 # number of overall (read+write) accesses 162system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses 163system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses 164system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses 165system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses 166system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses 167system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses 168system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency 169system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency 170system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency 171system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency 172system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency 173system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency 174system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 175system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 176system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 177system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 178system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180system.cpu.icache.fast_writes 0 # number of fast writes performed 181system.cpu.icache.cache_copies 0 # number of cache copies performed 182system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses 183system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses 184system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses 185system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses 186system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses 187system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses 188system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles 189system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles 190system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles 191system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles 192system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles 193system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles 194system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 195system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 196system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 197system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 198system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 199system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses 200system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency 201system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency 202system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 203system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency 204system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency 205system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency 206system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 207system.cpu.l2cache.tags.replacements 348459 # number of replacements 208system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use 209system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. 210system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. 211system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. 212system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. 213system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor 214system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor 215system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor 216system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy 217system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy 218system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy 219system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy 220system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id 221system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 222system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 223system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id 224system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id 225system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id 226system.cpu.l2cache.tags.tag_accesses 39930218 # Number of tag accesses 227system.cpu.l2cache.tags.data_accesses 39930218 # Number of data accesses 228system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits 229system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits 230system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits 231system.cpu.l2cache.Writeback_hits::writebacks 2323523 # number of Writeback hits 232system.cpu.l2cache.Writeback_hits::total 2323523 # number of Writeback hits 233system.cpu.l2cache.ReadExReq_hits::cpu.data 584353 # number of ReadExReq hits 234system.cpu.l2cache.ReadExReq_hits::total 584353 # number of ReadExReq hits 235system.cpu.l2cache.demand_hits::cpu.inst 928 # number of demand (read+write) hits 236system.cpu.l2cache.demand_hits::cpu.data 2139201 # number of demand (read+write) hits 237system.cpu.l2cache.demand_hits::total 2140129 # number of demand (read+write) hits 238system.cpu.l2cache.overall_hits::cpu.inst 928 # number of overall hits 239system.cpu.l2cache.overall_hits::cpu.data 2139201 # number of overall hits 240system.cpu.l2cache.overall_hits::total 2140129 # number of overall hits 241system.cpu.l2cache.ReadReq_misses::cpu.inst 1886 # number of ReadReq misses 242system.cpu.l2cache.ReadReq_misses::cpu.data 172566 # number of ReadReq misses 243system.cpu.l2cache.ReadReq_misses::total 174452 # number of ReadReq misses 244system.cpu.l2cache.ReadExReq_misses::cpu.data 206691 # number of ReadExReq misses 245system.cpu.l2cache.ReadExReq_misses::total 206691 # number of ReadExReq misses 246system.cpu.l2cache.demand_misses::cpu.inst 1886 # number of demand (read+write) misses 247system.cpu.l2cache.demand_misses::cpu.data 379257 # number of demand (read+write) misses 248system.cpu.l2cache.demand_misses::total 381143 # number of demand (read+write) misses 249system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses 250system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses 251system.cpu.l2cache.overall_misses::total 381143 # number of overall misses 252system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles 253system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles 254system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles 255system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles 256system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles 257system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles 258system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles 259system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles 260system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles 261system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles 262system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles 263system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) 264system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) 265system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) 266system.cpu.l2cache.Writeback_accesses::writebacks 2323523 # number of Writeback accesses(hits+misses) 267system.cpu.l2cache.Writeback_accesses::total 2323523 # number of Writeback accesses(hits+misses) 268system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) 269system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) 270system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses 271system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses 272system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses 273system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses 274system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses 275system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses 276system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.670220 # miss rate for ReadReq accesses 277system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099898 # miss rate for ReadReq accesses 278system.cpu.l2cache.ReadReq_miss_rate::total 0.100826 # miss rate for ReadReq accesses 279system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.261289 # miss rate for ReadExReq accesses 280system.cpu.l2cache.ReadExReq_miss_rate::total 0.261289 # miss rate for ReadExReq accesses 281system.cpu.l2cache.demand_miss_rate::cpu.inst 0.670220 # miss rate for demand accesses 282system.cpu.l2cache.demand_miss_rate::cpu.data 0.150591 # miss rate for demand accesses 283system.cpu.l2cache.demand_miss_rate::total 0.151171 # miss rate for demand accesses 284system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses 285system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses 286system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses 287system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency 288system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency 289system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency 290system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency 291system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency 292system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency 293system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency 294system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency 295system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency 296system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency 297system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency 298system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 299system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 300system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 301system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 302system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 303system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 304system.cpu.l2cache.fast_writes 0 # number of fast writes performed 305system.cpu.l2cache.cache_copies 0 # number of cache copies performed 306system.cpu.l2cache.writebacks::writebacks 292286 # number of writebacks 307system.cpu.l2cache.writebacks::total 292286 # number of writebacks 308system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1886 # number of ReadReq MSHR misses 309system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 172566 # number of ReadReq MSHR misses 310system.cpu.l2cache.ReadReq_mshr_misses::total 174452 # number of ReadReq MSHR misses 311system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206691 # number of ReadExReq MSHR misses 312system.cpu.l2cache.ReadExReq_mshr_misses::total 206691 # number of ReadExReq MSHR misses 313system.cpu.l2cache.demand_mshr_misses::cpu.inst 1886 # number of demand (read+write) MSHR misses 314system.cpu.l2cache.demand_mshr_misses::cpu.data 379257 # number of demand (read+write) MSHR misses 315system.cpu.l2cache.demand_mshr_misses::total 381143 # number of demand (read+write) MSHR misses 316system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses 317system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses 318system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses 319system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles 320system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles 321system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles 322system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles 323system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles 324system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles 325system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles 326system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles 327system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles 328system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles 329system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles 330system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses 331system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses 332system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses 333system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.261289 # mshr miss rate for ReadExReq accesses 334system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.261289 # mshr miss rate for ReadExReq accesses 335system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for demand accesses 336system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for demand accesses 337system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 # mshr miss rate for demand accesses 338system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses 339system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses 340system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses 341system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency 342system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency 343system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency 344system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency 345system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency 346system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency 347system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency 348system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency 349system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency 350system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency 351system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency 352system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 353system.cpu.dcache.tags.replacements 2514362 # number of replacements 354system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use 355system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. 356system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. 357system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. 358system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. 359system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor 360system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy 361system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy 362system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 363system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 364system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 365system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id 366system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id 367system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 368system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 369system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses 370system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses 371system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits 372system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits 373system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits 374system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits 375system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits 376system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits 377system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits 378system.cpu.dcache.overall_hits::total 530743930 # number of overall hits 379system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses 380system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses 381system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses 382system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses 383system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses 384system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses 385system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses 386system.cpu.dcache.overall_misses::total 2518458 # number of overall misses 387system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles 388system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles 389system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles 390system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles 391system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles 392system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles 393system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles 394system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles 395system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) 396system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) 397system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 398system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 399system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses 400system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses 401system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses 402system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses 403system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses 404system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses 405system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses 406system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses 407system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses 408system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses 409system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses 410system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses 411system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency 412system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency 413system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency 414system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency 415system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency 416system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency 417system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency 418system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency 419system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 420system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 422system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 423system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 424system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.cpu.dcache.fast_writes 0 # number of fast writes performed 426system.cpu.dcache.cache_copies 0 # number of cache copies performed 427system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks 428system.cpu.dcache.writebacks::total 2323523 # number of writebacks 429system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses 430system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses 431system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses 432system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses 433system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses 434system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses 435system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses 436system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses 437system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles 438system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles 439system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles 440system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles 441system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles 442system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles 443system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles 444system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles 445system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses 446system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses 447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses 448system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses 449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses 450system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses 451system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses 452system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses 453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency 454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency 455system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency 456system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency 457system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 458system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 459system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency 460system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency 461system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 462system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s) 463system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution 468system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5628 # Packet count per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7360439 # Packet count per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_count::total 7366067 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes) 472system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309886784 # Cumulative packet size per connected master and slave (bytes) 473system.cpu.toL2Bus.tot_pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes) 475system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 476system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) 477system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 478system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) 479system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 480system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) 481system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 482 483---------- End Simulation Statistics ---------- 484