stats.txt revision 9583:c1a5a20cc1fa
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.434779 # Number of seconds simulated 4sim_ticks 434778577000 # Number of ticks simulated 5final_tick 434778577000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 65958 # Simulator instruction rate (inst/s) 8host_op_rate 121963 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34681028 # Simulator tick rate (ticks/s) 10host_mem_usage 469672 # Number of bytes of host memory used 11host_seconds 12536.50 # Real time elapsed on the host 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988701 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 207616 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24480192 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24687808 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 207616 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 207616 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 18793792 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18793792 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3244 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 382503 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 385747 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 293653 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 293653 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 477521 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 56304964 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 56782485 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 477521 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 477521 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 43226122 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 43226122 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 43226122 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 477521 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 56304964 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 100008607 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 385749 # Total number of read requests seen 38system.physmem.writeReqs 293653 # Total number of write requests seen 39system.physmem.cpureqs 898439 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 24687808 # Total number of bytes read from memory 41system.physmem.bytesWritten 18793792 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 24687808 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 18793792 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 215914 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 23310 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 24517 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 23767 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 22579 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 23602 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 24804 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 24363 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 24233 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 24554 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 24709 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 24156 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 24303 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 24582 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 23494 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 24683 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 23927 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 17803 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 18810 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 18279 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 17552 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 18029 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 18664 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 18318 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 18338 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 18780 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 18770 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 18402 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 18539 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 18562 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 17888 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 18802 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 18117 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 3123 # Number of times wr buffer was full causing retry 80system.physmem.totGap 434778560000 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 385749 # Categorize read packet sizes 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes 94system.physmem.writePktSize::6 293653 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 380888 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 4255 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 362 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 63 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 127system.physmem.wrQLenPdf::0 12710 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 12723 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 12724 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::3 12726 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::4 12730 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::5 12731 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 12734 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 12734 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 12736 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 44 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::26 42 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::27 38 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::28 37 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 34 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see 159system.physmem.totQLat 3433767500 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 12026720000 # Sum of mem lat for all requests 161system.physmem.totBusLat 1927915000 # Total cycles spent in databus access 162system.physmem.totBankLat 6665037500 # Total cycles spent in bank access 163system.physmem.avgQLat 8905.39 # Average queueing delay per request 164system.physmem.avgBankLat 17285.61 # Average bank access latency per request 165system.physmem.avgBusLat 5000.00 # Average bus latency per request 166system.physmem.avgMemAccLat 31191.00 # Average memory access latency 167system.physmem.avgRdBW 56.78 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 43.23 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 56.78 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 43.23 # Average consumed write bandwidth in MB/s 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 172system.physmem.busUtil 0.78 # Data bus utilization in percentage 173system.physmem.avgRdQLen 0.03 # Average read queue length over time 174system.physmem.avgWrQLen 9.96 # Average write queue length over time 175system.physmem.readRowHits 331863 # Number of row buffer hits during reads 176system.physmem.writeRowHits 191855 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 65.33 # Row buffer hit rate for writes 179system.physmem.avgGap 639943.01 # Average gap between requests 180system.cpu.branchPred.lookups 214994146 # Number of BP lookups 181system.cpu.branchPred.condPredicted 214994146 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 13135298 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 150584792 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 147887338 # Number of BTB hits 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 186system.cpu.branchPred.BTBHitPct 98.208681 # BTB Hit Percentage 187system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 189system.cpu.workload.num_syscalls 551 # Number of system calls 190system.cpu.numCycles 869557155 # number of cpu cycles simulated 191system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 192system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 193system.cpu.fetch.icacheStallCycles 180620519 # Number of cycles fetch is stalled on an Icache miss 194system.cpu.fetch.Insts 1193264599 # Number of instructions fetch has processed 195system.cpu.fetch.Branches 214994146 # Number of branches that fetch encountered 196system.cpu.fetch.predictedBranches 147887338 # Number of branches that fetch has predicted taken 197system.cpu.fetch.Cycles 371275147 # Number of cycles fetch has run and was not squashing or blocked 198system.cpu.fetch.SquashCycles 83409102 # Number of cycles fetch has spent squashing 199system.cpu.fetch.BlockedCycles 231974123 # Number of cycles fetch has spent blocked 200system.cpu.fetch.MiscStallCycles 33791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 201system.cpu.fetch.PendingTrapStallCycles 326928 # Number of stall cycles due to pending traps 202system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR 203system.cpu.fetch.CacheLines 173497134 # Number of cache lines fetched 204system.cpu.fetch.IcacheSquashes 3845609 # Number of outstanding Icache misses that were squashed 205system.cpu.fetch.rateDist::samples 854248204 # Number of instructions fetched each cycle (Total) 206system.cpu.fetch.rateDist::mean 2.593680 # Number of instructions fetched each cycle (Total) 207system.cpu.fetch.rateDist::stdev 3.388732 # Number of instructions fetched each cycle (Total) 208system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 209system.cpu.fetch.rateDist::0 487377953 57.05% 57.05% # Number of instructions fetched each cycle (Total) 210system.cpu.fetch.rateDist::1 24712671 2.89% 59.95% # Number of instructions fetched each cycle (Total) 211system.cpu.fetch.rateDist::2 27340185 3.20% 63.15% # Number of instructions fetched each cycle (Total) 212system.cpu.fetch.rateDist::3 28885218 3.38% 66.53% # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::4 18461820 2.16% 68.69% # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::5 24636038 2.88% 71.57% # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::6 30640475 3.59% 75.16% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::7 28823425 3.37% 78.53% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::8 183370419 21.47% 100.00% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::total 854248204 # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.branchRate 0.247246 # Number of branch fetches per cycle 223system.cpu.fetch.rate 1.372267 # Number of inst fetches per cycle 224system.cpu.decode.IdleCycles 237078092 # Number of cycles decode is idle 225system.cpu.decode.BlockedCycles 188537109 # Number of cycles decode is blocked 226system.cpu.decode.RunCycles 313423018 # Number of cycles decode is running 227system.cpu.decode.UnblockCycles 45192344 # Number of cycles decode is unblocking 228system.cpu.decode.SquashCycles 70017641 # Number of cycles decode is squashing 229system.cpu.decode.DecodedInsts 2166915251 # Number of instructions handled by decode 230system.cpu.decode.SquashedInsts 6 # Number of squashed instructions handled by decode 231system.cpu.rename.SquashCycles 70017641 # Number of cycles rename is squashing 232system.cpu.rename.IdleCycles 270505809 # Number of cycles rename is idle 233system.cpu.rename.BlockCycles 54166582 # Number of cycles rename is blocking 234system.cpu.rename.serializeStallCycles 16246 # count of cycles rename stalled for serializing inst 235system.cpu.rename.RunCycles 322705449 # Number of cycles rename is running 236system.cpu.rename.UnblockCycles 136836477 # Number of cycles rename is unblocking 237system.cpu.rename.RenamedInsts 2120054204 # Number of instructions processed by rename 238system.cpu.rename.ROBFullEvents 31988 # Number of times rename has blocked due to ROB full 239system.cpu.rename.IQFullEvents 21457173 # Number of times rename has blocked due to IQ full 240system.cpu.rename.LSQFullEvents 101130762 # Number of times rename has blocked due to LSQ full 241system.cpu.rename.FullRegisterEvents 79 # Number of times there has been no free registers 242system.cpu.rename.RenamedOperands 2216502453 # Number of destination operands rename has renamed 243system.cpu.rename.RenameLookups 5356043513 # Number of register rename lookups that rename has made 244system.cpu.rename.int_rename_lookups 5355912931 # Number of integer rename lookups 245system.cpu.rename.fp_rename_lookups 130582 # Number of floating rename lookups 246system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed 247system.cpu.rename.UndoneMaps 602461599 # Number of HB maps that are undone due to squashing 248system.cpu.rename.serializingInsts 1415 # count of serializing insts renamed 249system.cpu.rename.tempSerializingInsts 1390 # count of temporary serializing insts renamed 250system.cpu.rename.skidInsts 330161364 # count of insts added to the skid buffer 251system.cpu.memDep0.insertedLoads 512694390 # Number of loads inserted to the mem dependence unit. 252system.cpu.memDep0.insertedStores 204951429 # Number of stores inserted to the mem dependence unit. 253system.cpu.memDep0.conflictingLoads 196255090 # Number of conflicting loads. 254system.cpu.memDep0.conflictingStores 55443674 # Number of conflicting stores. 255system.cpu.iq.iqInstsAdded 2034023079 # Number of instructions added to the IQ (excludes non-spec) 256system.cpu.iq.iqNonSpecInstsAdded 23697 # Number of non-speculative instructions added to the IQ 257system.cpu.iq.iqInstsIssued 1808317213 # Number of instructions issued 258system.cpu.iq.iqSquashedInstsIssued 841556 # Number of squashed instructions issued 259system.cpu.iq.iqSquashedInstsExamined 499552115 # Number of squashed instructions iterated over during squash; mainly for profiling 260system.cpu.iq.iqSquashedOperandsExamined 818199817 # Number of squashed operands that are examined and possibly removed from graph 261system.cpu.iq.iqSquashedNonSpecRemoved 23145 # Number of squashed non-spec instructions that were removed 262system.cpu.iq.issued_per_cycle::samples 854248204 # Number of insts issued each cycle 263system.cpu.iq.issued_per_cycle::mean 2.116852 # Number of insts issued each cycle 264system.cpu.iq.issued_per_cycle::stdev 1.887224 # Number of insts issued each cycle 265system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 266system.cpu.iq.issued_per_cycle::0 233580311 27.34% 27.34% # Number of insts issued each cycle 267system.cpu.iq.issued_per_cycle::1 145624549 17.05% 44.39% # Number of insts issued each cycle 268system.cpu.iq.issued_per_cycle::2 138385021 16.20% 60.59% # Number of insts issued each cycle 269system.cpu.iq.issued_per_cycle::3 133093921 15.58% 76.17% # Number of insts issued each cycle 270system.cpu.iq.issued_per_cycle::4 95894144 11.23% 87.40% # Number of insts issued each cycle 271system.cpu.iq.issued_per_cycle::5 58820201 6.89% 94.28% # Number of insts issued each cycle 272system.cpu.iq.issued_per_cycle::6 34887177 4.08% 98.37% # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::7 12062824 1.41% 99.78% # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::8 1900056 0.22% 100.00% # Number of insts issued each cycle 275system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::total 854248204 # Number of insts issued each cycle 279system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 280system.cpu.iq.fu_full::IntAlu 4959094 32.46% 32.46% # attempts to use FU when none available 281system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available 282system.cpu.iq.fu_full::IntDiv 0 0.00% 32.46% # attempts to use FU when none available 283system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.46% # attempts to use FU when none available 284system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.46% # attempts to use FU when none available 285system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.46% # attempts to use FU when none available 286system.cpu.iq.fu_full::FloatMult 0 0.00% 32.46% # attempts to use FU when none available 287system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.46% # attempts to use FU when none available 288system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.46% # attempts to use FU when none available 289system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.46% # attempts to use FU when none available 290system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.46% # attempts to use FU when none available 291system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.46% # attempts to use FU when none available 292system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.46% # attempts to use FU when none available 293system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.46% # attempts to use FU when none available 294system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.46% # attempts to use FU when none available 295system.cpu.iq.fu_full::SimdMult 0 0.00% 32.46% # attempts to use FU when none available 296system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.46% # attempts to use FU when none available 297system.cpu.iq.fu_full::SimdShift 0 0.00% 32.46% # attempts to use FU when none available 298system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.46% # attempts to use FU when none available 299system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.46% # attempts to use FU when none available 300system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.46% # attempts to use FU when none available 301system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.46% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.46% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.46% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.46% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.46% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.46% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.46% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.46% # attempts to use FU when none available 309system.cpu.iq.fu_full::MemRead 7752013 50.74% 83.20% # attempts to use FU when none available 310system.cpu.iq.fu_full::MemWrite 2567167 16.80% 100.00% # attempts to use FU when none available 311system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 312system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 313system.cpu.iq.FU_type_0::No_OpClass 2720919 0.15% 0.15% # Type of FU issued 314system.cpu.iq.FU_type_0::IntAlu 1190891827 65.86% 66.01% # Type of FU issued 315system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued 316system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued 317system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 66.01% # Type of FU issued 318system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued 319system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued 320system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued 321system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued 322system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued 323system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued 324system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued 325system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued 326system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued 327system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued 328system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued 329system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued 330system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued 331system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued 332system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued 343system.cpu.iq.FU_type_0::MemRead 438957859 24.27% 90.28% # Type of FU issued 344system.cpu.iq.FU_type_0::MemWrite 175746607 9.72% 100.00% # Type of FU issued 345system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 346system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 347system.cpu.iq.FU_type_0::total 1808317213 # Type of FU issued 348system.cpu.iq.rate 2.079584 # Inst issue rate 349system.cpu.iq.fu_busy_cnt 15278274 # FU busy when requested 350system.cpu.iq.fu_busy_rate 0.008449 # FU busy rate (busy events/executed inst) 351system.cpu.iq.int_inst_queue_reads 4486980237 # Number of integer instruction queue reads 352system.cpu.iq.int_inst_queue_writes 2533813283 # Number of integer instruction queue writes 353system.cpu.iq.int_inst_queue_wakeup_accesses 1768843031 # Number of integer instruction queue wakeup accesses 354system.cpu.iq.fp_inst_queue_reads 22223 # Number of floating instruction queue reads 355system.cpu.iq.fp_inst_queue_writes 42394 # Number of floating instruction queue writes 356system.cpu.iq.fp_inst_queue_wakeup_accesses 5084 # Number of floating instruction queue wakeup accesses 357system.cpu.iq.int_alu_accesses 1820864137 # Number of integer alu accesses 358system.cpu.iq.fp_alu_accesses 10431 # Number of floating point alu accesses 359system.cpu.iew.lsq.thread0.forwLoads 170575963 # Number of loads that had data forwarded from stores 360system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 361system.cpu.iew.lsq.thread0.squashedLoads 128592233 # Number of loads squashed 362system.cpu.iew.lsq.thread0.ignoredResponses 466094 # Number of memory responses ignored because the instruction is squashed 363system.cpu.iew.lsq.thread0.memOrderViolation 268512 # Number of memory ordering violations 364system.cpu.iew.lsq.thread0.squashedStores 55791476 # Number of stores squashed 365system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 366system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 367system.cpu.iew.lsq.thread0.rescheduledLoads 12353 # Number of loads that were rescheduled 368system.cpu.iew.lsq.thread0.cacheBlocked 585 # Number of times an access to memory failed due to the cache being blocked 369system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 370system.cpu.iew.iewSquashCycles 70017641 # Number of cycles IEW is squashing 371system.cpu.iew.iewBlockCycles 16317048 # Number of cycles IEW is blocking 372system.cpu.iew.iewUnblockCycles 2892217 # Number of cycles IEW is unblocking 373system.cpu.iew.iewDispatchedInsts 2034046776 # Number of instructions dispatched to IQ 374system.cpu.iew.iewDispSquashedInsts 2393263 # Number of squashed instructions skipped by dispatch 375system.cpu.iew.iewDispLoadInsts 512694390 # Number of dispatched load instructions 376system.cpu.iew.iewDispStoreInsts 204951662 # Number of dispatched store instructions 377system.cpu.iew.iewDispNonSpecInsts 6140 # Number of dispatched non-speculative instructions 378system.cpu.iew.iewIQFullEvents 1820618 # Number of times the IQ has become full, causing a stall 379system.cpu.iew.iewLSQFullEvents 76746 # Number of times the LSQ has become full, causing a stall 380system.cpu.iew.memOrderViolationEvents 268512 # Number of memory order violations 381system.cpu.iew.predictedTakenIncorrect 9116558 # Number of branches that were predicted taken incorrectly 382system.cpu.iew.predictedNotTakenIncorrect 4489858 # Number of branches that were predicted not taken incorrectly 383system.cpu.iew.branchMispredicts 13606416 # Number of branch mispredicts detected at execute 384system.cpu.iew.iewExecutedInsts 1780627625 # Number of executed instructions 385system.cpu.iew.iewExecLoadInsts 431426006 # Number of load instructions executed 386system.cpu.iew.iewExecSquashedInsts 27689588 # Number of squashed instructions skipped in execute 387system.cpu.iew.exec_swp 0 # number of swp insts executed 388system.cpu.iew.exec_nop 0 # number of nop insts executed 389system.cpu.iew.exec_refs 602161774 # number of memory reference insts executed 390system.cpu.iew.exec_branches 169273752 # Number of branches executed 391system.cpu.iew.exec_stores 170735768 # Number of stores executed 392system.cpu.iew.exec_rate 2.047741 # Inst execution rate 393system.cpu.iew.wb_sent 1775545178 # cumulative count of insts sent to commit 394system.cpu.iew.wb_count 1768848115 # cumulative count of insts written-back 395system.cpu.iew.wb_producers 1341672434 # num instructions producing a value 396system.cpu.iew.wb_consumers 1964743040 # num instructions consuming a value 397system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 398system.cpu.iew.wb_rate 2.034194 # insts written-back per cycle 399system.cpu.iew.wb_fanout 0.682874 # average fanout of values written-back 400system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 401system.cpu.commit.commitSquashedInsts 505092905 # The number of squashed insts skipped by commit 402system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards 403system.cpu.commit.branchMispredicts 13168881 # The number of times a branch was mispredicted 404system.cpu.commit.committed_per_cycle::samples 784230563 # Number of insts commited each cycle 405system.cpu.commit.committed_per_cycle::mean 1.949667 # Number of insts commited each cycle 406system.cpu.commit.committed_per_cycle::stdev 2.458347 # Number of insts commited each cycle 407system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 408system.cpu.commit.committed_per_cycle::0 290802586 37.08% 37.08% # Number of insts commited each cycle 409system.cpu.commit.committed_per_cycle::1 195769482 24.96% 62.04% # Number of insts commited each cycle 410system.cpu.commit.committed_per_cycle::2 62065599 7.91% 69.96% # Number of insts commited each cycle 411system.cpu.commit.committed_per_cycle::3 92211558 11.76% 81.72% # Number of insts commited each cycle 412system.cpu.commit.committed_per_cycle::4 25071827 3.20% 84.91% # Number of insts commited each cycle 413system.cpu.commit.committed_per_cycle::5 28246222 3.60% 88.52% # Number of insts commited each cycle 414system.cpu.commit.committed_per_cycle::6 9385684 1.20% 89.71% # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::7 10800015 1.38% 91.09% # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::8 69877590 8.91% 100.00% # Number of insts commited each cycle 417system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::total 784230563 # Number of insts commited each cycle 421system.cpu.commit.committedInsts 826877109 # Number of instructions committed 422system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed 423system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 424system.cpu.commit.refs 533262343 # Number of memory references committed 425system.cpu.commit.loads 384102157 # Number of loads committed 426system.cpu.commit.membars 0 # Number of memory barriers committed 427system.cpu.commit.branches 149758583 # Number of branches committed 428system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 429system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. 430system.cpu.commit.function_calls 0 # Number of function calls committed. 431system.cpu.commit.bw_lim_events 69877590 # number cycles where commit BW limit reached 432system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 433system.cpu.rob.rob_reads 2748434579 # The number of ROB reads 434system.cpu.rob.rob_writes 4138359582 # The number of ROB writes 435system.cpu.timesIdled 322597 # Number of times that the entire CPU went into an idle state and unscheduled itself 436system.cpu.idleCycles 15308951 # Total number of cycles that the CPU has spent unscheduled due to idling 437system.cpu.committedInsts 826877109 # Number of Instructions Simulated 438system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated 439system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated 440system.cpu.cpi 1.051616 # CPI: Cycles Per Instruction 441system.cpu.cpi_total 1.051616 # CPI: Total CPI of All Threads 442system.cpu.ipc 0.950917 # IPC: Instructions Per Cycle 443system.cpu.ipc_total 0.950917 # IPC: Total IPC of All Threads 444system.cpu.int_regfile_reads 3357648579 # number of integer regfile reads 445system.cpu.int_regfile_writes 1848573449 # number of integer regfile writes 446system.cpu.fp_regfile_reads 5079 # number of floating regfile reads 447system.cpu.fp_regfile_writes 8 # number of floating regfile writes 448system.cpu.misc_regfile_reads 980313786 # number of misc regfile reads 449system.cpu.misc_regfile_writes 1 # number of misc regfile writes 450system.cpu.icache.replacements 5514 # number of replacements 451system.cpu.icache.tagsinuse 1036.209327 # Cycle average of tags in use 452system.cpu.icache.total_refs 173254328 # Total number of references to valid blocks. 453system.cpu.icache.sampled_refs 7112 # Sample count of references to valid blocks. 454system.cpu.icache.avg_refs 24360.844769 # Average number of references to valid blocks. 455system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 456system.cpu.icache.occ_blocks::cpu.inst 1036.209327 # Average occupied blocks per requestor 457system.cpu.icache.occ_percent::cpu.inst 0.505962 # Average percentage of cache occupancy 458system.cpu.icache.occ_percent::total 0.505962 # Average percentage of cache occupancy 459system.cpu.icache.ReadReq_hits::cpu.inst 173270216 # number of ReadReq hits 460system.cpu.icache.ReadReq_hits::total 173270216 # number of ReadReq hits 461system.cpu.icache.demand_hits::cpu.inst 173270216 # number of demand (read+write) hits 462system.cpu.icache.demand_hits::total 173270216 # number of demand (read+write) hits 463system.cpu.icache.overall_hits::cpu.inst 173270216 # number of overall hits 464system.cpu.icache.overall_hits::total 173270216 # number of overall hits 465system.cpu.icache.ReadReq_misses::cpu.inst 226918 # number of ReadReq misses 466system.cpu.icache.ReadReq_misses::total 226918 # number of ReadReq misses 467system.cpu.icache.demand_misses::cpu.inst 226918 # number of demand (read+write) misses 468system.cpu.icache.demand_misses::total 226918 # number of demand (read+write) misses 469system.cpu.icache.overall_misses::cpu.inst 226918 # number of overall misses 470system.cpu.icache.overall_misses::total 226918 # number of overall misses 471system.cpu.icache.ReadReq_miss_latency::cpu.inst 1447936998 # number of ReadReq miss cycles 472system.cpu.icache.ReadReq_miss_latency::total 1447936998 # number of ReadReq miss cycles 473system.cpu.icache.demand_miss_latency::cpu.inst 1447936998 # number of demand (read+write) miss cycles 474system.cpu.icache.demand_miss_latency::total 1447936998 # number of demand (read+write) miss cycles 475system.cpu.icache.overall_miss_latency::cpu.inst 1447936998 # number of overall miss cycles 476system.cpu.icache.overall_miss_latency::total 1447936998 # number of overall miss cycles 477system.cpu.icache.ReadReq_accesses::cpu.inst 173497134 # number of ReadReq accesses(hits+misses) 478system.cpu.icache.ReadReq_accesses::total 173497134 # number of ReadReq accesses(hits+misses) 479system.cpu.icache.demand_accesses::cpu.inst 173497134 # number of demand (read+write) accesses 480system.cpu.icache.demand_accesses::total 173497134 # number of demand (read+write) accesses 481system.cpu.icache.overall_accesses::cpu.inst 173497134 # number of overall (read+write) accesses 482system.cpu.icache.overall_accesses::total 173497134 # number of overall (read+write) accesses 483system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001308 # miss rate for ReadReq accesses 484system.cpu.icache.ReadReq_miss_rate::total 0.001308 # miss rate for ReadReq accesses 485system.cpu.icache.demand_miss_rate::cpu.inst 0.001308 # miss rate for demand accesses 486system.cpu.icache.demand_miss_rate::total 0.001308 # miss rate for demand accesses 487system.cpu.icache.overall_miss_rate::cpu.inst 0.001308 # miss rate for overall accesses 488system.cpu.icache.overall_miss_rate::total 0.001308 # miss rate for overall accesses 489system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6380.882072 # average ReadReq miss latency 490system.cpu.icache.ReadReq_avg_miss_latency::total 6380.882072 # average ReadReq miss latency 491system.cpu.icache.demand_avg_miss_latency::cpu.inst 6380.882072 # average overall miss latency 492system.cpu.icache.demand_avg_miss_latency::total 6380.882072 # average overall miss latency 493system.cpu.icache.overall_avg_miss_latency::cpu.inst 6380.882072 # average overall miss latency 494system.cpu.icache.overall_avg_miss_latency::total 6380.882072 # average overall miss latency 495system.cpu.icache.blocked_cycles::no_mshrs 1948 # number of cycles access was blocked 496system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 497system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked 498system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 499system.cpu.icache.avg_blocked_cycles::no_mshrs 121.750000 # average number of cycles each access was blocked 500system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 501system.cpu.icache.fast_writes 0 # number of fast writes performed 502system.cpu.icache.cache_copies 0 # number of cache copies performed 503system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2338 # number of ReadReq MSHR hits 504system.cpu.icache.ReadReq_mshr_hits::total 2338 # number of ReadReq MSHR hits 505system.cpu.icache.demand_mshr_hits::cpu.inst 2338 # number of demand (read+write) MSHR hits 506system.cpu.icache.demand_mshr_hits::total 2338 # number of demand (read+write) MSHR hits 507system.cpu.icache.overall_mshr_hits::cpu.inst 2338 # number of overall MSHR hits 508system.cpu.icache.overall_mshr_hits::total 2338 # number of overall MSHR hits 509system.cpu.icache.ReadReq_mshr_misses::cpu.inst 224580 # number of ReadReq MSHR misses 510system.cpu.icache.ReadReq_mshr_misses::total 224580 # number of ReadReq MSHR misses 511system.cpu.icache.demand_mshr_misses::cpu.inst 224580 # number of demand (read+write) MSHR misses 512system.cpu.icache.demand_mshr_misses::total 224580 # number of demand (read+write) MSHR misses 513system.cpu.icache.overall_mshr_misses::cpu.inst 224580 # number of overall MSHR misses 514system.cpu.icache.overall_mshr_misses::total 224580 # number of overall MSHR misses 515system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 927401499 # number of ReadReq MSHR miss cycles 516system.cpu.icache.ReadReq_mshr_miss_latency::total 927401499 # number of ReadReq MSHR miss cycles 517system.cpu.icache.demand_mshr_miss_latency::cpu.inst 927401499 # number of demand (read+write) MSHR miss cycles 518system.cpu.icache.demand_mshr_miss_latency::total 927401499 # number of demand (read+write) MSHR miss cycles 519system.cpu.icache.overall_mshr_miss_latency::cpu.inst 927401499 # number of overall MSHR miss cycles 520system.cpu.icache.overall_mshr_miss_latency::total 927401499 # number of overall MSHR miss cycles 521system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001294 # mshr miss rate for ReadReq accesses 522system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001294 # mshr miss rate for ReadReq accesses 523system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001294 # mshr miss rate for demand accesses 524system.cpu.icache.demand_mshr_miss_rate::total 0.001294 # mshr miss rate for demand accesses 525system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001294 # mshr miss rate for overall accesses 526system.cpu.icache.overall_mshr_miss_rate::total 0.001294 # mshr miss rate for overall accesses 527system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4129.492827 # average ReadReq mshr miss latency 528system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4129.492827 # average ReadReq mshr miss latency 529system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4129.492827 # average overall mshr miss latency 530system.cpu.icache.demand_avg_mshr_miss_latency::total 4129.492827 # average overall mshr miss latency 531system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4129.492827 # average overall mshr miss latency 532system.cpu.icache.overall_avg_mshr_miss_latency::total 4129.492827 # average overall mshr miss latency 533system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 534system.cpu.l2cache.replacements 353068 # number of replacements 535system.cpu.l2cache.tagsinuse 29624.531163 # Cycle average of tags in use 536system.cpu.l2cache.total_refs 3697718 # Total number of references to valid blocks. 537system.cpu.l2cache.sampled_refs 385429 # Sample count of references to valid blocks. 538system.cpu.l2cache.avg_refs 9.593772 # Average number of references to valid blocks. 539system.cpu.l2cache.warmup_cycle 201975419000 # Cycle when the warmup percentage was hit. 540system.cpu.l2cache.occ_blocks::writebacks 21048.484716 # Average occupied blocks per requestor 541system.cpu.l2cache.occ_blocks::cpu.inst 232.592119 # Average occupied blocks per requestor 542system.cpu.l2cache.occ_blocks::cpu.data 8343.454327 # Average occupied blocks per requestor 543system.cpu.l2cache.occ_percent::writebacks 0.642349 # Average percentage of cache occupancy 544system.cpu.l2cache.occ_percent::cpu.inst 0.007098 # Average percentage of cache occupancy 545system.cpu.l2cache.occ_percent::cpu.data 0.254622 # Average percentage of cache occupancy 546system.cpu.l2cache.occ_percent::total 0.904069 # Average percentage of cache occupancy 547system.cpu.l2cache.ReadReq_hits::cpu.inst 3816 # number of ReadReq hits 548system.cpu.l2cache.ReadReq_hits::cpu.data 1586658 # number of ReadReq hits 549system.cpu.l2cache.ReadReq_hits::total 1590474 # number of ReadReq hits 550system.cpu.l2cache.Writeback_hits::writebacks 2331136 # number of Writeback hits 551system.cpu.l2cache.Writeback_hits::total 2331136 # number of Writeback hits 552system.cpu.l2cache.UpgradeReq_hits::cpu.data 1531 # number of UpgradeReq hits 553system.cpu.l2cache.UpgradeReq_hits::total 1531 # number of UpgradeReq hits 554system.cpu.l2cache.ReadExReq_hits::cpu.data 564560 # number of ReadExReq hits 555system.cpu.l2cache.ReadExReq_hits::total 564560 # number of ReadExReq hits 556system.cpu.l2cache.demand_hits::cpu.inst 3816 # number of demand (read+write) hits 557system.cpu.l2cache.demand_hits::cpu.data 2151218 # number of demand (read+write) hits 558system.cpu.l2cache.demand_hits::total 2155034 # number of demand (read+write) hits 559system.cpu.l2cache.overall_hits::cpu.inst 3816 # number of overall hits 560system.cpu.l2cache.overall_hits::cpu.data 2151218 # number of overall hits 561system.cpu.l2cache.overall_hits::total 2155034 # number of overall hits 562system.cpu.l2cache.ReadReq_misses::cpu.inst 3245 # number of ReadReq misses 563system.cpu.l2cache.ReadReq_misses::cpu.data 175772 # number of ReadReq misses 564system.cpu.l2cache.ReadReq_misses::total 179017 # number of ReadReq misses 565system.cpu.l2cache.UpgradeReq_misses::cpu.data 215883 # number of UpgradeReq misses 566system.cpu.l2cache.UpgradeReq_misses::total 215883 # number of UpgradeReq misses 567system.cpu.l2cache.ReadExReq_misses::cpu.data 206764 # number of ReadExReq misses 568system.cpu.l2cache.ReadExReq_misses::total 206764 # number of ReadExReq misses 569system.cpu.l2cache.demand_misses::cpu.inst 3245 # number of demand (read+write) misses 570system.cpu.l2cache.demand_misses::cpu.data 382536 # number of demand (read+write) misses 571system.cpu.l2cache.demand_misses::total 385781 # number of demand (read+write) misses 572system.cpu.l2cache.overall_misses::cpu.inst 3245 # number of overall misses 573system.cpu.l2cache.overall_misses::cpu.data 382536 # number of overall misses 574system.cpu.l2cache.overall_misses::total 385781 # number of overall misses 575system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201201000 # number of ReadReq miss cycles 576system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10144981454 # number of ReadReq miss cycles 577system.cpu.l2cache.ReadReq_miss_latency::total 10346182454 # number of ReadReq miss cycles 578system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7392500 # number of UpgradeReq miss cycles 579system.cpu.l2cache.UpgradeReq_miss_latency::total 7392500 # number of UpgradeReq miss cycles 580system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10367117000 # number of ReadExReq miss cycles 581system.cpu.l2cache.ReadExReq_miss_latency::total 10367117000 # number of ReadExReq miss cycles 582system.cpu.l2cache.demand_miss_latency::cpu.inst 201201000 # number of demand (read+write) miss cycles 583system.cpu.l2cache.demand_miss_latency::cpu.data 20512098454 # number of demand (read+write) miss cycles 584system.cpu.l2cache.demand_miss_latency::total 20713299454 # number of demand (read+write) miss cycles 585system.cpu.l2cache.overall_miss_latency::cpu.inst 201201000 # number of overall miss cycles 586system.cpu.l2cache.overall_miss_latency::cpu.data 20512098454 # number of overall miss cycles 587system.cpu.l2cache.overall_miss_latency::total 20713299454 # number of overall miss cycles 588system.cpu.l2cache.ReadReq_accesses::cpu.inst 7061 # number of ReadReq accesses(hits+misses) 589system.cpu.l2cache.ReadReq_accesses::cpu.data 1762430 # number of ReadReq accesses(hits+misses) 590system.cpu.l2cache.ReadReq_accesses::total 1769491 # number of ReadReq accesses(hits+misses) 591system.cpu.l2cache.Writeback_accesses::writebacks 2331136 # number of Writeback accesses(hits+misses) 592system.cpu.l2cache.Writeback_accesses::total 2331136 # number of Writeback accesses(hits+misses) 593system.cpu.l2cache.UpgradeReq_accesses::cpu.data 217414 # number of UpgradeReq accesses(hits+misses) 594system.cpu.l2cache.UpgradeReq_accesses::total 217414 # number of UpgradeReq accesses(hits+misses) 595system.cpu.l2cache.ReadExReq_accesses::cpu.data 771324 # number of ReadExReq accesses(hits+misses) 596system.cpu.l2cache.ReadExReq_accesses::total 771324 # number of ReadExReq accesses(hits+misses) 597system.cpu.l2cache.demand_accesses::cpu.inst 7061 # number of demand (read+write) accesses 598system.cpu.l2cache.demand_accesses::cpu.data 2533754 # number of demand (read+write) accesses 599system.cpu.l2cache.demand_accesses::total 2540815 # number of demand (read+write) accesses 600system.cpu.l2cache.overall_accesses::cpu.inst 7061 # number of overall (read+write) accesses 601system.cpu.l2cache.overall_accesses::cpu.data 2533754 # number of overall (read+write) accesses 602system.cpu.l2cache.overall_accesses::total 2540815 # number of overall (read+write) accesses 603system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459567 # miss rate for ReadReq accesses 604system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099733 # miss rate for ReadReq accesses 605system.cpu.l2cache.ReadReq_miss_rate::total 0.101169 # miss rate for ReadReq accesses 606system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992958 # miss rate for UpgradeReq accesses 607system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992958 # miss rate for UpgradeReq accesses 608system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268064 # miss rate for ReadExReq accesses 609system.cpu.l2cache.ReadExReq_miss_rate::total 0.268064 # miss rate for ReadExReq accesses 610system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459567 # miss rate for demand accesses 611system.cpu.l2cache.demand_miss_rate::cpu.data 0.150976 # miss rate for demand accesses 612system.cpu.l2cache.demand_miss_rate::total 0.151834 # miss rate for demand accesses 613system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459567 # miss rate for overall accesses 614system.cpu.l2cache.overall_miss_rate::cpu.data 0.150976 # miss rate for overall accesses 615system.cpu.l2cache.overall_miss_rate::total 0.151834 # miss rate for overall accesses 616system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62003.389831 # average ReadReq miss latency 617system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57716.709453 # average ReadReq miss latency 618system.cpu.l2cache.ReadReq_avg_miss_latency::total 57794.413123 # average ReadReq miss latency 619system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.243085 # average UpgradeReq miss latency 620system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.243085 # average UpgradeReq miss latency 621system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50139.855101 # average ReadExReq miss latency 622system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50139.855101 # average ReadExReq miss latency 623system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency 624system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53621.354471 # average overall miss latency 625system.cpu.l2cache.demand_avg_miss_latency::total 53691.860029 # average overall miss latency 626system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62003.389831 # average overall miss latency 627system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53621.354471 # average overall miss latency 628system.cpu.l2cache.overall_avg_miss_latency::total 53691.860029 # average overall miss latency 629system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 630system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 631system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 632system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 633system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 634system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 635system.cpu.l2cache.fast_writes 0 # number of fast writes performed 636system.cpu.l2cache.cache_copies 0 # number of cache copies performed 637system.cpu.l2cache.writebacks::writebacks 293653 # number of writebacks 638system.cpu.l2cache.writebacks::total 293653 # number of writebacks 639system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3245 # number of ReadReq MSHR misses 640system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175772 # number of ReadReq MSHR misses 641system.cpu.l2cache.ReadReq_mshr_misses::total 179017 # number of ReadReq MSHR misses 642system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 215883 # number of UpgradeReq MSHR misses 643system.cpu.l2cache.UpgradeReq_mshr_misses::total 215883 # number of UpgradeReq MSHR misses 644system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206764 # number of ReadExReq MSHR misses 645system.cpu.l2cache.ReadExReq_mshr_misses::total 206764 # number of ReadExReq MSHR misses 646system.cpu.l2cache.demand_mshr_misses::cpu.inst 3245 # number of demand (read+write) MSHR misses 647system.cpu.l2cache.demand_mshr_misses::cpu.data 382536 # number of demand (read+write) MSHR misses 648system.cpu.l2cache.demand_mshr_misses::total 385781 # number of demand (read+write) MSHR misses 649system.cpu.l2cache.overall_mshr_misses::cpu.inst 3245 # number of overall MSHR misses 650system.cpu.l2cache.overall_mshr_misses::cpu.data 382536 # number of overall MSHR misses 651system.cpu.l2cache.overall_mshr_misses::total 385781 # number of overall MSHR misses 652system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 160858519 # number of ReadReq MSHR miss cycles 653system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7969651402 # number of ReadReq MSHR miss cycles 654system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8130509921 # number of ReadReq MSHR miss cycles 655system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2164647428 # number of UpgradeReq MSHR miss cycles 656system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2164647428 # number of UpgradeReq MSHR miss cycles 657system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7779866278 # number of ReadExReq MSHR miss cycles 658system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7779866278 # number of ReadExReq MSHR miss cycles 659system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 160858519 # number of demand (read+write) MSHR miss cycles 660system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15749517680 # number of demand (read+write) MSHR miss cycles 661system.cpu.l2cache.demand_mshr_miss_latency::total 15910376199 # number of demand (read+write) MSHR miss cycles 662system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 160858519 # number of overall MSHR miss cycles 663system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15749517680 # number of overall MSHR miss cycles 664system.cpu.l2cache.overall_mshr_miss_latency::total 15910376199 # number of overall MSHR miss cycles 665system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for ReadReq accesses 666system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099733 # mshr miss rate for ReadReq accesses 667system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101169 # mshr miss rate for ReadReq accesses 668system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992958 # mshr miss rate for UpgradeReq accesses 669system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992958 # mshr miss rate for UpgradeReq accesses 670system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268064 # mshr miss rate for ReadExReq accesses 671system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268064 # mshr miss rate for ReadExReq accesses 672system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for demand accesses 673system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150976 # mshr miss rate for demand accesses 674system.cpu.l2cache.demand_mshr_miss_rate::total 0.151834 # mshr miss rate for demand accesses 675system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.459567 # mshr miss rate for overall accesses 676system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150976 # mshr miss rate for overall accesses 677system.cpu.l2cache.overall_mshr_miss_rate::total 0.151834 # mshr miss rate for overall accesses 678system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49571.192296 # average ReadReq mshr miss latency 679system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45340.847245 # average ReadReq mshr miss latency 680system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45417.529737 # average ReadReq mshr miss latency 681system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.947133 # average UpgradeReq mshr miss latency 682system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.947133 # average UpgradeReq mshr miss latency 683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37626.793243 # average ReadExReq mshr miss latency 684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37626.793243 # average ReadExReq mshr miss latency 685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency 686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41171.334672 # average overall mshr miss latency 687system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41241.990142 # average overall mshr miss latency 688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49571.192296 # average overall mshr miss latency 689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41171.334672 # average overall mshr miss latency 690system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41241.990142 # average overall mshr miss latency 691system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 692system.cpu.dcache.replacements 2529656 # number of replacements 693system.cpu.dcache.tagsinuse 4087.796251 # Cycle average of tags in use 694system.cpu.dcache.total_refs 405349896 # Total number of references to valid blocks. 695system.cpu.dcache.sampled_refs 2533752 # Sample count of references to valid blocks. 696system.cpu.dcache.avg_refs 159.980099 # Average number of references to valid blocks. 697system.cpu.dcache.warmup_cycle 1794571000 # Cycle when the warmup percentage was hit. 698system.cpu.dcache.occ_blocks::cpu.data 4087.796251 # Average occupied blocks per requestor 699system.cpu.dcache.occ_percent::cpu.data 0.997997 # Average percentage of cache occupancy 700system.cpu.dcache.occ_percent::total 0.997997 # Average percentage of cache occupancy 701system.cpu.dcache.ReadReq_hits::cpu.data 256610011 # number of ReadReq hits 702system.cpu.dcache.ReadReq_hits::total 256610011 # number of ReadReq hits 703system.cpu.dcache.WriteReq_hits::cpu.data 148154878 # number of WriteReq hits 704system.cpu.dcache.WriteReq_hits::total 148154878 # number of WriteReq hits 705system.cpu.dcache.demand_hits::cpu.data 404764889 # number of demand (read+write) hits 706system.cpu.dcache.demand_hits::total 404764889 # number of demand (read+write) hits 707system.cpu.dcache.overall_hits::cpu.data 404764889 # number of overall hits 708system.cpu.dcache.overall_hits::total 404764889 # number of overall hits 709system.cpu.dcache.ReadReq_misses::cpu.data 2895327 # number of ReadReq misses 710system.cpu.dcache.ReadReq_misses::total 2895327 # number of ReadReq misses 711system.cpu.dcache.WriteReq_misses::cpu.data 1005324 # number of WriteReq misses 712system.cpu.dcache.WriteReq_misses::total 1005324 # number of WriteReq misses 713system.cpu.dcache.demand_misses::cpu.data 3900651 # number of demand (read+write) misses 714system.cpu.dcache.demand_misses::total 3900651 # number of demand (read+write) misses 715system.cpu.dcache.overall_misses::cpu.data 3900651 # number of overall misses 716system.cpu.dcache.overall_misses::total 3900651 # number of overall misses 717system.cpu.dcache.ReadReq_miss_latency::cpu.data 51401791500 # number of ReadReq miss cycles 718system.cpu.dcache.ReadReq_miss_latency::total 51401791500 # number of ReadReq miss cycles 719system.cpu.dcache.WriteReq_miss_latency::cpu.data 23898482499 # number of WriteReq miss cycles 720system.cpu.dcache.WriteReq_miss_latency::total 23898482499 # number of WriteReq miss cycles 721system.cpu.dcache.demand_miss_latency::cpu.data 75300273999 # number of demand (read+write) miss cycles 722system.cpu.dcache.demand_miss_latency::total 75300273999 # number of demand (read+write) miss cycles 723system.cpu.dcache.overall_miss_latency::cpu.data 75300273999 # number of overall miss cycles 724system.cpu.dcache.overall_miss_latency::total 75300273999 # number of overall miss cycles 725system.cpu.dcache.ReadReq_accesses::cpu.data 259505338 # number of ReadReq accesses(hits+misses) 726system.cpu.dcache.ReadReq_accesses::total 259505338 # number of ReadReq accesses(hits+misses) 727system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) 728system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) 729system.cpu.dcache.demand_accesses::cpu.data 408665540 # number of demand (read+write) accesses 730system.cpu.dcache.demand_accesses::total 408665540 # number of demand (read+write) accesses 731system.cpu.dcache.overall_accesses::cpu.data 408665540 # number of overall (read+write) accesses 732system.cpu.dcache.overall_accesses::total 408665540 # number of overall (read+write) accesses 733system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011157 # miss rate for ReadReq accesses 734system.cpu.dcache.ReadReq_miss_rate::total 0.011157 # miss rate for ReadReq accesses 735system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006740 # miss rate for WriteReq accesses 736system.cpu.dcache.WriteReq_miss_rate::total 0.006740 # miss rate for WriteReq accesses 737system.cpu.dcache.demand_miss_rate::cpu.data 0.009545 # miss rate for demand accesses 738system.cpu.dcache.demand_miss_rate::total 0.009545 # miss rate for demand accesses 739system.cpu.dcache.overall_miss_rate::cpu.data 0.009545 # miss rate for overall accesses 740system.cpu.dcache.overall_miss_rate::total 0.009545 # miss rate for overall accesses 741system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17753.363092 # average ReadReq miss latency 742system.cpu.dcache.ReadReq_avg_miss_latency::total 17753.363092 # average ReadReq miss latency 743system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23771.920793 # average WriteReq miss latency 744system.cpu.dcache.WriteReq_avg_miss_latency::total 23771.920793 # average WriteReq miss latency 745system.cpu.dcache.demand_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency 746system.cpu.dcache.demand_avg_miss_latency::total 19304.540191 # average overall miss latency 747system.cpu.dcache.overall_avg_miss_latency::cpu.data 19304.540191 # average overall miss latency 748system.cpu.dcache.overall_avg_miss_latency::total 19304.540191 # average overall miss latency 749system.cpu.dcache.blocked_cycles::no_mshrs 6530 # number of cycles access was blocked 750system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 751system.cpu.dcache.blocked::no_mshrs 642 # number of cycles access was blocked 752system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 753system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.171340 # average number of cycles each access was blocked 754system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 755system.cpu.dcache.fast_writes 0 # number of fast writes performed 756system.cpu.dcache.cache_copies 0 # number of cache copies performed 757system.cpu.dcache.writebacks::writebacks 2331136 # number of writebacks 758system.cpu.dcache.writebacks::total 2331136 # number of writebacks 759system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1132617 # number of ReadReq MSHR hits 760system.cpu.dcache.ReadReq_mshr_hits::total 1132617 # number of ReadReq MSHR hits 761system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16869 # number of WriteReq MSHR hits 762system.cpu.dcache.WriteReq_mshr_hits::total 16869 # number of WriteReq MSHR hits 763system.cpu.dcache.demand_mshr_hits::cpu.data 1149486 # number of demand (read+write) MSHR hits 764system.cpu.dcache.demand_mshr_hits::total 1149486 # number of demand (read+write) MSHR hits 765system.cpu.dcache.overall_mshr_hits::cpu.data 1149486 # number of overall MSHR hits 766system.cpu.dcache.overall_mshr_hits::total 1149486 # number of overall MSHR hits 767system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762710 # number of ReadReq MSHR misses 768system.cpu.dcache.ReadReq_mshr_misses::total 1762710 # number of ReadReq MSHR misses 769system.cpu.dcache.WriteReq_mshr_misses::cpu.data 988455 # number of WriteReq MSHR misses 770system.cpu.dcache.WriteReq_mshr_misses::total 988455 # number of WriteReq MSHR misses 771system.cpu.dcache.demand_mshr_misses::cpu.data 2751165 # number of demand (read+write) MSHR misses 772system.cpu.dcache.demand_mshr_misses::total 2751165 # number of demand (read+write) MSHR misses 773system.cpu.dcache.overall_mshr_misses::cpu.data 2751165 # number of overall MSHR misses 774system.cpu.dcache.overall_mshr_misses::total 2751165 # number of overall MSHR misses 775system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27811279500 # number of ReadReq MSHR miss cycles 776system.cpu.dcache.ReadReq_mshr_miss_latency::total 27811279500 # number of ReadReq MSHR miss cycles 777system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21719252000 # number of WriteReq MSHR miss cycles 778system.cpu.dcache.WriteReq_mshr_miss_latency::total 21719252000 # number of WriteReq MSHR miss cycles 779system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49530531500 # number of demand (read+write) MSHR miss cycles 780system.cpu.dcache.demand_mshr_miss_latency::total 49530531500 # number of demand (read+write) MSHR miss cycles 781system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49530531500 # number of overall MSHR miss cycles 782system.cpu.dcache.overall_mshr_miss_latency::total 49530531500 # number of overall MSHR miss cycles 783system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006793 # mshr miss rate for ReadReq accesses 784system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006793 # mshr miss rate for ReadReq accesses 785system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006627 # mshr miss rate for WriteReq accesses 786system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006627 # mshr miss rate for WriteReq accesses 787system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006732 # mshr miss rate for demand accesses 788system.cpu.dcache.demand_mshr_miss_rate::total 0.006732 # mshr miss rate for demand accesses 789system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006732 # mshr miss rate for overall accesses 790system.cpu.dcache.overall_mshr_miss_rate::total 0.006732 # mshr miss rate for overall accesses 791system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15777.569481 # average ReadReq mshr miss latency 792system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15777.569481 # average ReadReq mshr miss latency 793system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21972.929471 # average WriteReq mshr miss latency 794system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21972.929471 # average WriteReq mshr miss latency 795system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18003.475437 # average overall mshr miss latency 796system.cpu.dcache.demand_avg_mshr_miss_latency::total 18003.475437 # average overall mshr miss latency 797system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18003.475437 # average overall mshr miss latency 798system.cpu.dcache.overall_avg_mshr_miss_latency::total 18003.475437 # average overall mshr miss latency 799system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 800 801---------- End Simulation Statistics ---------- 802