stats.txt revision 9348:44d31345e360
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.434496 # Number of seconds simulated 4sim_ticks 434496110500 # Number of ticks simulated 5final_tick 434496110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 78440 # Simulator instruction rate (inst/s) 8host_op_rate 145045 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41217689 # Simulator tick rate (ticks/s) 10host_mem_usage 343084 # Number of bytes of host memory used 11host_seconds 10541.50 # Real time elapsed on the host 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988699 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 205760 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24473920 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24679680 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 205760 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 205760 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 18793728 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18793728 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3215 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 382405 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 385620 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 293652 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 293652 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 473560 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 56327133 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 56800693 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 473560 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 473560 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 43254076 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 43254076 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 43254076 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 473560 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 56327133 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 100054769 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 385622 # Total number of read requests seen 38system.physmem.writeReqs 293652 # Total number of write requests seen 39system.physmem.cpureqs 889960 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 24679680 # Total number of bytes read from memory 41system.physmem.bytesWritten 18793728 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 24679680 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 18793728 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 136 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 210686 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 24775 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 22937 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 24964 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 25246 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 24873 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 24535 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 23841 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 24700 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 22880 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 23587 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 23221 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 23429 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 24164 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 24144 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 24092 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 24098 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 19149 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 17956 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 18934 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 18992 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 19023 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 18726 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 18089 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 18519 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 17452 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 17936 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 17736 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 17628 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 18448 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 18286 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 18332 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 18446 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 434496092500 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 385622 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 293652 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 210686 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 380872 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 4191 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 366 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 12765 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 12768 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 12768 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 12768 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 12768 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 12768 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 12768 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 12768 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 12768 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 12767 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 12767 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 12767 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 12767 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 12767 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 12767 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 12767 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 12767 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 12767 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 3490991093 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 11561975093 # Sum of mem lat for all requests 176system.physmem.totBusLat 1541944000 # Total cycles spent in databus access 177system.physmem.totBankLat 6529040000 # Total cycles spent in bank access 178system.physmem.avgQLat 9056.08 # Average queueing delay per request 179system.physmem.avgBankLat 16937.17 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 29993.24 # Average memory access latency 182system.physmem.avgRdBW 56.80 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 43.25 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 56.80 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 43.25 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.63 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.03 # Average read queue length over time 189system.physmem.avgWrQLen 9.57 # Average write queue length over time 190system.physmem.readRowHits 340592 # Number of row buffer hits during reads 191system.physmem.writeRowHits 151278 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 51.52 # Row buffer hit rate for writes 194system.physmem.avgGap 639647.76 # Average gap between requests 195system.cpu.workload.num_syscalls 551 # Number of system calls 196system.cpu.numCycles 868992222 # number of cpu cycles simulated 197system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 198system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 199system.cpu.BPredUnit.lookups 214993851 # Number of BP lookups 200system.cpu.BPredUnit.condPredicted 214993851 # Number of conditional branches predicted 201system.cpu.BPredUnit.condIncorrect 13132727 # Number of conditional branches incorrect 202system.cpu.BPredUnit.BTBLookups 150483811 # Number of BTB lookups 203system.cpu.BPredUnit.BTBHits 147870058 # Number of BTB hits 204system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 205system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 206system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 207system.cpu.fetch.icacheStallCycles 180595819 # Number of cycles fetch is stalled on an Icache miss 208system.cpu.fetch.Insts 1193570142 # Number of instructions fetch has processed 209system.cpu.fetch.Branches 214993851 # Number of branches that fetch encountered 210system.cpu.fetch.predictedBranches 147870058 # Number of branches that fetch has predicted taken 211system.cpu.fetch.Cycles 371300946 # Number of cycles fetch has run and was not squashing or blocked 212system.cpu.fetch.SquashCycles 83432044 # Number of cycles fetch has spent squashing 213system.cpu.fetch.BlockedCycles 232898189 # Number of cycles fetch has spent blocked 214system.cpu.fetch.MiscStallCycles 32611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 215system.cpu.fetch.PendingTrapStallCycles 320539 # Number of stall cycles due to pending traps 216system.cpu.fetch.IcacheWaitRetryStallCycles 60 # Number of stall cycles due to full MSHR 217system.cpu.fetch.CacheLines 173489759 # Number of cache lines fetched 218system.cpu.fetch.IcacheSquashes 3820168 # Number of outstanding Icache misses that were squashed 219system.cpu.fetch.rateDist::samples 855191197 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::mean 2.591382 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::stdev 3.388294 # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::0 488292980 57.10% 57.10% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::1 24712697 2.89% 59.99% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::2 27343487 3.20% 63.18% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::3 28814936 3.37% 66.55% # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::4 18484341 2.16% 68.72% # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::5 24598023 2.88% 71.59% # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::6 30669616 3.59% 75.18% # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::7 28863276 3.38% 78.55% # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.rateDist::8 183411841 21.45% 100.00% # Number of instructions fetched each cycle (Total) 232system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.rateDist::total 855191197 # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.branchRate 0.247406 # Number of branch fetches per cycle 237system.cpu.fetch.rate 1.373511 # Number of inst fetches per cycle 238system.cpu.decode.IdleCycles 237057033 # Number of cycles decode is idle 239system.cpu.decode.BlockedCycles 189447507 # Number of cycles decode is blocked 240system.cpu.decode.RunCycles 313514348 # Number of cycles decode is running 241system.cpu.decode.UnblockCycles 45129276 # Number of cycles decode is unblocking 242system.cpu.decode.SquashCycles 70043033 # Number of cycles decode is squashing 243system.cpu.decode.DecodedInsts 2167224659 # Number of instructions handled by decode 244system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode 245system.cpu.rename.SquashCycles 70043033 # Number of cycles rename is squashing 246system.cpu.rename.IdleCycles 270477979 # Number of cycles rename is idle 247system.cpu.rename.BlockCycles 55455808 # Number of cycles rename is blocking 248system.cpu.rename.serializeStallCycles 15344 # count of cycles rename stalled for serializing inst 249system.cpu.rename.RunCycles 322737561 # Number of cycles rename is running 250system.cpu.rename.UnblockCycles 136461472 # Number of cycles rename is unblocking 251system.cpu.rename.RenamedInsts 2120443257 # Number of instructions processed by rename 252system.cpu.rename.ROBFullEvents 31742 # Number of times rename has blocked due to ROB full 253system.cpu.rename.IQFullEvents 21271807 # Number of times rename has blocked due to IQ full 254system.cpu.rename.LSQFullEvents 100951250 # Number of times rename has blocked due to LSQ full 255system.cpu.rename.FullRegisterEvents 96 # Number of times there has been no free registers 256system.cpu.rename.RenamedOperands 2216845941 # Number of destination operands rename has renamed 257system.cpu.rename.RenameLookups 5356850652 # Number of register rename lookups that rename has made 258system.cpu.rename.int_rename_lookups 5356713794 # Number of integer rename lookups 259system.cpu.rename.fp_rename_lookups 136858 # Number of floating rename lookups 260system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed 261system.cpu.rename.UndoneMaps 602805090 # Number of HB maps that are undone due to squashing 262system.cpu.rename.serializingInsts 1368 # count of serializing insts renamed 263system.cpu.rename.tempSerializingInsts 1337 # count of temporary serializing insts renamed 264system.cpu.rename.skidInsts 329763590 # count of insts added to the skid buffer 265system.cpu.memDep0.insertedLoads 512746819 # Number of loads inserted to the mem dependence unit. 266system.cpu.memDep0.insertedStores 204948217 # Number of stores inserted to the mem dependence unit. 267system.cpu.memDep0.conflictingLoads 196647356 # Number of conflicting loads. 268system.cpu.memDep0.conflictingStores 55718334 # Number of conflicting stores. 269system.cpu.iq.iqInstsAdded 2034222855 # Number of instructions added to the IQ (excludes non-spec) 270system.cpu.iq.iqNonSpecInstsAdded 23204 # Number of non-speculative instructions added to the IQ 271system.cpu.iq.iqInstsIssued 1808269086 # Number of instructions issued 272system.cpu.iq.iqSquashedInstsIssued 840688 # Number of squashed instructions issued 273system.cpu.iq.iqSquashedInstsExamined 499770877 # Number of squashed instructions iterated over during squash; mainly for profiling 274system.cpu.iq.iqSquashedOperandsExamined 818821894 # Number of squashed operands that are examined and possibly removed from graph 275system.cpu.iq.iqSquashedNonSpecRemoved 22651 # Number of squashed non-spec instructions that were removed 276system.cpu.iq.issued_per_cycle::samples 855191197 # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::mean 2.114462 # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::stdev 1.887618 # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::0 234669237 27.44% 27.44% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::1 145408124 17.00% 44.44% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::2 138604269 16.21% 60.65% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::3 132699771 15.52% 76.17% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::4 96142027 11.24% 87.41% # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::5 58835818 6.88% 94.29% # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::6 34929865 4.08% 98.37% # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::7 11989965 1.40% 99.78% # Number of insts issued each cycle 288system.cpu.iq.issued_per_cycle::8 1912121 0.22% 100.00% # Number of insts issued each cycle 289system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 290system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 291system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 292system.cpu.iq.issued_per_cycle::total 855191197 # Number of insts issued each cycle 293system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 294system.cpu.iq.fu_full::IntAlu 4982607 32.47% 32.47% # attempts to use FU when none available 295system.cpu.iq.fu_full::IntMult 0 0.00% 32.47% # attempts to use FU when none available 296system.cpu.iq.fu_full::IntDiv 0 0.00% 32.47% # attempts to use FU when none available 297system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.47% # attempts to use FU when none available 298system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.47% # attempts to use FU when none available 299system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.47% # attempts to use FU when none available 300system.cpu.iq.fu_full::FloatMult 0 0.00% 32.47% # attempts to use FU when none available 301system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.47% # attempts to use FU when none available 302system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.47% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.47% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.47% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.47% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.47% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.47% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.47% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdMult 0 0.00% 32.47% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.47% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdShift 0 0.00% 32.47% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.47% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.47% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.47% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.47% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.47% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.47% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.47% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.47% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.47% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.47% # attempts to use FU when none available 322system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.47% # attempts to use FU when none available 323system.cpu.iq.fu_full::MemRead 7772291 50.65% 83.11% # attempts to use FU when none available 324system.cpu.iq.fu_full::MemWrite 2591536 16.89% 100.00% # attempts to use FU when none available 325system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 326system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 327system.cpu.iq.FU_type_0::No_OpClass 2719540 0.15% 0.15% # Type of FU issued 328system.cpu.iq.FU_type_0::IntAlu 1190958422 65.86% 66.01% # Type of FU issued 329system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.01% # Type of FU issued 330system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued 331system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued 332system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued 333system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued 334system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued 335system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued 336system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued 348system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued 355system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued 356system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued 357system.cpu.iq.FU_type_0::MemRead 438908111 24.27% 90.28% # Type of FU issued 358system.cpu.iq.FU_type_0::MemWrite 175683013 9.72% 100.00% # Type of FU issued 359system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 360system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 361system.cpu.iq.FU_type_0::total 1808269086 # Type of FU issued 362system.cpu.iq.rate 2.080881 # Inst issue rate 363system.cpu.iq.fu_busy_cnt 15346434 # FU busy when requested 364system.cpu.iq.fu_busy_rate 0.008487 # FU busy rate (busy events/executed inst) 365system.cpu.iq.int_inst_queue_reads 4487893952 # Number of integer instruction queue reads 366system.cpu.iq.int_inst_queue_writes 2534230949 # Number of integer instruction queue writes 367system.cpu.iq.int_inst_queue_wakeup_accesses 1768791787 # Number of integer instruction queue wakeup accesses 368system.cpu.iq.fp_inst_queue_reads 22539 # Number of floating instruction queue reads 369system.cpu.iq.fp_inst_queue_writes 44036 # Number of floating instruction queue writes 370system.cpu.iq.fp_inst_queue_wakeup_accesses 5119 # Number of floating instruction queue wakeup accesses 371system.cpu.iq.int_alu_accesses 1820885356 # Number of integer alu accesses 372system.cpu.iq.fp_alu_accesses 10624 # Number of floating point alu accesses 373system.cpu.iew.lsq.thread0.forwLoads 170553013 # Number of loads that had data forwarded from stores 374system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 375system.cpu.iew.lsq.thread0.squashedLoads 128644663 # Number of loads squashed 376system.cpu.iew.lsq.thread0.ignoredResponses 472582 # Number of memory responses ignored because the instruction is squashed 377system.cpu.iew.lsq.thread0.memOrderViolation 269715 # Number of memory ordering violations 378system.cpu.iew.lsq.thread0.squashedStores 55788376 # Number of stores squashed 379system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 380system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 381system.cpu.iew.lsq.thread0.rescheduledLoads 12339 # Number of loads that were rescheduled 382system.cpu.iew.lsq.thread0.cacheBlocked 1555 # Number of times an access to memory failed due to the cache being blocked 383system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 384system.cpu.iew.iewSquashCycles 70043033 # Number of cycles IEW is squashing 385system.cpu.iew.iewBlockCycles 17673850 # Number of cycles IEW is blocking 386system.cpu.iew.iewUnblockCycles 2842089 # Number of cycles IEW is unblocking 387system.cpu.iew.iewDispatchedInsts 2034246059 # Number of instructions dispatched to IQ 388system.cpu.iew.iewDispSquashedInsts 2370262 # Number of squashed instructions skipped by dispatch 389system.cpu.iew.iewDispLoadInsts 512746819 # Number of dispatched load instructions 390system.cpu.iew.iewDispStoreInsts 204948561 # Number of dispatched store instructions 391system.cpu.iew.iewDispNonSpecInsts 6149 # Number of dispatched non-speculative instructions 392system.cpu.iew.iewIQFullEvents 1800682 # Number of times the IQ has become full, causing a stall 393system.cpu.iew.iewLSQFullEvents 76001 # Number of times the LSQ has become full, causing a stall 394system.cpu.iew.memOrderViolationEvents 269715 # Number of memory order violations 395system.cpu.iew.predictedTakenIncorrect 9110771 # Number of branches that were predicted taken incorrectly 396system.cpu.iew.predictedNotTakenIncorrect 4492681 # Number of branches that were predicted not taken incorrectly 397system.cpu.iew.branchMispredicts 13603452 # Number of branch mispredicts detected at execute 398system.cpu.iew.iewExecutedInsts 1780575608 # Number of executed instructions 399system.cpu.iew.iewExecLoadInsts 431395989 # Number of load instructions executed 400system.cpu.iew.iewExecSquashedInsts 27693478 # Number of squashed instructions skipped in execute 401system.cpu.iew.exec_swp 0 # number of swp insts executed 402system.cpu.iew.exec_nop 0 # number of nop insts executed 403system.cpu.iew.exec_refs 602081251 # number of memory reference insts executed 404system.cpu.iew.exec_branches 169281204 # Number of branches executed 405system.cpu.iew.exec_stores 170685262 # Number of stores executed 406system.cpu.iew.exec_rate 2.049012 # Inst execution rate 407system.cpu.iew.wb_sent 1775484026 # cumulative count of insts sent to commit 408system.cpu.iew.wb_count 1768796906 # cumulative count of insts written-back 409system.cpu.iew.wb_producers 1341657182 # num instructions producing a value 410system.cpu.iew.wb_consumers 1964610476 # num instructions consuming a value 411system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 412system.cpu.iew.wb_rate 2.035458 # insts written-back per cycle 413system.cpu.iew.wb_fanout 0.682913 # average fanout of values written-back 414system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 415system.cpu.commit.commitSquashedInsts 505293245 # The number of squashed insts skipped by commit 416system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards 417system.cpu.commit.branchMispredicts 13164973 # The number of times a branch was mispredicted 418system.cpu.commit.committed_per_cycle::samples 785148164 # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::mean 1.947389 # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::stdev 2.457160 # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::0 291743548 37.16% 37.16% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::1 195452528 24.89% 62.05% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::2 62380641 7.95% 70.00% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::3 92170452 11.74% 81.74% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::4 25089847 3.20% 84.93% # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::5 28355719 3.61% 88.54% # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::6 9376881 1.19% 89.74% # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::7 10764120 1.37% 91.11% # Number of insts commited each cycle 430system.cpu.commit.committed_per_cycle::8 69814428 8.89% 100.00% # Number of insts commited each cycle 431system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 432system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 433system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 434system.cpu.commit.committed_per_cycle::total 785148164 # Number of insts commited each cycle 435system.cpu.commit.committedInsts 826877109 # Number of instructions committed 436system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed 437system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 438system.cpu.commit.refs 533262341 # Number of memory references committed 439system.cpu.commit.loads 384102156 # Number of loads committed 440system.cpu.commit.membars 0 # Number of memory barriers committed 441system.cpu.commit.branches 149758583 # Number of branches committed 442system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 443system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. 444system.cpu.commit.function_calls 0 # Number of function calls committed. 445system.cpu.commit.bw_lim_events 69814428 # number cycles where commit BW limit reached 446system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 447system.cpu.rob.rob_reads 2749615680 # The number of ROB reads 448system.cpu.rob.rob_writes 4138789024 # The number of ROB writes 449system.cpu.timesIdled 344205 # Number of times that the entire CPU went into an idle state and unscheduled itself 450system.cpu.idleCycles 13801025 # Total number of cycles that the CPU has spent unscheduled due to idling 451system.cpu.committedInsts 826877109 # Number of Instructions Simulated 452system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated 453system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated 454system.cpu.cpi 1.050933 # CPI: Cycles Per Instruction 455system.cpu.cpi_total 1.050933 # CPI: Total CPI of All Threads 456system.cpu.ipc 0.951536 # IPC: Instructions Per Cycle 457system.cpu.ipc_total 0.951536 # IPC: Total IPC of All Threads 458system.cpu.int_regfile_reads 3357495880 # number of integer regfile reads 459system.cpu.int_regfile_writes 1848564966 # number of integer regfile writes 460system.cpu.fp_regfile_reads 5116 # number of floating regfile reads 461system.cpu.fp_regfile_writes 3 # number of floating regfile writes 462system.cpu.misc_regfile_reads 980239891 # number of misc regfile reads 463system.cpu.icache.replacements 5389 # number of replacements 464system.cpu.icache.tagsinuse 1038.396160 # Cycle average of tags in use 465system.cpu.icache.total_refs 173252420 # Total number of references to valid blocks. 466system.cpu.icache.sampled_refs 6992 # Sample count of references to valid blocks. 467system.cpu.icache.avg_refs 24778.664188 # Average number of references to valid blocks. 468system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 469system.cpu.icache.occ_blocks::cpu.inst 1038.396160 # Average occupied blocks per requestor 470system.cpu.icache.occ_percent::cpu.inst 0.507029 # Average percentage of cache occupancy 471system.cpu.icache.occ_percent::total 0.507029 # Average percentage of cache occupancy 472system.cpu.icache.ReadReq_hits::cpu.inst 173268230 # number of ReadReq hits 473system.cpu.icache.ReadReq_hits::total 173268230 # number of ReadReq hits 474system.cpu.icache.demand_hits::cpu.inst 173268230 # number of demand (read+write) hits 475system.cpu.icache.demand_hits::total 173268230 # number of demand (read+write) hits 476system.cpu.icache.overall_hits::cpu.inst 173268230 # number of overall hits 477system.cpu.icache.overall_hits::total 173268230 # number of overall hits 478system.cpu.icache.ReadReq_misses::cpu.inst 221529 # number of ReadReq misses 479system.cpu.icache.ReadReq_misses::total 221529 # number of ReadReq misses 480system.cpu.icache.demand_misses::cpu.inst 221529 # number of demand (read+write) misses 481system.cpu.icache.demand_misses::total 221529 # number of demand (read+write) misses 482system.cpu.icache.overall_misses::cpu.inst 221529 # number of overall misses 483system.cpu.icache.overall_misses::total 221529 # number of overall misses 484system.cpu.icache.ReadReq_miss_latency::cpu.inst 1367876999 # number of ReadReq miss cycles 485system.cpu.icache.ReadReq_miss_latency::total 1367876999 # number of ReadReq miss cycles 486system.cpu.icache.demand_miss_latency::cpu.inst 1367876999 # number of demand (read+write) miss cycles 487system.cpu.icache.demand_miss_latency::total 1367876999 # number of demand (read+write) miss cycles 488system.cpu.icache.overall_miss_latency::cpu.inst 1367876999 # number of overall miss cycles 489system.cpu.icache.overall_miss_latency::total 1367876999 # number of overall miss cycles 490system.cpu.icache.ReadReq_accesses::cpu.inst 173489759 # number of ReadReq accesses(hits+misses) 491system.cpu.icache.ReadReq_accesses::total 173489759 # number of ReadReq accesses(hits+misses) 492system.cpu.icache.demand_accesses::cpu.inst 173489759 # number of demand (read+write) accesses 493system.cpu.icache.demand_accesses::total 173489759 # number of demand (read+write) accesses 494system.cpu.icache.overall_accesses::cpu.inst 173489759 # number of overall (read+write) accesses 495system.cpu.icache.overall_accesses::total 173489759 # number of overall (read+write) accesses 496system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001277 # miss rate for ReadReq accesses 497system.cpu.icache.ReadReq_miss_rate::total 0.001277 # miss rate for ReadReq accesses 498system.cpu.icache.demand_miss_rate::cpu.inst 0.001277 # miss rate for demand accesses 499system.cpu.icache.demand_miss_rate::total 0.001277 # miss rate for demand accesses 500system.cpu.icache.overall_miss_rate::cpu.inst 0.001277 # miss rate for overall accesses 501system.cpu.icache.overall_miss_rate::total 0.001277 # miss rate for overall accesses 502system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6174.708499 # average ReadReq miss latency 503system.cpu.icache.ReadReq_avg_miss_latency::total 6174.708499 # average ReadReq miss latency 504system.cpu.icache.demand_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency 505system.cpu.icache.demand_avg_miss_latency::total 6174.708499 # average overall miss latency 506system.cpu.icache.overall_avg_miss_latency::cpu.inst 6174.708499 # average overall miss latency 507system.cpu.icache.overall_avg_miss_latency::total 6174.708499 # average overall miss latency 508system.cpu.icache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked 509system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 510system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked 511system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 512system.cpu.icache.avg_blocked_cycles::no_mshrs 27.555556 # average number of cycles each access was blocked 513system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 514system.cpu.icache.fast_writes 0 # number of fast writes performed 515system.cpu.icache.cache_copies 0 # number of cache copies performed 516system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2325 # number of ReadReq MSHR hits 517system.cpu.icache.ReadReq_mshr_hits::total 2325 # number of ReadReq MSHR hits 518system.cpu.icache.demand_mshr_hits::cpu.inst 2325 # number of demand (read+write) MSHR hits 519system.cpu.icache.demand_mshr_hits::total 2325 # number of demand (read+write) MSHR hits 520system.cpu.icache.overall_mshr_hits::cpu.inst 2325 # number of overall MSHR hits 521system.cpu.icache.overall_mshr_hits::total 2325 # number of overall MSHR hits 522system.cpu.icache.ReadReq_mshr_misses::cpu.inst 219204 # number of ReadReq MSHR misses 523system.cpu.icache.ReadReq_mshr_misses::total 219204 # number of ReadReq MSHR misses 524system.cpu.icache.demand_mshr_misses::cpu.inst 219204 # number of demand (read+write) MSHR misses 525system.cpu.icache.demand_mshr_misses::total 219204 # number of demand (read+write) MSHR misses 526system.cpu.icache.overall_mshr_misses::cpu.inst 219204 # number of overall MSHR misses 527system.cpu.icache.overall_mshr_misses::total 219204 # number of overall MSHR misses 528system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 865886999 # number of ReadReq MSHR miss cycles 529system.cpu.icache.ReadReq_mshr_miss_latency::total 865886999 # number of ReadReq MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::cpu.inst 865886999 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.demand_mshr_miss_latency::total 865886999 # number of demand (read+write) MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::cpu.inst 865886999 # number of overall MSHR miss cycles 533system.cpu.icache.overall_mshr_miss_latency::total 865886999 # number of overall MSHR miss cycles 534system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for ReadReq accesses 535system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001263 # mshr miss rate for ReadReq accesses 536system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for demand accesses 537system.cpu.icache.demand_mshr_miss_rate::total 0.001263 # mshr miss rate for demand accesses 538system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001263 # mshr miss rate for overall accesses 539system.cpu.icache.overall_mshr_miss_rate::total 0.001263 # mshr miss rate for overall accesses 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3950.142329 # average ReadReq mshr miss latency 541system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3950.142329 # average ReadReq mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3950.142329 # average overall mshr miss latency 543system.cpu.icache.demand_avg_mshr_miss_latency::total 3950.142329 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3950.142329 # average overall mshr miss latency 545system.cpu.icache.overall_avg_mshr_miss_latency::total 3950.142329 # average overall mshr miss latency 546system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 547system.cpu.l2cache.replacements 352935 # number of replacements 548system.cpu.l2cache.tagsinuse 29621.088782 # Cycle average of tags in use 549system.cpu.l2cache.total_refs 3697485 # Total number of references to valid blocks. 550system.cpu.l2cache.sampled_refs 385298 # Sample count of references to valid blocks. 551system.cpu.l2cache.avg_refs 9.596429 # Average number of references to valid blocks. 552system.cpu.l2cache.warmup_cycle 201835510000 # Cycle when the warmup percentage was hit. 553system.cpu.l2cache.occ_blocks::writebacks 21057.332027 # Average occupied blocks per requestor 554system.cpu.l2cache.occ_blocks::cpu.inst 231.203913 # Average occupied blocks per requestor 555system.cpu.l2cache.occ_blocks::cpu.data 8332.552842 # Average occupied blocks per requestor 556system.cpu.l2cache.occ_percent::writebacks 0.642619 # Average percentage of cache occupancy 557system.cpu.l2cache.occ_percent::cpu.inst 0.007056 # Average percentage of cache occupancy 558system.cpu.l2cache.occ_percent::cpu.data 0.254289 # Average percentage of cache occupancy 559system.cpu.l2cache.occ_percent::total 0.903964 # Average percentage of cache occupancy 560system.cpu.l2cache.ReadReq_hits::cpu.inst 3731 # number of ReadReq hits 561system.cpu.l2cache.ReadReq_hits::cpu.data 1586467 # number of ReadReq hits 562system.cpu.l2cache.ReadReq_hits::total 1590198 # number of ReadReq hits 563system.cpu.l2cache.Writeback_hits::writebacks 2331049 # number of Writeback hits 564system.cpu.l2cache.Writeback_hits::total 2331049 # number of Writeback hits 565system.cpu.l2cache.UpgradeReq_hits::cpu.data 1506 # number of UpgradeReq hits 566system.cpu.l2cache.UpgradeReq_hits::total 1506 # number of UpgradeReq hits 567system.cpu.l2cache.ReadExReq_hits::cpu.data 564628 # number of ReadExReq hits 568system.cpu.l2cache.ReadExReq_hits::total 564628 # number of ReadExReq hits 569system.cpu.l2cache.demand_hits::cpu.inst 3731 # number of demand (read+write) hits 570system.cpu.l2cache.demand_hits::cpu.data 2151095 # number of demand (read+write) hits 571system.cpu.l2cache.demand_hits::total 2154826 # number of demand (read+write) hits 572system.cpu.l2cache.overall_hits::cpu.inst 3731 # number of overall hits 573system.cpu.l2cache.overall_hits::cpu.data 2151095 # number of overall hits 574system.cpu.l2cache.overall_hits::total 2154826 # number of overall hits 575system.cpu.l2cache.ReadReq_misses::cpu.inst 3216 # number of ReadReq misses 576system.cpu.l2cache.ReadReq_misses::cpu.data 175678 # number of ReadReq misses 577system.cpu.l2cache.ReadReq_misses::total 178894 # number of ReadReq misses 578system.cpu.l2cache.UpgradeReq_misses::cpu.data 210659 # number of UpgradeReq misses 579system.cpu.l2cache.UpgradeReq_misses::total 210659 # number of UpgradeReq misses 580system.cpu.l2cache.ReadExReq_misses::cpu.data 206756 # number of ReadExReq misses 581system.cpu.l2cache.ReadExReq_misses::total 206756 # number of ReadExReq misses 582system.cpu.l2cache.demand_misses::cpu.inst 3216 # number of demand (read+write) misses 583system.cpu.l2cache.demand_misses::cpu.data 382434 # number of demand (read+write) misses 584system.cpu.l2cache.demand_misses::total 385650 # number of demand (read+write) misses 585system.cpu.l2cache.overall_misses::cpu.inst 3216 # number of overall misses 586system.cpu.l2cache.overall_misses::cpu.data 382434 # number of overall misses 587system.cpu.l2cache.overall_misses::total 385650 # number of overall misses 588system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 180593000 # number of ReadReq miss cycles 589system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9239203954 # number of ReadReq miss cycles 590system.cpu.l2cache.ReadReq_miss_latency::total 9419796954 # number of ReadReq miss cycles 591system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7234500 # number of UpgradeReq miss cycles 592system.cpu.l2cache.UpgradeReq_miss_latency::total 7234500 # number of UpgradeReq miss cycles 593system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10965110500 # number of ReadExReq miss cycles 594system.cpu.l2cache.ReadExReq_miss_latency::total 10965110500 # number of ReadExReq miss cycles 595system.cpu.l2cache.demand_miss_latency::cpu.inst 180593000 # number of demand (read+write) miss cycles 596system.cpu.l2cache.demand_miss_latency::cpu.data 20204314454 # number of demand (read+write) miss cycles 597system.cpu.l2cache.demand_miss_latency::total 20384907454 # number of demand (read+write) miss cycles 598system.cpu.l2cache.overall_miss_latency::cpu.inst 180593000 # number of overall miss cycles 599system.cpu.l2cache.overall_miss_latency::cpu.data 20204314454 # number of overall miss cycles 600system.cpu.l2cache.overall_miss_latency::total 20384907454 # number of overall miss cycles 601system.cpu.l2cache.ReadReq_accesses::cpu.inst 6947 # number of ReadReq accesses(hits+misses) 602system.cpu.l2cache.ReadReq_accesses::cpu.data 1762145 # number of ReadReq accesses(hits+misses) 603system.cpu.l2cache.ReadReq_accesses::total 1769092 # number of ReadReq accesses(hits+misses) 604system.cpu.l2cache.Writeback_accesses::writebacks 2331049 # number of Writeback accesses(hits+misses) 605system.cpu.l2cache.Writeback_accesses::total 2331049 # number of Writeback accesses(hits+misses) 606system.cpu.l2cache.UpgradeReq_accesses::cpu.data 212165 # number of UpgradeReq accesses(hits+misses) 607system.cpu.l2cache.UpgradeReq_accesses::total 212165 # number of UpgradeReq accesses(hits+misses) 608system.cpu.l2cache.ReadExReq_accesses::cpu.data 771384 # number of ReadExReq accesses(hits+misses) 609system.cpu.l2cache.ReadExReq_accesses::total 771384 # number of ReadExReq accesses(hits+misses) 610system.cpu.l2cache.demand_accesses::cpu.inst 6947 # number of demand (read+write) accesses 611system.cpu.l2cache.demand_accesses::cpu.data 2533529 # number of demand (read+write) accesses 612system.cpu.l2cache.demand_accesses::total 2540476 # number of demand (read+write) accesses 613system.cpu.l2cache.overall_accesses::cpu.inst 6947 # number of overall (read+write) accesses 614system.cpu.l2cache.overall_accesses::cpu.data 2533529 # number of overall (read+write) accesses 615system.cpu.l2cache.overall_accesses::total 2540476 # number of overall (read+write) accesses 616system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.462934 # miss rate for ReadReq accesses 617system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099696 # miss rate for ReadReq accesses 618system.cpu.l2cache.ReadReq_miss_rate::total 0.101122 # miss rate for ReadReq accesses 619system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.992902 # miss rate for UpgradeReq accesses 620system.cpu.l2cache.UpgradeReq_miss_rate::total 0.992902 # miss rate for UpgradeReq accesses 621system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268033 # miss rate for ReadExReq accesses 622system.cpu.l2cache.ReadExReq_miss_rate::total 0.268033 # miss rate for ReadExReq accesses 623system.cpu.l2cache.demand_miss_rate::cpu.inst 0.462934 # miss rate for demand accesses 624system.cpu.l2cache.demand_miss_rate::cpu.data 0.150949 # miss rate for demand accesses 625system.cpu.l2cache.demand_miss_rate::total 0.151802 # miss rate for demand accesses 626system.cpu.l2cache.overall_miss_rate::cpu.inst 0.462934 # miss rate for overall accesses 627system.cpu.l2cache.overall_miss_rate::cpu.data 0.150949 # miss rate for overall accesses 628system.cpu.l2cache.overall_miss_rate::total 0.151802 # miss rate for overall accesses 629system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56154.539801 # average ReadReq miss latency 630system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52591.695910 # average ReadReq miss latency 631system.cpu.l2cache.ReadReq_avg_miss_latency::total 52655.745604 # average ReadReq miss latency 632system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 34.342231 # average UpgradeReq miss latency 633system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34.342231 # average UpgradeReq miss latency 634system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53034.061889 # average ReadExReq miss latency 635system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53034.061889 # average ReadExReq miss latency 636system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56154.539801 # average overall miss latency 637system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52830.853047 # average overall miss latency 638system.cpu.l2cache.demand_avg_miss_latency::total 52858.569828 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56154.539801 # average overall miss latency 640system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52830.853047 # average overall miss latency 641system.cpu.l2cache.overall_avg_miss_latency::total 52858.569828 # average overall miss latency 642system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 643system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 645system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 646system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 647system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.l2cache.fast_writes 0 # number of fast writes performed 649system.cpu.l2cache.cache_copies 0 # number of cache copies performed 650system.cpu.l2cache.writebacks::writebacks 293652 # number of writebacks 651system.cpu.l2cache.writebacks::total 293652 # number of writebacks 652system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3216 # number of ReadReq MSHR misses 653system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175678 # number of ReadReq MSHR misses 654system.cpu.l2cache.ReadReq_mshr_misses::total 178894 # number of ReadReq MSHR misses 655system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 210659 # number of UpgradeReq MSHR misses 656system.cpu.l2cache.UpgradeReq_mshr_misses::total 210659 # number of UpgradeReq MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206756 # number of ReadExReq MSHR misses 658system.cpu.l2cache.ReadExReq_mshr_misses::total 206756 # number of ReadExReq MSHR misses 659system.cpu.l2cache.demand_mshr_misses::cpu.inst 3216 # number of demand (read+write) MSHR misses 660system.cpu.l2cache.demand_mshr_misses::cpu.data 382434 # number of demand (read+write) MSHR misses 661system.cpu.l2cache.demand_mshr_misses::total 385650 # number of demand (read+write) MSHR misses 662system.cpu.l2cache.overall_mshr_misses::cpu.inst 3216 # number of overall MSHR misses 663system.cpu.l2cache.overall_mshr_misses::cpu.data 382434 # number of overall MSHR misses 664system.cpu.l2cache.overall_mshr_misses::total 385650 # number of overall MSHR misses 665system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 139955386 # number of ReadReq MSHR miss cycles 666system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6977520482 # number of ReadReq MSHR miss cycles 667system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7117475868 # number of ReadReq MSHR miss cycles 668system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2112120744 # number of UpgradeReq MSHR miss cycles 669system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2112120744 # number of UpgradeReq MSHR miss cycles 670system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8331237791 # number of ReadExReq MSHR miss cycles 671system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8331237791 # number of ReadExReq MSHR miss cycles 672system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139955386 # number of demand (read+write) MSHR miss cycles 673system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15308758273 # number of demand (read+write) MSHR miss cycles 674system.cpu.l2cache.demand_mshr_miss_latency::total 15448713659 # number of demand (read+write) MSHR miss cycles 675system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139955386 # number of overall MSHR miss cycles 676system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15308758273 # number of overall MSHR miss cycles 677system.cpu.l2cache.overall_mshr_miss_latency::total 15448713659 # number of overall MSHR miss cycles 678system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.462934 # mshr miss rate for ReadReq accesses 679system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099696 # mshr miss rate for ReadReq accesses 680system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101122 # mshr miss rate for ReadReq accesses 681system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.992902 # mshr miss rate for UpgradeReq accesses 682system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.992902 # mshr miss rate for UpgradeReq accesses 683system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268033 # mshr miss rate for ReadExReq accesses 684system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268033 # mshr miss rate for ReadExReq accesses 685system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.462934 # mshr miss rate for demand accesses 686system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150949 # mshr miss rate for demand accesses 687system.cpu.l2cache.demand_mshr_miss_rate::total 0.151802 # mshr miss rate for demand accesses 688system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.462934 # mshr miss rate for overall accesses 689system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150949 # mshr miss rate for overall accesses 690system.cpu.l2cache.overall_mshr_miss_rate::total 0.151802 # mshr miss rate for overall accesses 691system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43518.465796 # average ReadReq mshr miss latency 692system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39717.668018 # average ReadReq mshr miss latency 693system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39785.995439 # average ReadReq mshr miss latency 694system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.254487 # average UpgradeReq mshr miss latency 695system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.254487 # average UpgradeReq mshr miss latency 696system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40295.023076 # average ReadExReq mshr miss latency 697system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40295.023076 # average ReadExReq mshr miss latency 698system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43518.465796 # average overall mshr miss latency 699system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40029.804549 # average overall mshr miss latency 700system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40058.897080 # average overall mshr miss latency 701system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43518.465796 # average overall mshr miss latency 702system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40029.804549 # average overall mshr miss latency 703system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40058.897080 # average overall mshr miss latency 704system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 705system.cpu.dcache.replacements 2529431 # number of replacements 706system.cpu.dcache.tagsinuse 4087.842516 # Cycle average of tags in use 707system.cpu.dcache.total_refs 405341407 # Total number of references to valid blocks. 708system.cpu.dcache.sampled_refs 2533527 # Sample count of references to valid blocks. 709system.cpu.dcache.avg_refs 159.990956 # Average number of references to valid blocks. 710system.cpu.dcache.warmup_cycle 1787438000 # Cycle when the warmup percentage was hit. 711system.cpu.dcache.occ_blocks::cpu.data 4087.842516 # Average occupied blocks per requestor 712system.cpu.dcache.occ_percent::cpu.data 0.998008 # Average percentage of cache occupancy 713system.cpu.dcache.occ_percent::total 0.998008 # Average percentage of cache occupancy 714system.cpu.dcache.ReadReq_hits::cpu.data 256611582 # number of ReadReq hits 715system.cpu.dcache.ReadReq_hits::total 256611582 # number of ReadReq hits 716system.cpu.dcache.WriteReq_hits::cpu.data 148160067 # number of WriteReq hits 717system.cpu.dcache.WriteReq_hits::total 148160067 # number of WriteReq hits 718system.cpu.dcache.demand_hits::cpu.data 404771649 # number of demand (read+write) hits 719system.cpu.dcache.demand_hits::total 404771649 # number of demand (read+write) hits 720system.cpu.dcache.overall_hits::cpu.data 404771649 # number of overall hits 721system.cpu.dcache.overall_hits::total 404771649 # number of overall hits 722system.cpu.dcache.ReadReq_misses::cpu.data 2888518 # number of ReadReq misses 723system.cpu.dcache.ReadReq_misses::total 2888518 # number of ReadReq misses 724system.cpu.dcache.WriteReq_misses::cpu.data 1000134 # number of WriteReq misses 725system.cpu.dcache.WriteReq_misses::total 1000134 # number of WriteReq misses 726system.cpu.dcache.demand_misses::cpu.data 3888652 # number of demand (read+write) misses 727system.cpu.dcache.demand_misses::total 3888652 # number of demand (read+write) misses 728system.cpu.dcache.overall_misses::cpu.data 3888652 # number of overall misses 729system.cpu.dcache.overall_misses::total 3888652 # number of overall misses 730system.cpu.dcache.ReadReq_miss_latency::cpu.data 49903831500 # number of ReadReq miss cycles 731system.cpu.dcache.ReadReq_miss_latency::total 49903831500 # number of ReadReq miss cycles 732system.cpu.dcache.WriteReq_miss_latency::cpu.data 24367147000 # number of WriteReq miss cycles 733system.cpu.dcache.WriteReq_miss_latency::total 24367147000 # number of WriteReq miss cycles 734system.cpu.dcache.demand_miss_latency::cpu.data 74270978500 # number of demand (read+write) miss cycles 735system.cpu.dcache.demand_miss_latency::total 74270978500 # number of demand (read+write) miss cycles 736system.cpu.dcache.overall_miss_latency::cpu.data 74270978500 # number of overall miss cycles 737system.cpu.dcache.overall_miss_latency::total 74270978500 # number of overall miss cycles 738system.cpu.dcache.ReadReq_accesses::cpu.data 259500100 # number of ReadReq accesses(hits+misses) 739system.cpu.dcache.ReadReq_accesses::total 259500100 # number of ReadReq accesses(hits+misses) 740system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 741system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 742system.cpu.dcache.demand_accesses::cpu.data 408660301 # number of demand (read+write) accesses 743system.cpu.dcache.demand_accesses::total 408660301 # number of demand (read+write) accesses 744system.cpu.dcache.overall_accesses::cpu.data 408660301 # number of overall (read+write) accesses 745system.cpu.dcache.overall_accesses::total 408660301 # number of overall (read+write) accesses 746system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011131 # miss rate for ReadReq accesses 747system.cpu.dcache.ReadReq_miss_rate::total 0.011131 # miss rate for ReadReq accesses 748system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006705 # miss rate for WriteReq accesses 749system.cpu.dcache.WriteReq_miss_rate::total 0.006705 # miss rate for WriteReq accesses 750system.cpu.dcache.demand_miss_rate::cpu.data 0.009516 # miss rate for demand accesses 751system.cpu.dcache.demand_miss_rate::total 0.009516 # miss rate for demand accesses 752system.cpu.dcache.overall_miss_rate::cpu.data 0.009516 # miss rate for overall accesses 753system.cpu.dcache.overall_miss_rate::total 0.009516 # miss rate for overall accesses 754system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17276.621264 # average ReadReq miss latency 755system.cpu.dcache.ReadReq_avg_miss_latency::total 17276.621264 # average ReadReq miss latency 756system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24363.882240 # average WriteReq miss latency 757system.cpu.dcache.WriteReq_avg_miss_latency::total 24363.882240 # average WriteReq miss latency 758system.cpu.dcache.demand_avg_miss_latency::cpu.data 19099.415042 # average overall miss latency 759system.cpu.dcache.demand_avg_miss_latency::total 19099.415042 # average overall miss latency 760system.cpu.dcache.overall_avg_miss_latency::cpu.data 19099.415042 # average overall miss latency 761system.cpu.dcache.overall_avg_miss_latency::total 19099.415042 # average overall miss latency 762system.cpu.dcache.blocked_cycles::no_mshrs 7749 # number of cycles access was blocked 763system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu.dcache.blocked::no_mshrs 632 # number of cycles access was blocked 765system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.261076 # average number of cycles each access was blocked 767system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu.dcache.fast_writes 0 # number of fast writes performed 769system.cpu.dcache.cache_copies 0 # number of cache copies performed 770system.cpu.dcache.writebacks::writebacks 2331049 # number of writebacks 771system.cpu.dcache.writebacks::total 2331049 # number of writebacks 772system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126114 # number of ReadReq MSHR hits 773system.cpu.dcache.ReadReq_mshr_hits::total 1126114 # number of ReadReq MSHR hits 774system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16846 # number of WriteReq MSHR hits 775system.cpu.dcache.WriteReq_mshr_hits::total 16846 # number of WriteReq MSHR hits 776system.cpu.dcache.demand_mshr_hits::cpu.data 1142960 # number of demand (read+write) MSHR hits 777system.cpu.dcache.demand_mshr_hits::total 1142960 # number of demand (read+write) MSHR hits 778system.cpu.dcache.overall_mshr_hits::cpu.data 1142960 # number of overall MSHR hits 779system.cpu.dcache.overall_mshr_hits::total 1142960 # number of overall MSHR hits 780system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762404 # number of ReadReq MSHR misses 781system.cpu.dcache.ReadReq_mshr_misses::total 1762404 # number of ReadReq MSHR misses 782system.cpu.dcache.WriteReq_mshr_misses::cpu.data 983288 # number of WriteReq MSHR misses 783system.cpu.dcache.WriteReq_mshr_misses::total 983288 # number of WriteReq MSHR misses 784system.cpu.dcache.demand_mshr_misses::cpu.data 2745692 # number of demand (read+write) MSHR misses 785system.cpu.dcache.demand_mshr_misses::total 2745692 # number of demand (read+write) MSHR misses 786system.cpu.dcache.overall_mshr_misses::cpu.data 2745692 # number of overall MSHR misses 787system.cpu.dcache.overall_mshr_misses::total 2745692 # number of overall MSHR misses 788system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26902331000 # number of ReadReq MSHR miss cycles 789system.cpu.dcache.ReadReq_mshr_miss_latency::total 26902331000 # number of ReadReq MSHR miss cycles 790system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 22198368000 # number of WriteReq MSHR miss cycles 791system.cpu.dcache.WriteReq_mshr_miss_latency::total 22198368000 # number of WriteReq MSHR miss cycles 792system.cpu.dcache.demand_mshr_miss_latency::cpu.data 49100699000 # number of demand (read+write) MSHR miss cycles 793system.cpu.dcache.demand_mshr_miss_latency::total 49100699000 # number of demand (read+write) MSHR miss cycles 794system.cpu.dcache.overall_mshr_miss_latency::cpu.data 49100699000 # number of overall MSHR miss cycles 795system.cpu.dcache.overall_mshr_miss_latency::total 49100699000 # number of overall MSHR miss cycles 796system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006792 # mshr miss rate for ReadReq accesses 797system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006792 # mshr miss rate for ReadReq accesses 798system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006592 # mshr miss rate for WriteReq accesses 799system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006592 # mshr miss rate for WriteReq accesses 800system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for demand accesses 801system.cpu.dcache.demand_mshr_miss_rate::total 0.006719 # mshr miss rate for demand accesses 802system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006719 # mshr miss rate for overall accesses 803system.cpu.dcache.overall_mshr_miss_rate::total 0.006719 # mshr miss rate for overall accesses 804system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15264.565332 # average ReadReq mshr miss latency 805system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15264.565332 # average ReadReq mshr miss latency 806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22575.652301 # average WriteReq mshr miss latency 807system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22575.652301 # average WriteReq mshr miss latency 808system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency 809system.cpu.dcache.demand_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency 810system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17882.813877 # average overall mshr miss latency 811system.cpu.dcache.overall_avg_mshr_miss_latency::total 17882.813877 # average overall mshr miss latency 812system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 813 814---------- End Simulation Statistics ---------- 815