stats.txt revision 9322:01c8c5ff2c3b
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.447151 # Number of seconds simulated 4sim_ticks 447151291000 # Number of ticks simulated 5final_tick 447151291000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 99582 # Simulator instruction rate (inst/s) 8host_op_rate 184139 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53851139 # Simulator tick rate (ticks/s) 10host_mem_usage 337048 # Number of bytes of host memory used 11host_seconds 8303.47 # Real time elapsed on the host 12sim_insts 826877109 # Number of instructions simulated 13sim_ops 1528988699 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 207040 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24466624 # Number of bytes read from this memory 16system.physmem.bytes_read::total 24673664 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 207040 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 207040 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 18786368 # Number of bytes written to this memory 20system.physmem.bytes_written::total 18786368 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 3235 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 382291 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 385526 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 293537 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 293537 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 463020 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 54716657 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 55179677 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 463020 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 463020 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 42013449 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 42013449 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 42013449 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 463020 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 54716657 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 97193127 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 385528 # Total number of read requests seen 38system.physmem.writeReqs 293537 # Total number of write requests seen 39system.physmem.cpureqs 863596 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 24673664 # Total number of bytes read from memory 41system.physmem.bytesWritten 18786368 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 24673664 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 18786368 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 164 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 184531 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 24996 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 23035 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 24534 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 25301 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 24892 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 24563 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 23920 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 24683 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 22800 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 23577 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 23208 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 23396 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 24161 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 24133 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 24010 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 24155 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 19354 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 17947 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 18690 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 18990 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 19041 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 18723 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 18099 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 18501 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 17450 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 17927 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 17723 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 17609 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 18440 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 18279 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 18321 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 18443 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 447151273000 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 385528 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 293537 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 184531 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 380682 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 4205 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 406 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 12758 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 12762 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 12763 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 12763 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 12763 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 12763 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 12763 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 12763 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 12763 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 12763 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 12763 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 12762 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 12762 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 12762 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 12762 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 12762 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 12762 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 12762 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 12762 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 12762 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 12762 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 12762 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 12762 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 3526127005 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 11592689005 # Sum of mem lat for all requests 176system.physmem.totBusLat 1541456000 # Total cycles spent in databus access 177system.physmem.totBankLat 6525106000 # Total cycles spent in bank access 178system.physmem.avgQLat 9150.12 # Average queueing delay per request 179system.physmem.avgBankLat 16932.32 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 30082.44 # Average memory access latency 182system.physmem.avgRdBW 55.18 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 42.01 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 55.18 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 42.01 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.61 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.03 # Average read queue length over time 189system.physmem.avgWrQLen 8.93 # Average write queue length over time 190system.physmem.readRowHits 340552 # Number of row buffer hits during reads 191system.physmem.writeRowHits 151633 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 88.37 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 51.66 # Row buffer hit rate for writes 194system.physmem.avgGap 658480.81 # Average gap between requests 195system.cpu.workload.num_syscalls 551 # Number of system calls 196system.cpu.numCycles 894302583 # number of cpu cycles simulated 197system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 198system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 199system.cpu.BPredUnit.lookups 221834419 # Number of BP lookups 200system.cpu.BPredUnit.condPredicted 221834419 # Number of conditional branches predicted 201system.cpu.BPredUnit.condIncorrect 14438837 # Number of conditional branches incorrect 202system.cpu.BPredUnit.BTBLookups 157195941 # Number of BTB lookups 203system.cpu.BPredUnit.BTBHits 152967077 # Number of BTB hits 204system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 205system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 206system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 207system.cpu.fetch.icacheStallCycles 187305514 # Number of cycles fetch is stalled on an Icache miss 208system.cpu.fetch.Insts 1233712111 # Number of instructions fetch has processed 209system.cpu.fetch.Branches 221834419 # Number of branches that fetch encountered 210system.cpu.fetch.predictedBranches 152967077 # Number of branches that fetch has predicted taken 211system.cpu.fetch.Cycles 383213555 # Number of cycles fetch has run and was not squashing or blocked 212system.cpu.fetch.SquashCycles 92482547 # Number of cycles fetch has spent squashing 213system.cpu.fetch.BlockedCycles 231997744 # Number of cycles fetch has spent blocked 214system.cpu.fetch.MiscStallCycles 31125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 215system.cpu.fetch.PendingTrapStallCycles 302541 # Number of stall cycles due to pending traps 216system.cpu.fetch.IcacheWaitRetryStallCycles 64 # Number of stall cycles due to full MSHR 217system.cpu.fetch.CacheLines 179659779 # Number of cache lines fetched 218system.cpu.fetch.IcacheSquashes 4113909 # Number of outstanding Icache misses that were squashed 219system.cpu.fetch.rateDist::samples 880638441 # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::mean 2.600745 # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::stdev 3.391861 # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::0 501847528 56.99% 56.99% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::1 25496575 2.90% 59.88% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::2 28121767 3.19% 63.08% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::3 29451767 3.34% 66.42% # Number of instructions fetched each cycle (Total) 227system.cpu.fetch.rateDist::4 18987914 2.16% 68.58% # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::5 25123088 2.85% 71.43% # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::6 31720196 3.60% 75.03% # Number of instructions fetched each cycle (Total) 230system.cpu.fetch.rateDist::7 30784274 3.50% 78.53% # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.rateDist::8 189105332 21.47% 100.00% # Number of instructions fetched each cycle (Total) 232system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 233system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 234system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 235system.cpu.fetch.rateDist::total 880638441 # Number of instructions fetched each cycle (Total) 236system.cpu.fetch.branchRate 0.248053 # Number of branch fetches per cycle 237system.cpu.fetch.rate 1.379524 # Number of inst fetches per cycle 238system.cpu.decode.IdleCycles 244537844 # Number of cycles decode is idle 239system.cpu.decode.BlockedCycles 188536263 # Number of cycles decode is blocked 240system.cpu.decode.RunCycles 324191261 # Number of cycles decode is running 241system.cpu.decode.UnblockCycles 45585175 # Number of cycles decode is unblocking 242system.cpu.decode.SquashCycles 77787898 # Number of cycles decode is squashing 243system.cpu.decode.DecodedInsts 2236907904 # Number of instructions handled by decode 244system.cpu.rename.SquashCycles 77787898 # Number of cycles rename is squashing 245system.cpu.rename.IdleCycles 278585274 # Number of cycles rename is idle 246system.cpu.rename.BlockCycles 54813178 # Number of cycles rename is blocking 247system.cpu.rename.serializeStallCycles 15041 # count of cycles rename stalled for serializing inst 248system.cpu.rename.RunCycles 333395312 # Number of cycles rename is running 249system.cpu.rename.UnblockCycles 136041738 # Number of cycles rename is unblocking 250system.cpu.rename.RenamedInsts 2184748951 # Number of instructions processed by rename 251system.cpu.rename.ROBFullEvents 34526 # Number of times rename has blocked due to ROB full 252system.cpu.rename.IQFullEvents 20261515 # Number of times rename has blocked due to IQ full 253system.cpu.rename.LSQFullEvents 101530735 # Number of times rename has blocked due to LSQ full 254system.cpu.rename.FullRegisterEvents 116 # Number of times there has been no free registers 255system.cpu.rename.RenamedOperands 2284488026 # Number of destination operands rename has renamed 256system.cpu.rename.RenameLookups 5524710294 # Number of register rename lookups that rename has made 257system.cpu.rename.int_rename_lookups 5524485031 # Number of integer rename lookups 258system.cpu.rename.fp_rename_lookups 225263 # Number of floating rename lookups 259system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed 260system.cpu.rename.UndoneMaps 670447175 # Number of HB maps that are undone due to squashing 261system.cpu.rename.serializingInsts 1310 # count of serializing insts renamed 262system.cpu.rename.tempSerializingInsts 1291 # count of temporary serializing insts renamed 263system.cpu.rename.skidInsts 328673064 # count of insts added to the skid buffer 264system.cpu.memDep0.insertedLoads 528947917 # Number of loads inserted to the mem dependence unit. 265system.cpu.memDep0.insertedStores 211077156 # Number of stores inserted to the mem dependence unit. 266system.cpu.memDep0.conflictingLoads 202192665 # Number of conflicting loads. 267system.cpu.memDep0.conflictingStores 58804191 # Number of conflicting stores. 268system.cpu.iq.iqInstsAdded 2090539379 # Number of instructions added to the IQ (excludes non-spec) 269system.cpu.iq.iqNonSpecInstsAdded 34704 # Number of non-speculative instructions added to the IQ 270system.cpu.iq.iqInstsIssued 1836706736 # Number of instructions issued 271system.cpu.iq.iqSquashedInstsIssued 960329 # Number of squashed instructions issued 272system.cpu.iq.iqSquashedInstsExamined 555260187 # Number of squashed instructions iterated over during squash; mainly for profiling 273system.cpu.iq.iqSquashedOperandsExamined 919296135 # Number of squashed operands that are examined and possibly removed from graph 274system.cpu.iq.iqSquashedNonSpecRemoved 34151 # Number of squashed non-spec instructions that were removed 275system.cpu.iq.issued_per_cycle::samples 880638441 # Number of insts issued each cycle 276system.cpu.iq.issued_per_cycle::mean 2.085654 # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::stdev 1.886104 # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::0 249855133 28.37% 28.37% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::1 147643393 16.77% 45.14% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::2 139523467 15.84% 60.98% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::3 137737388 15.64% 76.62% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::4 97163823 11.03% 87.65% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::5 59916022 6.80% 94.46% # Number of insts issued each cycle 285system.cpu.iq.issued_per_cycle::6 34917189 3.96% 98.42% # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::7 11990499 1.36% 99.79% # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::8 1891527 0.21% 100.00% # Number of insts issued each cycle 288system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 289system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 290system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 291system.cpu.iq.issued_per_cycle::total 880638441 # Number of insts issued each cycle 292system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 293system.cpu.iq.fu_full::IntAlu 5040061 32.96% 32.96% # attempts to use FU when none available 294system.cpu.iq.fu_full::IntMult 0 0.00% 32.96% # attempts to use FU when none available 295system.cpu.iq.fu_full::IntDiv 0 0.00% 32.96% # attempts to use FU when none available 296system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.96% # attempts to use FU when none available 297system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.96% # attempts to use FU when none available 298system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.96% # attempts to use FU when none available 299system.cpu.iq.fu_full::FloatMult 0 0.00% 32.96% # attempts to use FU when none available 300system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.96% # attempts to use FU when none available 301system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.96% # attempts to use FU when none available 302system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.96% # attempts to use FU when none available 303system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.96% # attempts to use FU when none available 304system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.96% # attempts to use FU when none available 305system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.96% # attempts to use FU when none available 306system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.96% # attempts to use FU when none available 307system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.96% # attempts to use FU when none available 308system.cpu.iq.fu_full::SimdMult 0 0.00% 32.96% # attempts to use FU when none available 309system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.96% # attempts to use FU when none available 310system.cpu.iq.fu_full::SimdShift 0 0.00% 32.96% # attempts to use FU when none available 311system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.96% # attempts to use FU when none available 312system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.96% # attempts to use FU when none available 313system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.96% # attempts to use FU when none available 314system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.96% # attempts to use FU when none available 315system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.96% # attempts to use FU when none available 316system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.96% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.96% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.96% # attempts to use FU when none available 319system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.96% # attempts to use FU when none available 320system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.96% # attempts to use FU when none available 321system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.96% # attempts to use FU when none available 322system.cpu.iq.fu_full::MemRead 7632140 49.91% 82.87% # attempts to use FU when none available 323system.cpu.iq.fu_full::MemWrite 2619273 17.13% 100.00% # attempts to use FU when none available 324system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 325system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 326system.cpu.iq.FU_type_0::No_OpClass 2704214 0.15% 0.15% # Type of FU issued 327system.cpu.iq.FU_type_0::IntAlu 1211533027 65.96% 66.11% # Type of FU issued 328system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued 329system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued 330system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued 331system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.11% # Type of FU issued 332system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.11% # Type of FU issued 333system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.11% # Type of FU issued 334system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.11% # Type of FU issued 335system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued 348system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued 353system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued 354system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued 355system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued 356system.cpu.iq.FU_type_0::MemRead 444457178 24.20% 90.31% # Type of FU issued 357system.cpu.iq.FU_type_0::MemWrite 178012317 9.69% 100.00% # Type of FU issued 358system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 359system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 360system.cpu.iq.FU_type_0::total 1836706736 # Type of FU issued 361system.cpu.iq.rate 2.053787 # Inst issue rate 362system.cpu.iq.fu_busy_cnt 15291474 # FU busy when requested 363system.cpu.iq.fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst) 364system.cpu.iq.int_inst_queue_reads 4570263035 # Number of integer instruction queue reads 365system.cpu.iq.int_inst_queue_writes 2646020420 # Number of integer instruction queue writes 366system.cpu.iq.int_inst_queue_wakeup_accesses 1794037475 # Number of integer instruction queue wakeup accesses 367system.cpu.iq.fp_inst_queue_reads 40681 # Number of floating instruction queue reads 368system.cpu.iq.fp_inst_queue_writes 76210 # Number of floating instruction queue writes 369system.cpu.iq.fp_inst_queue_wakeup_accesses 9614 # Number of floating instruction queue wakeup accesses 370system.cpu.iq.int_alu_accesses 1849275039 # Number of integer alu accesses 371system.cpu.iq.fp_alu_accesses 18957 # Number of floating point alu accesses 372system.cpu.iew.lsq.thread0.forwLoads 170130474 # Number of loads that had data forwarded from stores 373system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 374system.cpu.iew.lsq.thread0.squashedLoads 144845761 # Number of loads squashed 375system.cpu.iew.lsq.thread0.ignoredResponses 503638 # Number of memory responses ignored because the instruction is squashed 376system.cpu.iew.lsq.thread0.memOrderViolation 274982 # Number of memory ordering violations 377system.cpu.iew.lsq.thread0.squashedStores 61917680 # Number of stores squashed 378system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 379system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 380system.cpu.iew.lsq.thread0.rescheduledLoads 10585 # Number of loads that were rescheduled 381system.cpu.iew.lsq.thread0.cacheBlocked 592 # Number of times an access to memory failed due to the cache being blocked 382system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 383system.cpu.iew.iewSquashCycles 77787898 # Number of cycles IEW is squashing 384system.cpu.iew.iewBlockCycles 17508647 # Number of cycles IEW is blocking 385system.cpu.iew.iewUnblockCycles 2908748 # Number of cycles IEW is unblocking 386system.cpu.iew.iewDispatchedInsts 2090574083 # Number of instructions dispatched to IQ 387system.cpu.iew.iewDispSquashedInsts 2437552 # Number of squashed instructions skipped by dispatch 388system.cpu.iew.iewDispLoadInsts 528947917 # Number of dispatched load instructions 389system.cpu.iew.iewDispStoreInsts 211077865 # Number of dispatched store instructions 390system.cpu.iew.iewDispNonSpecInsts 5687 # Number of dispatched non-speculative instructions 391system.cpu.iew.iewIQFullEvents 1841603 # Number of times the IQ has become full, causing a stall 392system.cpu.iew.iewLSQFullEvents 73588 # Number of times the LSQ has become full, causing a stall 393system.cpu.iew.memOrderViolationEvents 274982 # Number of memory order violations 394system.cpu.iew.predictedTakenIncorrect 10048689 # Number of branches that were predicted taken incorrectly 395system.cpu.iew.predictedNotTakenIncorrect 4929582 # Number of branches that were predicted not taken incorrectly 396system.cpu.iew.branchMispredicts 14978271 # Number of branch mispredicts detected at execute 397system.cpu.iew.iewExecutedInsts 1806703840 # Number of executed instructions 398system.cpu.iew.iewExecLoadInsts 436137965 # Number of load instructions executed 399system.cpu.iew.iewExecSquashedInsts 30002896 # Number of squashed instructions skipped in execute 400system.cpu.iew.exec_swp 0 # number of swp insts executed 401system.cpu.iew.exec_nop 0 # number of nop insts executed 402system.cpu.iew.exec_refs 608784008 # number of memory reference insts executed 403system.cpu.iew.exec_branches 171260555 # Number of branches executed 404system.cpu.iew.exec_stores 172646043 # Number of stores executed 405system.cpu.iew.exec_rate 2.020238 # Inst execution rate 406system.cpu.iew.wb_sent 1801373489 # cumulative count of insts sent to commit 407system.cpu.iew.wb_count 1794047089 # cumulative count of insts written-back 408system.cpu.iew.wb_producers 1362133405 # num instructions producing a value 409system.cpu.iew.wb_consumers 1992639116 # num instructions consuming a value 410system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 411system.cpu.iew.wb_rate 2.006085 # insts written-back per cycle 412system.cpu.iew.wb_fanout 0.683583 # average fanout of values written-back 413system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 414system.cpu.commit.commitSquashedInsts 561620004 # The number of squashed insts skipped by commit 415system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards 416system.cpu.commit.branchMispredicts 14469462 # The number of times a branch was mispredicted 417system.cpu.commit.committed_per_cycle::samples 802850543 # Number of insts commited each cycle 418system.cpu.commit.committed_per_cycle::mean 1.904450 # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::stdev 2.430311 # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::0 304835163 37.97% 37.97% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::1 198905096 24.77% 62.74% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::2 63436109 7.90% 70.65% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::3 92154984 11.48% 82.12% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::4 26044111 3.24% 85.37% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::5 29384573 3.66% 89.03% # Number of insts commited each cycle 427system.cpu.commit.committed_per_cycle::6 9423573 1.17% 90.20% # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::7 10229786 1.27% 91.48% # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::8 68437148 8.52% 100.00% # Number of insts commited each cycle 430system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 431system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 432system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 433system.cpu.commit.committed_per_cycle::total 802850543 # Number of insts commited each cycle 434system.cpu.commit.committedInsts 826877109 # Number of instructions committed 435system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed 436system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 437system.cpu.commit.refs 533262341 # Number of memory references committed 438system.cpu.commit.loads 384102156 # Number of loads committed 439system.cpu.commit.membars 0 # Number of memory barriers committed 440system.cpu.commit.branches 149758583 # Number of branches committed 441system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 442system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. 443system.cpu.commit.function_calls 0 # Number of function calls committed. 444system.cpu.commit.bw_lim_events 68437148 # number cycles where commit BW limit reached 445system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 446system.cpu.rob.rob_reads 2825022098 # The number of ROB reads 447system.cpu.rob.rob_writes 4259228710 # The number of ROB writes 448system.cpu.timesIdled 301112 # Number of times that the entire CPU went into an idle state and unscheduled itself 449system.cpu.idleCycles 13664142 # Total number of cycles that the CPU has spent unscheduled due to idling 450system.cpu.committedInsts 826877109 # Number of Instructions Simulated 451system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated 452system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated 453system.cpu.cpi 1.081542 # CPI: Cycles Per Instruction 454system.cpu.cpi_total 1.081542 # CPI: Total CPI of All Threads 455system.cpu.ipc 0.924606 # IPC: Instructions Per Cycle 456system.cpu.ipc_total 0.924606 # IPC: Total IPC of All Threads 457system.cpu.int_regfile_reads 3392416402 # number of integer regfile reads 458system.cpu.int_regfile_writes 1873878910 # number of integer regfile writes 459system.cpu.fp_regfile_reads 9612 # number of floating regfile reads 460system.cpu.fp_regfile_writes 2 # number of floating regfile writes 461system.cpu.misc_regfile_reads 993805261 # number of misc regfile reads 462system.cpu.icache.replacements 5664 # number of replacements 463system.cpu.icache.tagsinuse 1040.414195 # Cycle average of tags in use 464system.cpu.icache.total_refs 179444520 # Total number of references to valid blocks. 465system.cpu.icache.sampled_refs 7258 # Sample count of references to valid blocks. 466system.cpu.icache.avg_refs 24723.686966 # Average number of references to valid blocks. 467system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 468system.cpu.icache.occ_blocks::cpu.inst 1040.414195 # Average occupied blocks per requestor 469system.cpu.icache.occ_percent::cpu.inst 0.508015 # Average percentage of cache occupancy 470system.cpu.icache.occ_percent::total 0.508015 # Average percentage of cache occupancy 471system.cpu.icache.ReadReq_hits::cpu.inst 179464097 # number of ReadReq hits 472system.cpu.icache.ReadReq_hits::total 179464097 # number of ReadReq hits 473system.cpu.icache.demand_hits::cpu.inst 179464097 # number of demand (read+write) hits 474system.cpu.icache.demand_hits::total 179464097 # number of demand (read+write) hits 475system.cpu.icache.overall_hits::cpu.inst 179464097 # number of overall hits 476system.cpu.icache.overall_hits::total 179464097 # number of overall hits 477system.cpu.icache.ReadReq_misses::cpu.inst 195682 # number of ReadReq misses 478system.cpu.icache.ReadReq_misses::total 195682 # number of ReadReq misses 479system.cpu.icache.demand_misses::cpu.inst 195682 # number of demand (read+write) misses 480system.cpu.icache.demand_misses::total 195682 # number of demand (read+write) misses 481system.cpu.icache.overall_misses::cpu.inst 195682 # number of overall misses 482system.cpu.icache.overall_misses::total 195682 # number of overall misses 483system.cpu.icache.ReadReq_miss_latency::cpu.inst 1231899498 # number of ReadReq miss cycles 484system.cpu.icache.ReadReq_miss_latency::total 1231899498 # number of ReadReq miss cycles 485system.cpu.icache.demand_miss_latency::cpu.inst 1231899498 # number of demand (read+write) miss cycles 486system.cpu.icache.demand_miss_latency::total 1231899498 # number of demand (read+write) miss cycles 487system.cpu.icache.overall_miss_latency::cpu.inst 1231899498 # number of overall miss cycles 488system.cpu.icache.overall_miss_latency::total 1231899498 # number of overall miss cycles 489system.cpu.icache.ReadReq_accesses::cpu.inst 179659779 # number of ReadReq accesses(hits+misses) 490system.cpu.icache.ReadReq_accesses::total 179659779 # number of ReadReq accesses(hits+misses) 491system.cpu.icache.demand_accesses::cpu.inst 179659779 # number of demand (read+write) accesses 492system.cpu.icache.demand_accesses::total 179659779 # number of demand (read+write) accesses 493system.cpu.icache.overall_accesses::cpu.inst 179659779 # number of overall (read+write) accesses 494system.cpu.icache.overall_accesses::total 179659779 # number of overall (read+write) accesses 495system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001089 # miss rate for ReadReq accesses 496system.cpu.icache.ReadReq_miss_rate::total 0.001089 # miss rate for ReadReq accesses 497system.cpu.icache.demand_miss_rate::cpu.inst 0.001089 # miss rate for demand accesses 498system.cpu.icache.demand_miss_rate::total 0.001089 # miss rate for demand accesses 499system.cpu.icache.overall_miss_rate::cpu.inst 0.001089 # miss rate for overall accesses 500system.cpu.icache.overall_miss_rate::total 0.001089 # miss rate for overall accesses 501system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6295.415511 # average ReadReq miss latency 502system.cpu.icache.ReadReq_avg_miss_latency::total 6295.415511 # average ReadReq miss latency 503system.cpu.icache.demand_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency 504system.cpu.icache.demand_avg_miss_latency::total 6295.415511 # average overall miss latency 505system.cpu.icache.overall_avg_miss_latency::cpu.inst 6295.415511 # average overall miss latency 506system.cpu.icache.overall_avg_miss_latency::total 6295.415511 # average overall miss latency 507system.cpu.icache.blocked_cycles::no_mshrs 959 # number of cycles access was blocked 508system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 509system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked 510system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 511system.cpu.icache.avg_blocked_cycles::no_mshrs 56.411765 # average number of cycles each access was blocked 512system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 513system.cpu.icache.fast_writes 0 # number of fast writes performed 514system.cpu.icache.cache_copies 0 # number of cache copies performed 515system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2352 # number of ReadReq MSHR hits 516system.cpu.icache.ReadReq_mshr_hits::total 2352 # number of ReadReq MSHR hits 517system.cpu.icache.demand_mshr_hits::cpu.inst 2352 # number of demand (read+write) MSHR hits 518system.cpu.icache.demand_mshr_hits::total 2352 # number of demand (read+write) MSHR hits 519system.cpu.icache.overall_mshr_hits::cpu.inst 2352 # number of overall MSHR hits 520system.cpu.icache.overall_mshr_hits::total 2352 # number of overall MSHR hits 521system.cpu.icache.ReadReq_mshr_misses::cpu.inst 193330 # number of ReadReq MSHR misses 522system.cpu.icache.ReadReq_mshr_misses::total 193330 # number of ReadReq MSHR misses 523system.cpu.icache.demand_mshr_misses::cpu.inst 193330 # number of demand (read+write) MSHR misses 524system.cpu.icache.demand_mshr_misses::total 193330 # number of demand (read+write) MSHR misses 525system.cpu.icache.overall_mshr_misses::cpu.inst 193330 # number of overall MSHR misses 526system.cpu.icache.overall_mshr_misses::total 193330 # number of overall MSHR misses 527system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 781617498 # number of ReadReq MSHR miss cycles 528system.cpu.icache.ReadReq_mshr_miss_latency::total 781617498 # number of ReadReq MSHR miss cycles 529system.cpu.icache.demand_mshr_miss_latency::cpu.inst 781617498 # number of demand (read+write) MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::total 781617498 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.overall_mshr_miss_latency::cpu.inst 781617498 # number of overall MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::total 781617498 # number of overall MSHR miss cycles 533system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for ReadReq accesses 534system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001076 # mshr miss rate for ReadReq accesses 535system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for demand accesses 536system.cpu.icache.demand_mshr_miss_rate::total 0.001076 # mshr miss rate for demand accesses 537system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001076 # mshr miss rate for overall accesses 538system.cpu.icache.overall_mshr_miss_rate::total 0.001076 # mshr miss rate for overall accesses 539system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4042.918833 # average ReadReq mshr miss latency 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4042.918833 # average ReadReq mshr miss latency 541system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency 543system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4042.918833 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::total 4042.918833 # average overall mshr miss latency 545system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 546system.cpu.dcache.replacements 2529793 # number of replacements 547system.cpu.dcache.tagsinuse 4087.981859 # Cycle average of tags in use 548system.cpu.dcache.total_refs 410271543 # Total number of references to valid blocks. 549system.cpu.dcache.sampled_refs 2533889 # Sample count of references to valid blocks. 550system.cpu.dcache.avg_refs 161.913779 # Average number of references to valid blocks. 551system.cpu.dcache.warmup_cycle 1794023000 # Cycle when the warmup percentage was hit. 552system.cpu.dcache.occ_blocks::cpu.data 4087.981859 # Average occupied blocks per requestor 553system.cpu.dcache.occ_percent::cpu.data 0.998042 # Average percentage of cache occupancy 554system.cpu.dcache.occ_percent::total 0.998042 # Average percentage of cache occupancy 555system.cpu.dcache.ReadReq_hits::cpu.data 261613799 # number of ReadReq hits 556system.cpu.dcache.ReadReq_hits::total 261613799 # number of ReadReq hits 557system.cpu.dcache.WriteReq_hits::cpu.data 148186041 # number of WriteReq hits 558system.cpu.dcache.WriteReq_hits::total 148186041 # number of WriteReq hits 559system.cpu.dcache.demand_hits::cpu.data 409799840 # number of demand (read+write) hits 560system.cpu.dcache.demand_hits::total 409799840 # number of demand (read+write) hits 561system.cpu.dcache.overall_hits::cpu.data 409799840 # number of overall hits 562system.cpu.dcache.overall_hits::total 409799840 # number of overall hits 563system.cpu.dcache.ReadReq_misses::cpu.data 2816252 # number of ReadReq misses 564system.cpu.dcache.ReadReq_misses::total 2816252 # number of ReadReq misses 565system.cpu.dcache.WriteReq_misses::cpu.data 974160 # number of WriteReq misses 566system.cpu.dcache.WriteReq_misses::total 974160 # number of WriteReq misses 567system.cpu.dcache.demand_misses::cpu.data 3790412 # number of demand (read+write) misses 568system.cpu.dcache.demand_misses::total 3790412 # number of demand (read+write) misses 569system.cpu.dcache.overall_misses::cpu.data 3790412 # number of overall misses 570system.cpu.dcache.overall_misses::total 3790412 # number of overall misses 571system.cpu.dcache.ReadReq_miss_latency::cpu.data 49180630000 # number of ReadReq miss cycles 572system.cpu.dcache.ReadReq_miss_latency::total 49180630000 # number of ReadReq miss cycles 573system.cpu.dcache.WriteReq_miss_latency::cpu.data 23742046000 # number of WriteReq miss cycles 574system.cpu.dcache.WriteReq_miss_latency::total 23742046000 # number of WriteReq miss cycles 575system.cpu.dcache.demand_miss_latency::cpu.data 72922676000 # number of demand (read+write) miss cycles 576system.cpu.dcache.demand_miss_latency::total 72922676000 # number of demand (read+write) miss cycles 577system.cpu.dcache.overall_miss_latency::cpu.data 72922676000 # number of overall miss cycles 578system.cpu.dcache.overall_miss_latency::total 72922676000 # number of overall miss cycles 579system.cpu.dcache.ReadReq_accesses::cpu.data 264430051 # number of ReadReq accesses(hits+misses) 580system.cpu.dcache.ReadReq_accesses::total 264430051 # number of ReadReq accesses(hits+misses) 581system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) 582system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) 583system.cpu.dcache.demand_accesses::cpu.data 413590252 # number of demand (read+write) accesses 584system.cpu.dcache.demand_accesses::total 413590252 # number of demand (read+write) accesses 585system.cpu.dcache.overall_accesses::cpu.data 413590252 # number of overall (read+write) accesses 586system.cpu.dcache.overall_accesses::total 413590252 # number of overall (read+write) accesses 587system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010650 # miss rate for ReadReq accesses 588system.cpu.dcache.ReadReq_miss_rate::total 0.010650 # miss rate for ReadReq accesses 589system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006531 # miss rate for WriteReq accesses 590system.cpu.dcache.WriteReq_miss_rate::total 0.006531 # miss rate for WriteReq accesses 591system.cpu.dcache.demand_miss_rate::cpu.data 0.009165 # miss rate for demand accesses 592system.cpu.dcache.demand_miss_rate::total 0.009165 # miss rate for demand accesses 593system.cpu.dcache.overall_miss_rate::cpu.data 0.009165 # miss rate for overall accesses 594system.cpu.dcache.overall_miss_rate::total 0.009165 # miss rate for overall accesses 595system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17463.149605 # average ReadReq miss latency 596system.cpu.dcache.ReadReq_avg_miss_latency::total 17463.149605 # average ReadReq miss latency 597system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24371.813665 # average WriteReq miss latency 598system.cpu.dcache.WriteReq_avg_miss_latency::total 24371.813665 # average WriteReq miss latency 599system.cpu.dcache.demand_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency 600system.cpu.dcache.demand_avg_miss_latency::total 19238.720224 # average overall miss latency 601system.cpu.dcache.overall_avg_miss_latency::cpu.data 19238.720224 # average overall miss latency 602system.cpu.dcache.overall_avg_miss_latency::total 19238.720224 # average overall miss latency 603system.cpu.dcache.blocked_cycles::no_mshrs 6306 # number of cycles access was blocked 604system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 605system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked 606system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 607system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.397914 # average number of cycles each access was blocked 608system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 609system.cpu.dcache.fast_writes 0 # number of fast writes performed 610system.cpu.dcache.cache_copies 0 # number of cache copies performed 611system.cpu.dcache.writebacks::writebacks 2331455 # number of writebacks 612system.cpu.dcache.writebacks::total 2331455 # number of writebacks 613system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1053646 # number of ReadReq MSHR hits 614system.cpu.dcache.ReadReq_mshr_hits::total 1053646 # number of ReadReq MSHR hits 615system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16861 # number of WriteReq MSHR hits 616system.cpu.dcache.WriteReq_mshr_hits::total 16861 # number of WriteReq MSHR hits 617system.cpu.dcache.demand_mshr_hits::cpu.data 1070507 # number of demand (read+write) MSHR hits 618system.cpu.dcache.demand_mshr_hits::total 1070507 # number of demand (read+write) MSHR hits 619system.cpu.dcache.overall_mshr_hits::cpu.data 1070507 # number of overall MSHR hits 620system.cpu.dcache.overall_mshr_hits::total 1070507 # number of overall MSHR hits 621system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762606 # number of ReadReq MSHR misses 622system.cpu.dcache.ReadReq_mshr_misses::total 1762606 # number of ReadReq MSHR misses 623system.cpu.dcache.WriteReq_mshr_misses::cpu.data 957299 # number of WriteReq MSHR misses 624system.cpu.dcache.WriteReq_mshr_misses::total 957299 # number of WriteReq MSHR misses 625system.cpu.dcache.demand_mshr_misses::cpu.data 2719905 # number of demand (read+write) MSHR misses 626system.cpu.dcache.demand_mshr_misses::total 2719905 # number of demand (read+write) MSHR misses 627system.cpu.dcache.overall_mshr_misses::cpu.data 2719905 # number of overall MSHR misses 628system.cpu.dcache.overall_mshr_misses::total 2719905 # number of overall MSHR misses 629system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26907249500 # number of ReadReq MSHR miss cycles 630system.cpu.dcache.ReadReq_mshr_miss_latency::total 26907249500 # number of ReadReq MSHR miss cycles 631system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21627560000 # number of WriteReq MSHR miss cycles 632system.cpu.dcache.WriteReq_mshr_miss_latency::total 21627560000 # number of WriteReq MSHR miss cycles 633system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48534809500 # number of demand (read+write) MSHR miss cycles 634system.cpu.dcache.demand_mshr_miss_latency::total 48534809500 # number of demand (read+write) MSHR miss cycles 635system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48534809500 # number of overall MSHR miss cycles 636system.cpu.dcache.overall_mshr_miss_latency::total 48534809500 # number of overall MSHR miss cycles 637system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006666 # mshr miss rate for ReadReq accesses 638system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006666 # mshr miss rate for ReadReq accesses 639system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006418 # mshr miss rate for WriteReq accesses 640system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006418 # mshr miss rate for WriteReq accesses 641system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006576 # mshr miss rate for demand accesses 642system.cpu.dcache.demand_mshr_miss_rate::total 0.006576 # mshr miss rate for demand accesses 643system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006576 # mshr miss rate for overall accesses 644system.cpu.dcache.overall_mshr_miss_rate::total 0.006576 # mshr miss rate for overall accesses 645system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15265.606437 # average ReadReq mshr miss latency 646system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15265.606437 # average ReadReq mshr miss latency 647system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22592.272634 # average WriteReq mshr miss latency 648system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22592.272634 # average WriteReq mshr miss latency 649system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17844.303202 # average overall mshr miss latency 650system.cpu.dcache.demand_avg_mshr_miss_latency::total 17844.303202 # average overall mshr miss latency 651system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17844.303202 # average overall mshr miss latency 652system.cpu.dcache.overall_avg_mshr_miss_latency::total 17844.303202 # average overall mshr miss latency 653system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 654system.cpu.l2cache.replacements 352840 # number of replacements 655system.cpu.l2cache.tagsinuse 29572.307883 # Cycle average of tags in use 656system.cpu.l2cache.total_refs 3696862 # Total number of references to valid blocks. 657system.cpu.l2cache.sampled_refs 385170 # Sample count of references to valid blocks. 658system.cpu.l2cache.avg_refs 9.598001 # Average number of references to valid blocks. 659system.cpu.l2cache.warmup_cycle 211000207000 # Cycle when the warmup percentage was hit. 660system.cpu.l2cache.occ_blocks::writebacks 21064.458635 # Average occupied blocks per requestor 661system.cpu.l2cache.occ_blocks::cpu.inst 238.476437 # Average occupied blocks per requestor 662system.cpu.l2cache.occ_blocks::cpu.data 8269.372811 # Average occupied blocks per requestor 663system.cpu.l2cache.occ_percent::writebacks 0.642836 # Average percentage of cache occupancy 664system.cpu.l2cache.occ_percent::cpu.inst 0.007278 # Average percentage of cache occupancy 665system.cpu.l2cache.occ_percent::cpu.data 0.252361 # Average percentage of cache occupancy 666system.cpu.l2cache.occ_percent::total 0.902475 # Average percentage of cache occupancy 667system.cpu.l2cache.ReadReq_hits::cpu.inst 3978 # number of ReadReq hits 668system.cpu.l2cache.ReadReq_hits::cpu.data 1586642 # number of ReadReq hits 669system.cpu.l2cache.ReadReq_hits::total 1590620 # number of ReadReq hits 670system.cpu.l2cache.Writeback_hits::writebacks 2331455 # number of Writeback hits 671system.cpu.l2cache.Writeback_hits::total 2331455 # number of Writeback hits 672system.cpu.l2cache.UpgradeReq_hits::cpu.data 1524 # number of UpgradeReq hits 673system.cpu.l2cache.UpgradeReq_hits::total 1524 # number of UpgradeReq hits 674system.cpu.l2cache.ReadExReq_hits::cpu.data 564916 # number of ReadExReq hits 675system.cpu.l2cache.ReadExReq_hits::total 564916 # number of ReadExReq hits 676system.cpu.l2cache.demand_hits::cpu.inst 3978 # number of demand (read+write) hits 677system.cpu.l2cache.demand_hits::cpu.data 2151558 # number of demand (read+write) hits 678system.cpu.l2cache.demand_hits::total 2155536 # number of demand (read+write) hits 679system.cpu.l2cache.overall_hits::cpu.inst 3978 # number of overall hits 680system.cpu.l2cache.overall_hits::cpu.data 2151558 # number of overall hits 681system.cpu.l2cache.overall_hits::total 2155536 # number of overall hits 682system.cpu.l2cache.ReadReq_misses::cpu.inst 3236 # number of ReadReq misses 683system.cpu.l2cache.ReadReq_misses::cpu.data 175667 # number of ReadReq misses 684system.cpu.l2cache.ReadReq_misses::total 178903 # number of ReadReq misses 685system.cpu.l2cache.UpgradeReq_misses::cpu.data 184491 # number of UpgradeReq misses 686system.cpu.l2cache.UpgradeReq_misses::total 184491 # number of UpgradeReq misses 687system.cpu.l2cache.ReadExReq_misses::cpu.data 206666 # number of ReadExReq misses 688system.cpu.l2cache.ReadExReq_misses::total 206666 # number of ReadExReq misses 689system.cpu.l2cache.demand_misses::cpu.inst 3236 # number of demand (read+write) misses 690system.cpu.l2cache.demand_misses::cpu.data 382333 # number of demand (read+write) misses 691system.cpu.l2cache.demand_misses::total 385569 # number of demand (read+write) misses 692system.cpu.l2cache.overall_misses::cpu.inst 3236 # number of overall misses 693system.cpu.l2cache.overall_misses::cpu.data 382333 # number of overall misses 694system.cpu.l2cache.overall_misses::total 385569 # number of overall misses 695system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187805000 # number of ReadReq miss cycles 696system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9240729957 # number of ReadReq miss cycles 697system.cpu.l2cache.ReadReq_miss_latency::total 9428534957 # number of ReadReq miss cycles 698system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 7282500 # number of UpgradeReq miss cycles 699system.cpu.l2cache.UpgradeReq_miss_latency::total 7282500 # number of UpgradeReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10987147000 # number of ReadExReq miss cycles 701system.cpu.l2cache.ReadExReq_miss_latency::total 10987147000 # number of ReadExReq miss cycles 702system.cpu.l2cache.demand_miss_latency::cpu.inst 187805000 # number of demand (read+write) miss cycles 703system.cpu.l2cache.demand_miss_latency::cpu.data 20227876957 # number of demand (read+write) miss cycles 704system.cpu.l2cache.demand_miss_latency::total 20415681957 # number of demand (read+write) miss cycles 705system.cpu.l2cache.overall_miss_latency::cpu.inst 187805000 # number of overall miss cycles 706system.cpu.l2cache.overall_miss_latency::cpu.data 20227876957 # number of overall miss cycles 707system.cpu.l2cache.overall_miss_latency::total 20415681957 # number of overall miss cycles 708system.cpu.l2cache.ReadReq_accesses::cpu.inst 7214 # number of ReadReq accesses(hits+misses) 709system.cpu.l2cache.ReadReq_accesses::cpu.data 1762309 # number of ReadReq accesses(hits+misses) 710system.cpu.l2cache.ReadReq_accesses::total 1769523 # number of ReadReq accesses(hits+misses) 711system.cpu.l2cache.Writeback_accesses::writebacks 2331455 # number of Writeback accesses(hits+misses) 712system.cpu.l2cache.Writeback_accesses::total 2331455 # number of Writeback accesses(hits+misses) 713system.cpu.l2cache.UpgradeReq_accesses::cpu.data 186015 # number of UpgradeReq accesses(hits+misses) 714system.cpu.l2cache.UpgradeReq_accesses::total 186015 # number of UpgradeReq accesses(hits+misses) 715system.cpu.l2cache.ReadExReq_accesses::cpu.data 771582 # number of ReadExReq accesses(hits+misses) 716system.cpu.l2cache.ReadExReq_accesses::total 771582 # number of ReadExReq accesses(hits+misses) 717system.cpu.l2cache.demand_accesses::cpu.inst 7214 # number of demand (read+write) accesses 718system.cpu.l2cache.demand_accesses::cpu.data 2533891 # number of demand (read+write) accesses 719system.cpu.l2cache.demand_accesses::total 2541105 # number of demand (read+write) accesses 720system.cpu.l2cache.overall_accesses::cpu.inst 7214 # number of overall (read+write) accesses 721system.cpu.l2cache.overall_accesses::cpu.data 2533891 # number of overall (read+write) accesses 722system.cpu.l2cache.overall_accesses::total 2541105 # number of overall (read+write) accesses 723system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448572 # miss rate for ReadReq accesses 724system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099680 # miss rate for ReadReq accesses 725system.cpu.l2cache.ReadReq_miss_rate::total 0.101102 # miss rate for ReadReq accesses 726system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991807 # miss rate for UpgradeReq accesses 727system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991807 # miss rate for UpgradeReq accesses 728system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.267847 # miss rate for ReadExReq accesses 729system.cpu.l2cache.ReadExReq_miss_rate::total 0.267847 # miss rate for ReadExReq accesses 730system.cpu.l2cache.demand_miss_rate::cpu.inst 0.448572 # miss rate for demand accesses 731system.cpu.l2cache.demand_miss_rate::cpu.data 0.150888 # miss rate for demand accesses 732system.cpu.l2cache.demand_miss_rate::total 0.151733 # miss rate for demand accesses 733system.cpu.l2cache.overall_miss_rate::cpu.inst 0.448572 # miss rate for overall accesses 734system.cpu.l2cache.overall_miss_rate::cpu.data 0.150888 # miss rate for overall accesses 735system.cpu.l2cache.overall_miss_rate::total 0.151733 # miss rate for overall accesses 736system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58036.155748 # average ReadReq miss latency 737system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52603.676029 # average ReadReq miss latency 738system.cpu.l2cache.ReadReq_avg_miss_latency::total 52701.938799 # average ReadReq miss latency 739system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39.473470 # average UpgradeReq miss latency 740system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39.473470 # average UpgradeReq miss latency 741system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53163.786012 # average ReadExReq miss latency 742system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53163.786012 # average ReadExReq miss latency 743system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58036.155748 # average overall miss latency 744system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52906.437469 # average overall miss latency 745system.cpu.l2cache.demand_avg_miss_latency::total 52949.490122 # average overall miss latency 746system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58036.155748 # average overall miss latency 747system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52906.437469 # average overall miss latency 748system.cpu.l2cache.overall_avg_miss_latency::total 52949.490122 # average overall miss latency 749system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 750system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 752system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 753system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 754system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 755system.cpu.l2cache.fast_writes 0 # number of fast writes performed 756system.cpu.l2cache.cache_copies 0 # number of cache copies performed 757system.cpu.l2cache.writebacks::writebacks 293537 # number of writebacks 758system.cpu.l2cache.writebacks::total 293537 # number of writebacks 759system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3236 # number of ReadReq MSHR misses 760system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175667 # number of ReadReq MSHR misses 761system.cpu.l2cache.ReadReq_mshr_misses::total 178903 # number of ReadReq MSHR misses 762system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 184491 # number of UpgradeReq MSHR misses 763system.cpu.l2cache.UpgradeReq_mshr_misses::total 184491 # number of UpgradeReq MSHR misses 764system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206666 # number of ReadExReq MSHR misses 765system.cpu.l2cache.ReadExReq_mshr_misses::total 206666 # number of ReadExReq MSHR misses 766system.cpu.l2cache.demand_mshr_misses::cpu.inst 3236 # number of demand (read+write) MSHR misses 767system.cpu.l2cache.demand_mshr_misses::cpu.data 382333 # number of demand (read+write) MSHR misses 768system.cpu.l2cache.demand_mshr_misses::total 385569 # number of demand (read+write) MSHR misses 769system.cpu.l2cache.overall_mshr_misses::cpu.inst 3236 # number of overall MSHR misses 770system.cpu.l2cache.overall_mshr_misses::cpu.data 382333 # number of overall MSHR misses 771system.cpu.l2cache.overall_mshr_misses::total 385569 # number of overall MSHR misses 772system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 146938362 # number of ReadReq MSHR miss cycles 773system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6979134954 # number of ReadReq MSHR miss cycles 774system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7126073316 # number of ReadReq MSHR miss cycles 775system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1849956331 # number of UpgradeReq MSHR miss cycles 776system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1849956331 # number of UpgradeReq MSHR miss cycles 777system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8352740653 # number of ReadExReq MSHR miss cycles 778system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8352740653 # number of ReadExReq MSHR miss cycles 779system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 146938362 # number of demand (read+write) MSHR miss cycles 780system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15331875607 # number of demand (read+write) MSHR miss cycles 781system.cpu.l2cache.demand_mshr_miss_latency::total 15478813969 # number of demand (read+write) MSHR miss cycles 782system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 146938362 # number of overall MSHR miss cycles 783system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15331875607 # number of overall MSHR miss cycles 784system.cpu.l2cache.overall_mshr_miss_latency::total 15478813969 # number of overall MSHR miss cycles 785system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for ReadReq accesses 786system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099680 # mshr miss rate for ReadReq accesses 787system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101102 # mshr miss rate for ReadReq accesses 788system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991807 # mshr miss rate for UpgradeReq accesses 789system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991807 # mshr miss rate for UpgradeReq accesses 790system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.267847 # mshr miss rate for ReadExReq accesses 791system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.267847 # mshr miss rate for ReadExReq accesses 792system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for demand accesses 793system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150888 # mshr miss rate for demand accesses 794system.cpu.l2cache.demand_mshr_miss_rate::total 0.151733 # mshr miss rate for demand accesses 795system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448572 # mshr miss rate for overall accesses 796system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150888 # mshr miss rate for overall accesses 797system.cpu.l2cache.overall_mshr_miss_rate::total 0.151733 # mshr miss rate for overall accesses 798system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45407.404821 # average ReadReq mshr miss latency 799system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39729.345603 # average ReadReq mshr miss latency 800system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39832.050418 # average ReadReq mshr miss latency 801system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.352722 # average UpgradeReq mshr miss latency 802system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.352722 # average UpgradeReq mshr miss latency 803system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40416.617407 # average ReadExReq mshr miss latency 804system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40416.617407 # average ReadExReq mshr miss latency 805system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45407.404821 # average overall mshr miss latency 806system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40100.843001 # average overall mshr miss latency 807system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40145.379865 # average overall mshr miss latency 808system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45407.404821 # average overall mshr miss latency 809system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40100.843001 # average overall mshr miss latency 810system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40145.379865 # average overall mshr miss latency 811system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 812 813---------- End Simulation Statistics ---------- 814